EP2283514A1 - Formation d une jonction sur des plaquettes substrats en utilisant des nanoparticules du groupe iv - Google Patents

Formation d une jonction sur des plaquettes substrats en utilisant des nanoparticules du groupe iv

Info

Publication number
EP2283514A1
EP2283514A1 EP08873989A EP08873989A EP2283514A1 EP 2283514 A1 EP2283514 A1 EP 2283514A1 EP 08873989 A EP08873989 A EP 08873989A EP 08873989 A EP08873989 A EP 08873989A EP 2283514 A1 EP2283514 A1 EP 2283514A1
Authority
EP
European Patent Office
Prior art keywords
dopant
thin film
wafer
temperature
nanoparticles
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08873989A
Other languages
German (de)
English (en)
Inventor
Mason Terry
Homer Antoniadis
Dmitry Poplavskyy
Maxim Kelman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Innovalight Inc
Original Assignee
Innovalight Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Innovalight Inc filed Critical Innovalight Inc
Publication of EP2283514A1 publication Critical patent/EP2283514A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02623—Liquid deposition
    • H01L21/02628—Liquid deposition using solutions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H01L21/2256—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides through the applied layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • CVD chemical vapor deposition
  • a substrate which can be an insulator, a semiconductor, or metal
  • one or more volatile precursors which react and/or decompose on the substrate surface to produce a doped film.
  • CVD is expensive since it requires specialized and expensive semiconductor manufacturing equipment.
  • CVD also tends to be very slow, as the film layers are built up a single atom at a time.
  • Other common doping techniques include gas phase doping.
  • the cells to be diffused, loaded in quartz boats, are placed in a quartz tube with resistance heating and held at the processing temperature.
  • the cells enter and exit the furnace through one end, while gases are fed through the opposite one.
  • Dopant itself can be supplied in this way, typically by bubbling nitrogen through liquid dopant precursor before injection into the furnace.
  • Solid dopant sources are also compatible with furnace processing. Five to fifteen minutes at temperatures in the range from about 900 0 C to about 950 0 C can be considered representative.
  • the channel of a FET is generally doped to reproduce either an n-type semiconductor or a p-type semiconductor.
  • the drain and source may be doped of opposite type to the channel.
  • FETs of different type such as N-MOSFET and P-MOSFET, may be further aggregated into larger doped regions on the substrate called P-wells and N-wells to simplify the device layout. That is, N- MOSFET transistors may be aggregated in P-wells, while P-MOSFET transistors may be aggregated in N-wells. Consequently, nanoparticle ink may be used to define patterns that can be annealed to form N-wells and P-wells. More details may be found in U.S. Patent App. No. 11/954,784, filed December 12, 2007, the entirety of which is incorporated herein by reference.
  • the nanoparticle porous compact was processed at 1000 0 C for 20 seconds (sample 1) and 300 seconds (sample 2) in a rapid-thermal-processing tool to sinter the n+ particles and to diffuse dopants into the wafer. Subsequently, a 100 nm capping layer of aluminum was thermally evaporated on top of the sintered layer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Electromagnetism (AREA)
  • Photovoltaic Devices (AREA)

Abstract

L’invention concerne un procédé de formation d’une région de diffusion. Le procédé comprend le dépôt d’une encre à nanoparticules sur une surface d’une plaquette pour former un film mince non densifié. L’encre à nanoparticules contient un ensemble de nanoparticules, au moins certaines nanoparticules de l’ensemble de nanoparticules contenant des atomes dopants. Le procédé comprend également le chauffage du film mince non densifié à une première température et pendant une première durée pour éliminer un solvant de l’encre à nanoparticules déposée; et le chauffage du film mince non densifié à une seconde température et pendant une seconde durée pour former un film mince densifié, au moins certains des atomes dopants se diffusant dans la plaquette pour former la région de diffusion.
EP08873989A 2008-04-25 2008-04-25 Formation d une jonction sur des plaquettes substrats en utilisant des nanoparticules du groupe iv Withdrawn EP2283514A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2008/061611 WO2009131587A1 (fr) 2008-04-25 2008-04-25 Formation d’une jonction sur des plaquettes substrats en utilisant des nanoparticules du groupe iv

Publications (1)

Publication Number Publication Date
EP2283514A1 true EP2283514A1 (fr) 2011-02-16

Family

ID=40140025

Family Applications (1)

Application Number Title Priority Date Filing Date
EP08873989A Withdrawn EP2283514A1 (fr) 2008-04-25 2008-04-25 Formation d une jonction sur des plaquettes substrats en utilisant des nanoparticules du groupe iv

Country Status (3)

Country Link
EP (1) EP2283514A1 (fr)
CN (1) CN102047389B (fr)
WO (1) WO2009131587A1 (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101675531B (zh) 2007-02-16 2013-03-06 纳克公司 太阳能电池结构、光生伏打模块及对应的工艺
TWI559372B (zh) * 2010-04-06 2016-11-21 薄膜電子Ａｓａ公司 磊晶結構、其形成方法及含此結構之元件
US8377738B2 (en) * 2010-07-01 2013-02-19 Sunpower Corporation Fabrication of solar cells with counter doping prevention
US8912083B2 (en) 2011-01-31 2014-12-16 Nanogram Corporation Silicon substrates with doped surface contacts formed from doped silicon inks and corresponding processes
CN102347223B (zh) * 2011-09-30 2013-04-24 浙江大学 一种利用胶态硅纳米颗粒对硅片进行掺杂的方法
US8822262B2 (en) * 2011-12-22 2014-09-02 Sunpower Corporation Fabricating solar cells with silicon nanoparticles
EP2833391A4 (fr) * 2012-03-30 2015-04-22 Teijin Ltd Laminat semi-conducteur et procédé de fabrication correspondant, procédé de fabrication de dispositif semi-conducteur, dispositif semi-conducteur, composition de dopant, couche d'injection de dopant, et procédé de réalisation de couche dopée
EP2787541B1 (fr) 2013-04-03 2022-08-31 LG Electronics, Inc. Cellule solaire
KR102219804B1 (ko) 2014-11-04 2021-02-24 엘지전자 주식회사 태양 전지 및 그의 제조 방법
EP3026713B1 (fr) 2014-11-28 2019-03-27 LG Electronics Inc. Cellule solaire et son procédé de fabrication
KR102272433B1 (ko) 2015-06-30 2021-07-05 엘지전자 주식회사 태양 전지 및 이의 제조 방법
KR102257824B1 (ko) * 2016-12-05 2021-05-28 엘지전자 주식회사 태양 전지 제조 방법
US11404270B2 (en) * 2018-11-30 2022-08-02 Texas Instruments Incorporated Microelectronic device substrate formed by additive process
US10861715B2 (en) 2018-12-28 2020-12-08 Texas Instruments Incorporated 3D printed semiconductor package
US10910465B2 (en) 2018-12-28 2021-02-02 Texas Instruments Incorporated 3D printed semiconductor package

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003188393A (ja) * 2001-12-18 2003-07-04 Sharp Corp 太陽電池の製造方法
JP2004221149A (ja) * 2003-01-10 2004-08-05 Hitachi Ltd 太陽電池の製造方法
DE102004031950A1 (de) * 2003-06-26 2005-02-10 Kyocera Corp. Halbleiter/Elektroden-Kontaktstruktur und eine solche verwendendes Halbleiterbauteil
CN1331194C (zh) * 2004-06-30 2007-08-08 吉林大学 一种具有金属上扩散层的金属诱导多晶硅薄膜制造方法
US20080078441A1 (en) * 2006-09-28 2008-04-03 Dmitry Poplavskyy Semiconductor devices and methods from group iv nanoparticle materials

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2009131587A1 *

Also Published As

Publication number Publication date
WO2009131587A1 (fr) 2009-10-29
CN102047389A (zh) 2011-05-04
CN102047389B (zh) 2013-06-19

Similar Documents

Publication Publication Date Title
US7923368B2 (en) Junction formation on wafer substrates using group IV nanoparticles
WO2009131587A1 (fr) Formation d’une jonction sur des plaquettes substrats en utilisant des nanoparticules du groupe iv
EP2191513B1 (fr) Jonctions de nanoparticules de groupe iv et dispositifs issus de celles-ci
US7851336B2 (en) Method of forming a passivated densified nanoparticle thin film on a substrate
TWI575764B (zh) 具有寬能帶間隙半導體材料之射極區的太陽能電池
CN107658212B (zh) 半导体层叠体、半导体装置，以及它们的制造方法
JP6552011B2 (ja) イオン注入を使用した太陽電池のエミッタ領域の製造
US8394658B2 (en) Methods of using a silicon nanoparticle fluid to control in situ a set of dopant diffusion profiles
JP2013512570A (ja) １組のドーパント拡散プロフィールをインサイチュに制御するために１組のシリコンナノ粒子液体を使用する方法
CN105304749A (zh) 太阳能电池及其制造方法
CN111769179A (zh) 制造太阳能电池的发射极区域的方法
JP2013518442A (ja) シリコン含有粒子を用いて多重ドープ接合を形成する方法
EP1882275A1 (fr) Procede permettant de produire des cellules photovoltaiques
WO2010046284A1 (fr) Procédé de fabrication de dispositifs semi-conducteurs, dispositif semi-conducteur et installation de fabrication de dispositifs semi-conducteurs
EP2448002B1 (fr) Structure de couche de passivation de dispositif semi-conducteur et procédé de formation associé
WO2015130334A1 (fr) Cellules solaires au silicium avec des émetteurs épitaxiaux
WO2015130672A1 (fr) Cellules solaires au silicium à émetteurs épitaxiaux
US9559236B2 (en) Solar cell fabricated by simplified deposition process

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20101122

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA MK RS

RIN1 Information on inventor provided before grant (corrected)

Inventor name: KELMAN, MAXIM

Inventor name: POPLAVSKYY, DMITRY

Inventor name: ANTONIADIS, HOMER

Inventor name: TERRY, MASON

DAX Request for extension of the european patent (deleted)
17Q First examination report despatched

Effective date: 20120914

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20141101