EP2260623A2 - Structure de rafales monoporteuse pour une égalisation et un suivi de rétroaction de décision - Google Patents

Structure de rafales monoporteuse pour une égalisation et un suivi de rétroaction de décision

Info

Publication number
EP2260623A2
EP2260623A2 EP09723201A EP09723201A EP2260623A2 EP 2260623 A2 EP2260623 A2 EP 2260623A2 EP 09723201 A EP09723201 A EP 09723201A EP 09723201 A EP09723201 A EP 09723201A EP 2260623 A2 EP2260623 A2 EP 2260623A2
Authority
EP
European Patent Office
Prior art keywords
data
channel
sequences
blocks
data block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP09723201A
Other languages
German (de)
English (en)
Inventor
Ismail Lakkis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of EP2260623A2 publication Critical patent/EP2260623A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/0335—Arrangements for removing intersymbol interference characterised by the type of transmission
    • H04L2025/03375—Passband transmission
    • H04L2025/03414—Multicarrier
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
    • H04L2025/03439—Fixed structures
    • H04L2025/03445—Time domain
    • H04L2025/03471—Tapped delay lines
    • H04L2025/03484—Tapped delay lines time-recursive
    • H04L2025/0349—Tapped delay lines time-recursive as a feedback filter

Definitions

  • Certain aspects of the present disclosure generally relate to a wireless communication and, more particularly, to physical-layer signal processing in a wireless communication system.
  • An ultra- wideband (UWB) Physical Layer (PHY) can be used for millimeter wave communications (e.g., communications with carrier frequency of approximately 60 GHz).
  • a dual-mode UWB PHY supporting single carrier and Orthogonal Frequency Division Multiplexing (OFDM) modulation can employ a common mode.
  • the common mode is a single-carrier mode used by both single-carrier and OFDM devices for beaconing, network-control signaling, and base-rate data communications.
  • the common mode is typically required for interoperability between different devices and different networks.
  • the Institute of Electrical and Electronics Engineers (IEEE) 802.15.3c standard is intended to support a millimeter-wave-based PHY as an alternative for the existing 802.15.3 Wireless Personal Area Network (WPAN) standard 802.15.3-2003.
  • This particular millimeter-wave WPAN should operate in a new and clear band including 57-64 GHz unlicensed band specified by the Federal Communications Commission (FCC).
  • the millimeter-wave WPAN should allow high coexistence (i.e., close physical spacing) with all other microwave systems in the 802.15 family of WPANs.
  • the millimeter- wave WPAN should support high data rate applications (i.e., at least 1 Gbps data rates), such as high speed internet access, streaming video, etc. Very high data rates in excess of 2 Gbps may be provided for simultaneous time dependent applications such as real time multiple High Definition Television (HDTV) video streams.
  • HDTV High Definition Television
  • a frame format for UWB single-carrier data communications typically comprises a known sequence followed by a data portion.
  • the known sequence may be a Golay code, which can be used by a receiver for tracking, channel estimation, detection, and channel decoding.
  • Signal detection at the receiver can be based on decision feedback equalization (DFE) or some other equalization technique.
  • DFE decision feedback equalization
  • a clock frequency employed by a part of receiver dedicated for equalization typically operates at an integer-multiple of an input signal's data rate. For very high data rates (e.g., 1728 MHz, which has been adopted in the IEEE 802.15.3c standard) it is impractical to operate such high clock frequencies. In addition, power dissipation can be prohibitively high in this case.
  • Certain aspects of the present disclosure provide a method for wireless communications.
  • Certain aspects of the present disclosure provide a method for wireless communications.
  • the method generally includes receiving at least one data block of a data stream on a channel with one or more paths, each of the at least one data block having known sequences of data between sub-blocks of the data block, obtaining a channel estimate for at least one path of the channel, and performing multiple equalizations in parallel, each equalization utilizing the channel estimate, at least one of the known sequences, and at least one of the sub-blocks.
  • the apparatus generally includes a receiver for receiving at least one data block of a data stream on a channel with one or more paths, each of the at least one data block having known sequences of data between sub-blocks of the data block, an estimator for obtaining a channel estimate for at least one path of the channel, and an equalizer for performing multiple equalizations in parallel, each equalization utilizing the channel estimate, at least one of the known sequences, and at least one of the sub- blocks.
  • the apparatus generally includes means for receiving at least one data block of a data stream on a channel with one or more paths, each of the at least one data block having known sequences of data between sub-blocks of the data block, means for obtaining a channel estimate for at least one path of the channel, and means for performing multiple equalizations in parallel, each equalization utilizing the channel estimate, at least one of the known sequences, and at least one of the sub-blocks.
  • the computer-program product includes a computer readable medium encoded with instructions executable to receive at least one data block of a data stream on a channel with one or more paths, each of the at least one data block having known sequences of data between sub-blocks of the data block, obtain a channel estimate for at least one path of the channel, and perform multiple equalizations in parallel, each equalization utilizing the channel estimate, at least one of the known sequences, and at least one of the sub-blocks.
  • the mobile handset generally includes at least one antenna, a receiver for receiving via the at least one antenna at least one data block of a data stream on a channel with one or more paths, each of the at least one data block having known sequences of data between sub-blocks of the data block, an estimator for obtaining a channel estimate for at least one path of the channel, and an equalizer for performing multiple equalizations in parallel, each equalization utilizing the channel estimate, at least one of the known sequences, and at least one of the sub- blocks.
  • FIG. 1 illustrates an example wireless communication system, in accordance with certain aspects of the present disclosure.
  • FIG. 2 illustrates various components that may be utilized in a wireless device in accordance with certain aspects of the present disclosure.
  • FIG. 3 illustrates an example transmitter that may be used within a wireless communication system in accordance with certain aspects of the present disclosure.
  • FIG. 4 illustrates an example receiver with sequential decision feedback equalization (DFE) that may be used within a wireless communication system in accordance with certain aspects of the present disclosure.
  • DFE sequential decision feedback equalization
  • FIG. 5 illustrates example operations for transmitting data stream with inserted known sequences in accordance with certain aspects of the present disclosure.
  • FIG. 5 A illustrates example components capable of performing the operations illustrated in FIG. 5.
  • FIGS. 6A-6B illustrate examples of data-block structures for a single-carrier transmission in accordance with certain aspects of the present disclosure.
  • FIG. 7 illustrates example operations for performing parallel equalization at the receiver in accordance with certain aspects of the present disclosure.
  • FIG. 7A illustrates example components capable of performing the operations illustrated in FIG. 7.
  • FIG. 8 illustrates an example of data-block structure that comprises sub- blocks and known sequences inserted between each sub-block in accordance with certain aspects of the present disclosure.
  • FIG. 9 illustrates an example receiver with parallel equalizers in accordance with certain aspects of the present disclosure.
  • the techniques described herein may be used for various broadband wireless communication systems, including communication systems that are based on a single carrier transmission. Aspects disclosed herein may be advantageous to systems employing Ultra Wide Band (UWB) signals including millimeter-wave signals. However, the present disclosure is not intended to be limited to such systems, as other coded signals may benefit from similar advantages.
  • UWB Ultra Wide Band
  • FIG. 1 illustrates an example of a wireless communication system 100 in which aspects of the present disclosure may be employed.
  • the wireless communication system 100 may be a broadband wireless communication system.
  • the wireless communication system 100 may provide communication for a number of cells 102, each of which is serviced by a base station 104.
  • a base station 104 may be a fixed station that communicates with user terminals 106.
  • the base station 104 may alternatively be referred to as an access point, a Node B or some other terminology.
  • FIG. 1 depicts various user terminals 106 dispersed throughout the system 100.
  • the user terminals 106 may be fixed (i.e., stationary) or mobile.
  • the user terminals 106 may alternatively be referred to as remote stations, access terminals, terminals, subscriber units, mobile stations, stations, user equipment, etc.
  • the user terminals 106 may be wireless devices, such as cellular phones, personal digital assistants (PDAs), handheld devices, wireless modems, laptop computers, personal computers, etc.
  • PDAs personal digital assistants
  • a variety of algorithms and methods may be used for transmissions in the wireless communication system 100 between the base stations 104 and the user terminals 106.
  • signals may be sent and received between the base stations 104 and the user terminals 106 in accordance with UWB techniques. If this is the case, the wireless communication system 100 may be referred to as an UWB system.
  • a communication link that facilitates transmission from a base station 104 to a user terminal 106 may be referred to as a downlink (DL) 108, and a communication link that facilitates transmission from a user terminal 106 to a base station 104 may be referred to as an uplink (UL) 110.
  • DL downlink
  • UL uplink
  • a downlink 108 may be referred to as a forward link or a forward channel
  • an uplink 110 may be referred to as a reverse link or a reverse channel.
  • a cell 102 may be divided into multiple sectors 112.
  • a sector 112 is a physical coverage area within a cell 102.
  • Base stations 104 within a wireless communication system 100 may utilize antennas that concentrate the flow of power within a particular sector 112 of the cell 102. Such antennas may be referred to as directional antennas.
  • FIG. 2 illustrates various components that may be utilized in a wireless device 202 that may be employed within the wireless communication system 100.
  • the wireless device 202 is an example of a device that may be configured to implement the various methods described herein.
  • the wireless device 202 may be a base station 104 or a user terminal 106.
  • the wireless device 202 may include a processor 204 which controls operation of the wireless device 202.
  • the processor 204 may also be referred to as a central processing unit (CPU).
  • Memory 206 which may include both read-only memory (ROM) and random access memory (RAM), provides instructions and data to the processor 204.
  • a portion of the memory 206 may also include non- volatile random access memory (NVRAM).
  • the processor 204 typically performs logical and arithmetic operations based on program instructions stored within the memory 206.
  • the instructions in the memory 206 may be executable to implement the methods described herein.
  • the wireless device 202 may also include a housing 208 that may include a transmitter 210 and a receiver 212 to allow transmission and reception of data between the wireless device 202 and a remote location.
  • the transmitter 210 and receiver 212 may be combined into a transceiver 214.
  • An antenna 216 may be attached to the housing 208 and electrically coupled to the transceiver 214.
  • the wireless device 202 may also include (not shown) multiple transmitters, multiple receivers, multiple transceivers, and/or multiple antennas.
  • the wireless device 202 may also include a signal detector 218 that may be used in an effort to detect and quantify the level of signals received by the transceiver 214.
  • the signal detector 218 may detect such signals as total energy, energy per subcarrier per symbol, power spectral density and other signals.
  • the wireless device 202 may also include a digital signal processor (DSP) 220 for use in processing signals.
  • DSP digital signal processor
  • the various components of the wireless device 202 may be coupled together by a bus system 222, which may include a power bus, a control signal bus, and a status signal bus in addition to a data bus.
  • a bus system 222 may include a power bus, a control signal bus, and a status signal bus in addition to a data bus.
  • FIG. 3 illustrates an example of a transmitter 302 that may be used within a wireless communication system 100 that utilizes single-carrier or some other transmission technique. Portions of the transmitter 302 may be implemented in the transmitter 210 of a wireless device 202. The transmitter 302 may be implemented in a base station 104 for transmitting data 304 to a user terminal 106 on a downlink 108. The transmitter 302 may also be implemented in a user terminal 106 for transmitting data 304 to a base station 104 on an uplink 110.
  • Data 304 to be transmitted are shown being provided as input to a mapper 306.
  • the mapper 306 may map the data stream 304 onto constellation points. The mapping may be done using some modulation constellation, such as binary phase-shift keying (BPSK), quadrature phase-shift keying (QPSK), 8 phase-shift keying (8PSK), quadrature amplitude modulation (QAM), etc.
  • BPSK binary phase-shift keying
  • QPSK quadrature phase-shift keying
  • 8PSK 8 phase-shift keying
  • QAM quadrature amplitude modulation
  • the mapper 306 may output a symbol stream 308, which may represents an input into an insertion unit 310.
  • the insertion unit 310 may be configured for inserting sequences known at the receiver within the input symbol stream 308, and generates a corresponding data stream 314 with inserted known sequences.
  • Known sequences may comprise Golay codes and can be used by the receiver for tracking, channel estimation, detection and channel decoding.
  • Known sequences may also comprise a guard interval inserted at the beginning of the input symbol stream 308.
  • the output 314 of the insertion unit 310 may then be up-converted to a desired transmit frequency band by a radio frequency (RF) front end 316.
  • An antenna 318 may then transmit the resulting signal 320.
  • FIG. 4 illustrates an example of a receiver 402 that may be used within a wireless device 202 that utilizes a single-carrier or some other transmission technique. Portions of the receiver 402 may be implemented in the receiver 212 of a wireless device 202.
  • the receiver 402 may be implemented in a user terminal 106 for receiving data 404 from a base station 104 on a downlink 108.
  • the receiver 402 may also be implemented in a base station 104 for receiving data 404 from a user terminal 106 on an uplink 110.
  • a signal 404 When a signal 404 is received by an antenna 406, it may be down-converted and digitized to form a digital baseband signal 412 by an RF front end 408.
  • a frame format of the received signal for single-carrier data communications typically comprises a known sequence followed by a data portion, which facilitates equalization based on a decision feedback.
  • a received baseband signal y n may be expressed as:
  • the receiver may use a simple one -tap decision feedback equalizer (DFE), such as the one illustrated in FIG. 4.
  • DFE simple one -tap decision feedback equalizer
  • the DFE portion 410 of the receiver 402 may be configured to normalize the first channel tap such that the received baseband signal 412 may be given as:
  • the DFE portion of the receiver may be also adapted for multipath channels having more than two paths.
  • the received baseband signal may be expressed as:
  • the previous data symbol d_ y may be from the known sequence.
  • an estimate d 0 of the first data symbol may be derived by subtracting interference due to the preceding symbol d_ y h y from the received signal y 0 and by providing for a soft or hard decision on the difference:
  • equation (4) For example, for BPSK modulation, the decision operation in equation (4) is simply the sign operation.
  • d 0 Once d 0 is determined, it can be used to estimate the next data symbol d l from y ⁇ , as follows:
  • d n ⁇ the channel tap Zz 1 and then subtracted from the received symbol y n .
  • Estimate of a data symbol d n may be determined by a decision unit 414 (e.g., a soft or hard decision unit) as:
  • a demapper 418 may input an equalized data stream 416 and may perform the inverse of the symbol mapping operation that was performed by the mapper 306 from FIG. 3 thereby outputting a data stream 420.
  • this data stream 420 corresponds to the data 304 that was provided as input to the transmitter 302, as illustrated in FIG. 3.
  • a clock (not shown) employed by the DFE portion of the receiver in FIG. 4 may be typically operated at an integer-multiple of the input signal's data rate/ .
  • very high data rates e.g., 1728 MHz, which has been adopted in the IEEE 802.15.3c standard
  • the receiver can be typically a mobile device, and power dissipation may be prohibitively high if the mobile device is operated with very high clock frequency.
  • Certain aspects of the present disclosure employ a special format of a transmission frame (data stream) and parallel equalization allowing a clock to operate at a fraction of the input signal data rate / .
  • FIG. 5 illustrates example operations 500 for transmitting a data stream with inserted known sequences supporting parallel equalization operations at a receiver, such as, for example, decision feedback equalization (DFE) operations.
  • DFE decision feedback equalization
  • the data stream may be generated that comprises one or more data blocks. Sequences of known data may be inserted between sub-blocks of each data block, at 520. Such data stream with inserted known sequences may be then transmitted over a wireless channel, at 530.
  • FIG. 6A and FIG. 6B are representations of a structure of one data block for a single-carrier transmission signal that support employing parallel equalization operations at the receiver.
  • a short known sequence 608 may follow the last data sub-block 612 of a data block 602. It can be assumed, without loss of generality, that sub-blocks 606, 610, and 612 may comprise Q chips (samples).
  • FIG. 6B illustrates a data block structure in which the trailing known short sequence 628 of the last sub- block 632 of a data block 622 may be omitted. It can be also assumed, without loss of generality, that sub-blocks 626, 630 and 632 may also comprise Q chips (samples).
  • FFT fast Fourier transform
  • the data blocks 602 and 622 may comprise, for example, 256 or 512 samples.
  • the frequency domain equalization may be applied at the receiver when the wireless channel has a substantial number of paths. In this case, the channel may be divided into flat- fading frequency sub -components (i.e., sub-carriers) that can be equalized independently with a lower computational complexity than the computational complexity of time domain equalization.
  • time domain equalization may be more appropriate for environments with a smaller number of channel paths in order to reduce computational complexity and power dissipation of receiver processing.
  • each known sequence 608 and 628 may comprise a number of samples related to a time domain channel length. The channel length may be available at the transmitter side. Therefore, the appropriate number of known samples may be included between each data sub- block, and these known samples may be used at the receiver for equalization of data samples.
  • a first known sequence 604 (i.e., a sequence that is known at the receiver) of the data block 602 in FIG. 6 A and a first known sequence 624 of the data block 622 in FIG. 6B may be followed by a sub-block 606 and a sub-block 626, respectively.
  • Lengths of the first known sequences 604 and 624 may be typically equal to or greater than the largest expected channel length, and may be, for example, equal to a mean- squared multipath delay, a total multipath delay, or to some other function of the channel multipath delay.
  • the first known sequence of the data block may be utilized to update channel estimates, provide for frequency and time tracking, and to facilitate the frequency domain equalization.
  • the data portion of the blocks 602 and 622 may be partitioned into a plurality N of data sub-blocks. At least one known short sequence indicated as 608 in FIG. 6A and 628 in FIG. 6B may be inserted between each data sub-block. The number N of data sub-blocks within the data block may provide for a parallelism factor of N , which may divide the required clock frequency by the factor of N .
  • the short sequence 608 in FIG. 6A and the short sequence 628 in FIG. 6B (which may be as short as one chip) may be used to facilitate parallel processing at the receiver that employs a decision feedback equalization (DFE) or a maximum likelihood sequence estimation (MLSE). Alternatively, the receiver may employ other receiver processing techniques configured to process a plurality of parallel data sub-blocks at a lower rate than a rate of the receiving data streams.
  • DFE decision feedback equalization
  • MLSE maximum likelihood sequence estimation
  • the receiver may employ other receiver processing techniques configured to process a plurality of parallel data sub-blocks at a
  • Each short sequence 608 or 628 may comprise a single chip or a plurality of chips (samples), and the short sequences may be selected in accordance with the channel length.
  • certain aspects of the present disclosure may be configured to support a wide range of channel lengths.
  • time- and/or frequency-domain equalization techniques may be used to produce an effective impulse response shorter than the channel impulse response. This facilitates the use of short sequences when the channel length is long.
  • a channel-shortening filter may shorten a long channel length to a length of only five chips.
  • each short sequence 608 or 628 may comprise four chips of known data.
  • FIG. 7 illustrates example operations 700 for performing parallel equalization at the receiver.
  • FIG. 8 illustrates a data block structure 800 for a single carrier signal wherein the data block may be partitioned into four sub-blocks and a known chip may be placed between each sub-block. While this particular aspect of the present disclosure employs four sub-blocks and a short sequence of one chip, alternative aspects may employ different numbers of sub-blocks and short sequences longer than one chip.
  • Each data block may comprise known sequences of data between sub-blocks of that data block.
  • the data block 800 may be demultiplexed into four sub-blocks 801-804, each of which can be processed by an equalizer (such as, for example, decision feedback equalizer) at a quarter of the input signal's data rate/,, .
  • Each sub-block 801-804 may comprise a data segment bounded by a known chip.
  • the first sub-block 801 has a first chip 811 from the known sequence preceding the data segment.
  • the fourth sub-block 804 has a trailing chip 812, which may be from the known sequence of the following block (not shown in FIG. 8).
  • known sequences may be utilized to compute channel estimates.
  • multiple equalizations may be performed in parallel. Each equalization may utilize the computed channel estimates, known sequences, and previously detected symbols from the sub-blocks, as given by equation (6).
  • FIG. 9 illustrates an example receiver in accordance with one aspect of the present disclosure.
  • Four parallel decision feedback equalizers (DFEs) 901-904 may follow a demultiplexer 900 and may be configured for processing sub-blocks 801-804 at a quarter of the input signal's data rate / .
  • the DFEs 901-904 may operate independently of each other because each equalizer starts processing from a known state (i.e., with a known chip).
  • each of the sub-blocks 801-804 illustrated in FIG. 8 includes both a leading known chip and a trailing known chip bounding each end of its data portion.
  • the leading known chip may be required for a DFE-based processing. Therefore, certain aspects of the present disclosure may provide for demultiplexing the data block without including the trailing known chip.
  • the DFEs 901-904 may be replaced by parallel maximum likelihood sequence estimators, in which case the trailing known chip may be utilized.
  • receivers and receiving methods in accordance with alternative aspects of the disclosure may be configured to process a plurality K of data blocks in parallel, resulting in an increased parallelism factor of N ⁇ K .
  • two of the data blocks may be demultiplexed simultaneously by the demultiplexer 900 illustrated in FIG. 9. Since there are twice as many data sub-blocks being demultiplexed, eight parallel DFEs (or other similar receiver components) may need to be provided. Eight parallel DFEs may be controlled with a clock rate o ⁇ f y / 8.
  • the various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions.
  • the means may include various hardware and/or software component(s) and/or module(s), including, but not limited to a circuit, an application specific integrate circuit (ASIC), or processor.
  • ASIC application specific integrate circuit
  • blocks 510-530 and 710-730 illustrated in FIGS. 5 and 7 correspond to circuit blocks 510A-530A and 710A-730A illustrated in FIGS. 5A and 7A.
  • determining encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Also, “determining” may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Also, “determining” may include resolving, selecting, choosing, establishing and the like.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array signal
  • PLD programmable logic device
  • a general purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller or state machine.
  • a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
  • the steps of a method or algorithm described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two.
  • a software module may reside in any form of storage medium that is known in the art. Some examples of storage media that may be used include random access memory (RAM), read only memory (ROM), flash memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD- ROM and so forth.
  • a software module may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media.
  • a storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
  • the methods disclosed herein comprise one or more steps or actions for achieving the described method.
  • the method steps and/or actions may be interchanged with one another without departing from the scope of the claims.
  • the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.
  • a storage media may be any available media that can be accessed by a computer.
  • such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.
  • Disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray ® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.
  • certain aspects may comprise a computer program product for performing the operations presented herein.
  • a computer program product may comprise a computer readable medium having instructions stored (and/or encoded) thereon, the instructions being executable by one or more processors to perform the operations described herein.
  • the computer program product may include packaging material.
  • Software or instructions may also be transmitted over a transmission medium.
  • a transmission medium For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of transmission medium.
  • DSL digital subscriber line
  • modules and/or other appropriate means for performing the methods and techniques described herein can be downloaded and/or otherwise obtained by a user terminal and/or base station as applicable.
  • a user terminal and/or base station can be coupled to a server to facilitate the transfer of means for performing the methods described herein.
  • various methods described herein can be provided via storage means (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc.), such that a user terminal and/or base station can obtain the various methods upon coupling or providing the storage means to the device.
  • storage means e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc.
  • CD compact disc
  • floppy disk etc.
  • any other suitable technique for providing the methods and techniques described herein to a device can be utilized.
  • the techniques provided herein may be utilized in a variety of applications.
  • the techniques presented herein may be incorporated in an access point, a mobile handset, a personal digital assistant (PDA) or other type of wireless devices that operate in UWB part of spectrum with processing logic and elements to perform the techniques provided herein.
  • PDA personal digital assistant

Abstract

Certains aspects de la présente invention concernent un procédé d'utilisation d'un format spécial pour transmettre des blocs de données qui permet des égalisations parallèles au niveau d'un récepteur. Grâce à l'application d'opérations d'égalisations parallèles, une horloge au niveau du récepteur peut fonctionner à une fraction du débit de données du signal d'entrée, ce qui s'avère plus pratique dans le cas de débits de données très élevés, alors que la dissipation de puissance est également réduite.
EP09723201A 2008-03-18 2009-03-17 Structure de rafales monoporteuse pour une égalisation et un suivi de rétroaction de décision Withdrawn EP2260623A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US3765208P 2008-03-18 2008-03-18
US12/404,903 US8831063B2 (en) 2008-03-18 2009-03-16 Single carrier burst structure for decision feedback equalization and tracking
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JP5670491B2 (ja) 2015-02-18
TW201006185A (en) 2010-02-01
JP5964387B2 (ja) 2016-08-03
KR20100124822A (ko) 2010-11-29
CN101978662B (zh) 2014-12-03
WO2009117441A2 (fr) 2009-09-24
US8831063B2 (en) 2014-09-09
JP2013146081A (ja) 2013-07-25
CN101978662A (zh) 2011-02-16
WO2009117441A3 (fr) 2010-05-06
JP2015057898A (ja) 2015-03-26
KR101230962B1 (ko) 2013-02-07
US20090238240A1 (en) 2009-09-24

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