EP2254008A1 - Séquence d'impulsions modulées en largeur générant une réponse indicielle apériodique critique - Google Patents

Séquence d'impulsions modulées en largeur générant une réponse indicielle apériodique critique Download PDF

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Publication number
EP2254008A1
EP2254008A1 EP10173926A EP10173926A EP2254008A1 EP 2254008 A1 EP2254008 A1 EP 2254008A1 EP 10173926 A EP10173926 A EP 10173926A EP 10173926 A EP10173926 A EP 10173926A EP 2254008 A1 EP2254008 A1 EP 2254008A1
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EP
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Prior art keywords
pulse width
pulse
control system
state transition
response
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EP10173926A
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German (de)
English (en)
Inventor
Andrew Roman Gizara
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Cufer Asset Ltd LLC
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IPower Holdings LLC
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Priority claimed from EP07844184A external-priority patent/EP2076822B1/fr
Publication of EP2254008A1 publication Critical patent/EP2254008A1/fr
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B11/00—Automatic controllers
    • G05B11/01—Automatic controllers electric
    • G05B11/26—Automatic controllers electric in which the output signal is a pulse-train
    • G05B11/28—Automatic controllers electric in which the output signal is a pulse-train using pulse-height modulation; using pulse-width modulation
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B5/00—Anti-hunting arrangements
    • G05B5/01—Anti-hunting arrangements electric
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/025—Digital function generators for functions having two-valued amplitude, e.g. Walsh functions
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention is generally in the field of control systems. More specifically, the present invention is in the field of use of pulse width modulation in a control system.
  • This specification herein exemplifies the present invention by an open loop, and subsequently, a closed loop digital power supply embodying voltage or current regulation.
  • control system engineers have implemented pulse width modulation schemes for driving a regulated voltage or current from a control plant.
  • Control system engineers of ordinary skill in the art have long since designed digital open loop pulse width modulation control schemes to power loads that do not require precise voltage or current regulation.
  • These digital open loop pulse width modulation control systems generally have powered loads such as DC motors, or heating elements, or other inductive and/or resistive loads which tolerate a system step response exhibiting large overshoot, for instance in excess of fifty percent beyond the set-point.
  • DC motors or heating elements
  • inductive and/or resistive loads which tolerate a system step response exhibiting large overshoot, for instance in excess of fifty percent beyond the set-point.
  • digital open loop pulse width modulation design offers advantages of substantial cost savings in terms of reduced component count and ease of implementation due to modest design complexity.
  • the present invention is directed to a novel but readily comprehensible algorithm implemented with tools commonly in use by a control engineer of ordinary skill in the art.
  • the present invention depicts such an algorithm using these tools to create a specific pulse width modulation sequence that generates a near critical damped step response in a second order or higher order linear or non-linear system that otherwise would exhibit an under damped step response.
  • the present invention exemplifies the use of tools and method for integrating a semiconductor die of plural power supply voltage domains with an open loop, and subsequently, a closed loop switch mode DC-to-DC converter to obtain optimal power savings, and minimal heat dissipation and component cost.
  • the present invention is not limited to application to the exemplary system.
  • the present invention may be applied to control of any second or higher order system mathematically analogous to pulsed control and requiring near critical damped step response.
  • Any electrical, mechanical or electromechanical system under the mathematical analogue of pulsed open loop control may especially benefit from the present invention whereby without the present invention, open loop control could result in a characteristically under damped step response thus rendering such a topology undesirable and the cost benefits and ease of implementation of such open loop topology unrealizable.
  • the present invention places only the design requirements of use of control plant component values of +/-10% tolerance and reasonably accurate estimates of the load of the system, with tolerance of +/-25% depending upon how near to the ideal response time and how much overshoot the system can withstand i.e. the load regulation specification of the control system.
  • the present invention pertains to a control system and algorithm for generating a near critical damped step response using pulse width modulation techniques in an inherently under damped system.
  • the following description contains specific information pertaining to various embodiments and implementations of the invention.
  • One skilled in the art will recognize that one may practice the present invention in a manner different from that specifically depicted in the present specification.
  • the present specification has omitted some of the specific details of the present invention in order to not obscure the invention.
  • a person of ordinary skills in the art would have knowledge of the specific details not described in the present specification. Obviously, one may omit or only partially implement some features of the present invention and remain well within the scope and spirit of the present invention.
  • Figure 1 illustrates a schematic of an ideal embodiment of the present invention.
  • Block 100 represents the control plant implemented with ideal models of an exemplary embodiment of the present invention.
  • the exemplary embodiment within block 100 consists of the typical step-down switch mode power supply components that constitute a canonical parallel resonant LRC circuit well understood by one of ordinary skill in the art.
  • the input power supply and the controlled switching element have been modeled as an ideal pulsed source 101 referenced to ground 102 and feeding power into the remaining system components from the node entitled Vin 103 through the inductor 104.
  • the node entitled Vout 106 connects the inductor 104 and the output capacitor 105 referenced to ground 102 and forming the energy storage and filtering elements that transform the switched Vin 103 to a DC output Vout 106 that powers the load modeled as a resistor 107 referenced to ground 102.
  • this model in block 100 represents using ordinary second order differential equation analysis techniques, with the exact solution depending upon values of the L1 104, R1 107, and C1 105, with respect to each other.
  • the present invention does not address the case of the over damped response which exhibits no overshoot above the set-point and thus presents no danger of exceeding an upper limit of specified load regulation, but does perform less than optimally in regard to slow response time.
  • the present invention presumes the engineer designing such a system would likely avoid sub-optimal over damped performance, leaving the two remaining cases to consider.
  • the present invention does address the two remaining cases, under damped and critical damped response in such a model 100 and analogous systems.
  • Figure 2 depicts both an example of an under damped 204 and an example of a critical damped 203 step response in plot 200.
  • the vertical axis 201 represents a normalized set-point scale whereas the horizontal axis 202 represents time given in units of an arbitrary switching period.
  • the degree to which the step response goes under damped coincides with a damping factor of approximately .23, overshooting by more than 55% and one can commonly find this sort of step response given typical switch mode power supply components configured in an open loop topology.
  • a particular point of interest along the plot 200 of the two different step responses one may note includes the point 205 where the responses begin to deviate by approximately 5% from each other.
  • Figure 3 details equations including: equation 301 describing time domain critical damped step response; equation 302 describing the sequence of duty cycles in a pulse train that results in a critical damped response for the circuit in block 100 of Figure 1 ; a definition 303 of one of the parameters of equation 302; a time domain system equation 304 representing the circuit in block 100 of Figure 1 ; and equation 305, the general form of the time domain input signal that results in a critical damped step response for the circuit in block 100 of Figure 1 .
  • the variable v o (t) in equation 301 represents the time variant output voltage synonymous with Vout 106 in the model 100 of Figure 1 .
  • V in in equation 301 represents the amplitude of the input voltage synonymous with the amplitude ofVin 103 in the model 100 of Figure 1 .
  • the coefficient A OF corresponds to the gain of an amplifier with feedback, which one of ordinary skill in the art has known to ideally behave analogously to a parallel resonant LRC circuit.
  • the coefficient A OF equivalent to the duty cycle required to obtain a desired set-point in an ideal pulse width modulated control system 100.
  • the two remaining variables, t and ⁇ 0 one may immediately recognize as time in seconds, and the resonant frequency in radians per second, commonly known most directly equal to one over the square root of the value of L1 104 times C1 105, respectively.
  • u(t) fails to meet the requirements of a function
  • engineers have referred to u(t) as the unit step forcing function as a widely accepted artifice, and this specification will use u(t) in such a conventional manner hereinafter.
  • the discrete variable n 1 denotes an integer number of switching periods T sw , the inverse of the switching frequency, in which the duty cycle initially assumes its final value in order to obtain the desired voltage gain set-point.
  • T sw the inverse of the switching frequency
  • this time period corresponds to the point 205 where the critical damped and under damped responses begin to deviate by approximately 5% from each other in an ideal second order system model 100.
  • equation 304 one may prove using the mathematical operation of convolution that the pulse train defined by its duty cycle in equation 302, using its formal definition as an input signal in equation 305, provides a near critical damped step response, y m (t) in equation 304, synonymous to Vout 106 in model 100 of Figure 1 , in a system 100 that would otherwise exhibit an under damped response had a step directly to the desired duty cycle set-point occurred.
  • h(t) represents the system 100 impulse response equivalent to the derivative with respect to time of y m (t) when X m (t) equals a unit step forcing function, u(t).
  • the subscript m in equation 304 implies a unique response y m (t) associated with a unique input x m (t) for each transition in system state m indexes.
  • the discrete variable n 2 in equations 302 and 305 signifies an offset in time in the application of the critical damped response scaling function from the time at which one applies the scaling to the duty cycle. Therefore the discrete variables n 1 and n 2 as introduced in equations 302 and 305 carry out the resulting purpose of coarse and fine tuning in the time domain, respectively, to bring the system step response, once tuned, closer towards a critical damped response.
  • This subtle difference implies step changes subsequent to initial power-on of the control system may attain similar critical damped response through application of the same scaled pulse width modulation input per equation 305.
  • This specification of the present invention examines these additional power state transitions and further general form equations that describe how to attain critical damped step response for higher order systems in subsequent paragraphs describing Figure 6 .
  • Figure 4 shows a view of a spreadsheet 400 computer program that serves as an analysis tool to the designer, as well as a means to generate the pulse width modulation that results in a near critical damped response, for an inherently under damped system.
  • graphical user interface buttons 401 enable the user to navigate from the top sheet 402 to subsequent sheets 403.
  • the specification will herein discuss the top sheet 402, and following paragraphs will discuss the subsequent sheets 403.
  • the spreadsheet 400 of Figure 4 shows a schematic plot 404, and a response plot 405 illustrative of the ideal under damped and critical damped response of the exemplary control system under development.
  • the schematic plot 404 inserted onto the top sheet 402 of the spreadsheet 400 has replaced the ideal switching element, pulsed source 101, with a physical model of two switching transistors 406, 407 and a model of a pulse width modulation controller labeled Vgdrvr to drive the gates of the physical transistors 406, 407.
  • Cells A1 down to A8 comprise the names of physical parameters the designer enters into the spreadsheet 400 with the actual values of those parameters entered into corresponding cells B1 down to B8.
  • formulae reside in cells D9 down to D20 computing other parameters necessary for further computation in the formulae that create the points in the response plots 405 along with the formulae that generate the simulation code for use within a Simulation Program with Integrated Circuit Emphasis commonly known as SPICE to those of ordinary skill in the art.
  • the names of the computed parameters in cells D9 down to D20 appear correspondingly in cells C9 down to C20.
  • the user enters parameters into cells B1 down to B8 as follows: R, the resistive model for the load in cell B1; L, the inductance value in cell B2; C, the output capacitance in cell B3; Vin, the fixed DC input voltage in cell B4; Vcore0, the output DC voltage in this particular example to which the system first transitions, in cell B5; Vcore1, the output DC voltage to which the system transitions after Vcore0, in cell B6; F sw , the switching frequency of the system, in cell B7; and A DE , a coefficient which compensates for dynamic error caused by loss from non-ideal behavior in the physical switching elements, in cell B8.
  • the spreadsheet 400 computes intermediate parameters as displayed in cells D9 down to D20. These intermediate parameters include: A v0 , the ideal voltage gain for the first power state obtained by dividing Vcore0 by Vin, in cell D9; A v1 , the ideal voltage gain for the second power state in this particular example, obtained by dividing Vcore1 by Vin, in cell D10; ⁇ 0 , the resonant frequency in radians per second given by one over the root of the quantity L times C, in cell D11; ⁇ d , the damped frequency given by the resonant frequency times the root of the quantity one minus the damping factor, in cell D 12; Q, the quality factor, given by R over the quantity L times the resonant frequency, in cell D13; ⁇ , the damping factor, in some texts symbolized as "k” in other texts a lower case zeta as shown, with
  • the immediate method of system analysis or synthesis of critical damped response may not use all of these intermediate parameters, but these parameters may provide insight to one familiar with other analysis methods including but not limited to root locus and pole zero matching.
  • n discrete variable
  • Cell B23 and cell C23 identify the columns below as the normalized critical damped and under damped step response functions by their properties of damping factor range, respectively, with the actual points of the response plots 405 occupying the cells starting at cell B25 and cell C25 and continuing downward corresponding in time to the value of n to the left times the switching period T sw .
  • D23 identifies the error in terms of the magnitude of the difference of the critical damped response minus the under damped response, with the points of this error function starting at cell D25 and continuing downward.
  • cell E23 identifies the column starting at E25 comprising the normalized value of the input signal into the plant that a hypothetical feedback network, synthesized using the prior art pole zero matching method, affects when such a network receives the under damped response as depicted in column C starting at cell C25.
  • Empirical results indicate the pole zero matching feedback network performs sub-optimally with substantially slower response times than the near critical damped response generated by the pulse width sequence of the present invention.
  • Figure 5 represents an example of a code sheet 500 from the subsequent sheets 403 that generate SPICE executable simulation code based upon the values entered into columns B1 down to B8 on the top sheet 402 of the spreadsheet 400 in Figure 4 .
  • the designer of the exemplary control system copies the entire text of the simulation code sheet 500 into a text window of the graphical user interface of a SPICE simulation program or saves the code sheet 500 as a separate text file to run within SPICE in command-line mode, as the final step of me analysis and verification iterative process. While this specification will not offer much reference to the syntax of SPICE, the discussion will now turn to the individual lines of code labeled with a reference designator from 501 down to 523.
  • Line number 501 down to 523 specify the physical model of the inductor L1, the capacitor C1, the DC input voltage Vin, and the switching transistors 406, 407 with the interconnection of these plant elements as previously graphically depicted in schematic plot 404 of Figure 4 .
  • Lines 505 down to 507 appear as comments as indicated by the "*" for the first character in the line.
  • Line 505 indicates the two values of discrete variable n 1 : the first value equal to seven, the second value equal to three; and the set-point pulse widths for two transitions of power states for this given simulation.
  • Line 506 essentially indicates the discrete variable n 2 has a value of zero for both transitions.
  • Line 507 denotes the polarity of the top Field Effect Transistor 406 in the switching element 406, 407, and as such requires a logic inversion of the gate driver output signal gdrvr in order for proper operation of the exemplary switch mode power supply per the reference patent U.S. patent 6,940,189 .
  • Lines 508 down to line 514 demonstrate how the discrete variable n 1 affects the pulse width as one can readily observe the values for the turn-off time of the top transistor 406 ending in the number sequence 5890 repeating for seven lines corresponding to n 1 equal to seven.
  • the pulse width sequence continues from line 515, with the set-point pulse period scaled by the critical damped step response function starting with the scaling factor in cell B33 of the top sheet 402 and continuing downward.
  • the ellipsis 516 merely indicates a discontinuity in Figure 5 wherein an arbitrary number of lines of code, excessive for this drawing figure to exhaustively list, would define the behavior of the model of the gate driver and pulse width modulation controller Vgdrvr throughout the time of the simulation.
  • Lines 517, 518 show the last two lines of the piece wise linear time domain description of the model of the gate driver and pulse width modulation controller Vgdrvr that started on line 508.
  • lines 517, 518 one can see the time values for the turn-off time of the top transistor 406 ending in the number sequence 4908 having reached its the terminal value of the second set-point after the second transition in this given simulation.
  • Lines 519 and 520 alternately affect the simulation in that line 519 describes Iload, a physical model of a non-linear capacitive load resembling that of the semiconductor core of this exemplary system under development, whereas line 520, commented out as per the "*" first character, describes a simple resistive load such as R1 107 of Figure 1 .
  • line 519 and inserting line 520 facilitates variation of load, in this immediate example, changing the resistance value of 1.8 ohms in line 520 to alternate values.
  • line 520 and 521 may replace lines 520 and 521 with a piecewise linear time domain description for Iload, similar to the previously mentioned PWL statement starting from line 508 down to line 518.
  • the designer may physically simulate the actual load, with data stored on a digital storage oscilloscope captured empirically from a characteristic load.
  • the user may alter the physical parameters of L1 in line 501 and C1 in line 502 to conveniently characterize deviations from initial estimates and model different physical conditions.
  • Line 521 refers the SPICE simulator to the previously stated physically characterized library for the switching transistors 406, 407.
  • Line 522 simply indicates to SPICE the intended time domain transient analysis of 200 microseconds duration while line 523 fulfills a simple syntactic necessity.
  • Figure 6 extends the equations introduced in Figure 3 beyond an ideal second order system towards a higher order physical system as portrayed in the schematic plot 404 of Figure 4 while also incorporating both transitions from lower to higher and higher to lower power states.
  • equation 601 describing the duty cycle sequence of a transition from a lower to higher power state shares with equation 302.
  • the subtle difference of including a "+" subscripted D + (n) indicates the duty cycle as a function of discrete time having relevance in a transition from a lower to higher power state, i.e. duty cycle increasing with time.
  • the inclusion of the dynamic error compensation coefficient, A DE as a factor for the duty cycle over all time stands as the only other difference that equation 601 holds apart from equation 302.
  • Figure 6 mathematically defines the dynamic error compensation coefficient, A DE , in equation 602, relation 603, and applies A DE in equation 604 to define the voltage V sw at node sw as shown in the schematic plot 404 of Figure 4 .
  • the need for such a dynamic error compensation coefficient arises due to traversing from the idea1 second order model to a physical higher order model, and accounts for switching frequency dependent dynamic losses incurred in the physical switching elements.
  • equation 602 implies the designer obtains the value of A DE after simulating a non-idea1 switching element such as that depicted in schematic plot 404 of Figure 4 , after having previously applied the ideal voltage gain coefficient, A v0 , and the power state transition has settled to its final value.
  • the relation 603 implies direct proportionality of A DE to switching frequency, to output voltage with respect to the input voltage, and to the output current. While the previous example treated A DE as a constant, A DE may vary from one power state to the next as implied in equation 610 as a function of the output voltage with respect to the input voltage as well as a function of the output current per the relation 603. Although all the examples in this specification illustrate voltage changes, relation 603 clearly indicates the control system in the scope of the present invention must also manage substantial changes in output current, thus affecting A DE(p) per relation 603 and equation 610, in the same manner as voltage changes.
  • the iterative process of analysis and verification including SPICE simulation determines how substantially any change in current or voltage affects A DE and thus if the change requires application of a transition function that equations 302, 305, 601, and 605 through 609 describe.
  • the range of output currents and voltages differed within limits allowing a constant A DE across all power state transitions to maintain accuracy to within approximately one-third of a percent of the desired set-point.
  • Equation 605 of Figure 6 simply applies equation 601 to obtain a general form of the output signal of the gate driver and pulse width modulation controller Vgdrvr, in the same fashion equation 305 applies the equation 302 of Figure 3 for the ideal model.
  • V sw replaces V in of equation 305 since equation 605 introduces A DE per equation 604 as a factor compensating for the dynamic losses through the physical switching element, and thus allows equation 605 to retain the mathematical precision given in the ideal model of equation 305.
  • Equation 606 introduces the duty cycle sequence of a transition from higher to lower power state and identifies the transition as going from a higher to a lower power state by stipulating the condition A v0 >A v1 .
  • Equation 607 likewise stipulates A v1 >A v0 in the way it introduces a general form duty cycle sequence for a transition from lower to higher power state. Obviously if the designer sets A v0 equal to zero, one then may algebraically reduce both equations 606, 607 to equation 601.
  • Equations 608 and 609 once again provide a general form of the output signal of the gate driver and pulse width modulation controller Vgdrvr resulting from equations 606, 607, in the same fashion equation 305 applies the equation 302 of Figure 3 for the ideal model.
  • equations 608, 609 introduce T Set(p) as the set-point pulse width defined in terms of equation 610, where p indexes the discrete power states and thus these equations describe a means to generate a near critical damped response for y m (t) in equation 304 for any arbitrary transition m proceeding from any power state p to any power state p+1.
  • Equation 611 reduces both equations 608, 609 to a single general form solution for a near critical damped response.
  • the benefit equations 608, 609 offer in their separate forms avoids potential confusion caused by terms of negative time value.
  • the relation 612 indicates the magnitude of the change in pulse width time period has direct proportional effects on the discrete variables n 1 , n 2 in the above equations 606 through 609, where n 1 and n 2 affect a coarse and fine tuning in the time domain, respectively, towards a critical damped response. Progressing to a higher order physical model from an ideal second order model also affects the value of n 1 and n 2 , which further accentuates the necessity of the iterative simulation analysis and verification process.
  • Figure 7 illustrates a canonical general state transition diagram 700 for which this specification will now briefly discuss the application of the equations and relations of Figure 6 .
  • the designer first enumerates all power states 701, 703, 705, 707, and transitions 702, 704, 704R, 706, 706R, 708, 708R, 709, 710 in the state transition diagram 700.
  • the total number of possible transitions, M in general appears to grow by the summation given by equation 711 where, as before, p stands for the index to discrete power states with P denoting the total number of power states.
  • p stands for the index to discrete power states with P denoting the total number of power states.
  • properties of physical systems in general as described in the equations of Figure 6 allow substantial reduction in complexity.
  • the inventor empirically found in the column starting at cell B25 of top sheet 402 of critical damped scaling factors of the pulse width set-point time period, the value N, the practical upper limit of summation in equations 305, 605, 608, 609, equals 63.
  • the limit N+1 carries importance in determining the length requirement of the column starting at cell B25 of top sheet 402 comprising critical damped scaling factors of the pulse width set-point period.
  • a state machine may execute the alternate operations of adding or subtracting the scaled
  • one may provide for differences in the discrete variables n 1 , n 2 from one transition to another by altering pointers to the memory addresses of a single transition's worth of N+1 stored exponential scaling function scaling factors.
  • the designer may decrease the total number of memory locations of scaling factors to N+1-n 1(min) where n 1(min) represents the lowest value of n 1 for all possible transitions in any system under development.
  • a least computation-intensive implementation of the present invention requires no computation whatsoever while the state machine controlling the system during transitions merely points to any one of M times (N+1) unique scaled pulse widths desired at that time.
  • the memory requirement entails M transitions worth of N+1 instances of exponentially scaled pulse periods per any one of the equations 305, or 605, or 608, or 609.
  • the designer may further decrease the total number of memory locations for each one of the M transitions to N+1-n 1 for each n 1 unique to each possible transition in the exemplary system under development.
  • Dithering involves alternating in short periods of time between two or more adjacent output codes in order to attain an average output value of greater precision existing between the ordinary output codes realizable without the method of dithering.
  • the state machine controlling the system during transition encounters a sequence in the look-up table of pulse width scaling factors for which the present embodiment can practically only attain less accuracy than 1%, the state machine may dither between several adjacent pulse widths over the course of this sequence time to improve accuracy.
  • dithering can also provide another benefit of reducing the scaling function memory requirement of the system.
  • a designer of a system within the scope of the present invention may also simply utilize dithering when changing the pulse width,
  • dithering can again provide the benefit of reducing the scaling function memory requirement of the system.
  • dithering offers several additional advantages aside from reducing quantization error and memory requirements. In steady state operation, dithering disperses the frequency spectrum of pulse width modulation into smaller peaks over a wider band giving the side benefit of diminishing electromagnetic emissions from the overall system.
  • Closed loop systems may suffer a phenomenon known by one of ordinary skill in the art as limit cycle oscillation, caused by insufficient output resolution with respect to input resolution in such control systems, which output dithering can prevent.
  • any embodiment within the scope of the present invention may apply dithering for any of the aforementioned benefits including reducing system memory requirements, reducing electromagnetic emissions, reducing quantization error or enhancing pulse width modulation resolution in an open loop system, or eliminating limit cycle oscillation in a closed loop system.
  • the specification will discuss an exemplary application of the present invention in a closed loop topology in a subsequent description of Figure 22 .
  • Figures 8 through 21 provide results from varying physical parameters during simulation and thus further define "nearness" to critical damped response in an actual realizable system.
  • Figure 8 illustrates a time domain response plot 800 from a simulation comprising two transitions of power states for an exemplary embodiment of the present invention. As shown in the response plots 200, 405, of Figure 2 and Figure 4 , respectively, the vertical axis of response plot 800 of Figure 8 displays a normalized set-point scale for the amplitude.
  • the horizontal axes of the response plots of Figures 8 through 21 now differ from the horizontal axes in plots 200, 405 of Figure 2 and Figure 4 in that the horizontal axes of the plots in Figures 8 through 21 now display units of time in microseconds whereas before the horizontal axes displayed integer multiples of T sw switching periods.
  • the legend 802 affixes a physical value of 1.8 volts to the normalized set-point value for this particular example.
  • the horizontal cursor 805 gauges the response curve 801 rise to within 2% of the normalized set-point, in a period that vertical cursor 804 minus vertical cursor 803 delineates.
  • Figure 9 represents an alternate view 900 of the time domain response curve 801 whereby the horizontal cursors 901, 905 and vertical cursors 903, 904 now measure the response times of the second exemplary transition from the same simulation that produced response curve 801 in plot 800 of Figure 8 .
  • the legend 902 affixes a physical value of 1.5volts to, while horizontal cursor 901 gauges the approach to within 2% of, the second power state set-point.
  • Horizontal cursor 905 and vertical cursor 903 delineate the point of departure from the previous power state.
  • Vertical cursor 904 minus vertical cursor 903 yields a response time of 24.48 microseconds.
  • a pulse sequence describable by equations such as equation 608 with parameters n 1 equal to four and n 2 equal to two driving the same previously specified plant components further illustrates the relation 612 of Figure 6 compared to the previous transition measured in Figure 8 of greater magnitude
  • Figure 10 illustrates the simulation plot 1000 of a response curve 1001 with horizontal cursors 805, 1005 and vertical cursors 1003, 1004 once again measuring the second transition of equal magnitude
  • this simulation plot 1000 With exactly the same values for n 1 and n 2 for the second transition as in the previous simulation plot 900, this simulation plot 1000, with the legend 1002 once again affixing the physical value to 1.8 volts, vertical cursor 1004 minus 1003 yields a value of time to arrive within 2% of the second power state set-point of 23.22 microseconds.
  • This response time for plot 1000 appears close though not exactly equal to the response time of plot 900, due measurement error and error arising from using a fixed A DE instead of a unique A DE for each power state.
  • Figure 11 exhibits a response curve 1101 in a time domain plot 1100 wherein the vertical cursors 1103, 1104 and horizontal cursors 1105, 1106 delineate the response time and change of amplitude for a second transition of lesser magnitude
  • legend 1102 affixes the physical value of 1.65 volts to the normalized set-point, thus horizontal cursor 1106 delineates the departure from 1.5V to the cursor 1105 delineating the approach to within 2% of the set-point of 1.65 volts.
  • Vertical cursor 1104 minus 1103 measures the response time equal to 17.99 microseconds.
  • Figure 12 exhibits a response curve 1201 in a time domain plot 1200 wherein the vertical cursors 1203, 1204 and horizontal cursors 1202, 805 delineate the response time and change of amplitude for a second transition of greater magnitude ( ⁇ T Set(m)
  • the values of n 1 and n 2 for the second transition of this response curve 1201 remain the same as in the previous response curves 801, 901, 1001, 1101 time domain plots 800, 900, 1000, 1100.
  • horizontal cursor 805 marks the approach to within 2% of the set-point of 1.8V according to the legend 1202 whereas the horizontal cursor 1205 delineates the point of departure from 1.2 volts.
  • Figure 13 resembles Figure 11 in that the second transition of both response plots 1300 and 1100, respectively exhibit a transition of equal magnitude but opposite direction again.
  • Legend 1302 like legend 1102 affixes the physical value of 1.65 volts to the normalized set-point for the second power state after the second transition.
  • Horizontal cursors 905, 1305 and vertical cursors 1303, 1304 demarcate the amplitude and time of the approach of the response curve 1301 to within 2% of the second power state set-point.
  • Vertical cursor 1304 minus vertical cursor 1303 yields a response time value of 17.15 microseconds, once again differing slightly from the response time of plot 1100.
  • the inventor found the fixed A DE by following the aforementioned method implied by equation 602 using a Vout of 1.65 volts.
  • Using this fixed A DE for all power states causes an error of +0.33% for a set-point of 1.5 volts, an error of -0.34% for a set-point of 1.8 volts and an error of +1.33% for a set-point of 1.2 volts in the exemplary system under development.
  • the plots 1400 and 1500 of Figures 14 and 15 differ from the other plots of Figures 8 through 21 in that the vertical axes on the left hand side of the plots 1400, 1500 now display a scale of amperes instead of a normalized set-point scale.
  • the legend 1402 assigns response curve 1401 the description of load current plus noise current for the plot 1400.
  • plot 1500 has legend 1504 to do the same for response curve 1503
  • legend 1502 also affixes the typical physical value for the response curve 1501 to the axis displaying the normalized scale on the right hand side of plot 1500, in this case a physical value of 1.65 volts.
  • plots 1400 and 1500 portray the response curves 1401, 1501, 1503 of the exemplary system under development, for the same simulated transitions of plot 1300, only now under the influence of added high frequency and low frequency noise, respectively, as a customary test of stability employed during power supply design.
  • Plot 1400 illustrates the effect of 10 MHz, 50 milliampere, 50% duty cycle noise added
  • plot 1500 illustrates the effect of 10 KHz, 50 milliampere, 50% duty cycle noise added.
  • the noise current 1401 has an envelope that would obliterate the view of a voltage response curve and therefore this specification omits the voltage response curve herein substituting several written statistics.
  • Plot 1500 shows the use of horizontal cursors 1505, 1506 in this manner to determine the voltage response curve 1501 deviates from the ideal set-point by less than 1.7% in either positive or negative direction while vertical cursors 1507, 1508 merely demarcate where the peak deviations occur on the time scale.
  • the remaining response plots 1600, 1700, 1800, 1900, 2000, and 2100 in Figures 16 through 21 illustrate the effect of the physical plant and load parameter values differing from those which the designer estimated in the design of the present system under development.
  • the designer easily achieves the effect of deviation of plant and load parameter values in simulation by manually changing lines 501, 502, 519, 520 of code as documented in the simulation code sheet 500 of Figure 5 .
  • this specification will highlight a particularly effectual subset of operational corners one may encounter in the design of the exemplary system under development visible in the remaining response plots.
  • the legends 1602, 1702, 1802, 1902, 2002, 2102 affix the physical value of greatest magnitude thus far, 1.8 volts to the normalized set-point of the remaining response curves 1601, 1701, 1801, 1901, 2001, 2101, respectively.
  • Response curve 1601 in plot 1600 of Figure 16 once again presents the first transition to a normalized set-point to which legend 1602 affixes the physical value of 1.8 volts.
  • the horizontal cursor 805 delineates the approach to within 2% of the set-point whereby one can readily see a pronounced overshoot phenomenon has occurred.
  • Both the inductance value in line 501 and the capacitance value in line 502 of the simulation code sheet 500 have simultaneously increased 10% beyond their nominal values to which the designer has applied the pulse width modulation sequence of the present invention. Even in such adverse conditions, the aberration of overshoot extends less than 1.6% beyond the set-point according to measurements facilitated by the use of the horizontal cursor 805.
  • Vertical cursor 1604 minus vertical cursor 1603 demarcates the period of rise from 0% to 98% amplitude equal to 31.65 microseconds.
  • this response curve 1601 depicting an under-driven operational state, although the resultant overshoot phenomenon renders this under-driven principle counterintuitive.
  • Cursor 1704 minus 1703 exhibits the 0% -to-98% amplitude rise time which substantiates the notion of an under-driven control plant with the time now equal to 37.03 microseconds, slower than the previous response 1601. Nevertheless, the 0% -to- 95% amplitude rise time remains below 32 microseconds for the compensated response 1701, allowing implementation of the same simple aforementioned "power-good" circuit and output signal despite the need for compensation for excessive plant component values.
  • the simulation that generated plot 1800 of Figure 18 presents the condition whereby one can noticeably see an anomalous response curve 1801 has occurred.
  • both the inductance value in line 501 and the capacitance value in line 502 of the simulation code sheet 500 have simultaneously decreased 10% below their nominal values to which the designer has applied the pulse width modulation sequence of the present invention. Given these lower component values qualifies this as an overdriven condition, but once again, the aberration of overshoot extends less than 1.6% beyond the set-point according to measurements facilitated by the use of the horizontal cursor 805.
  • vertical cursor 1804 minus vertical cursor 1803 demarcates the period of rise from 0% to 98% amplitude equal to 39.12 microseconds, and thus even the 0% - to- 95% amplitude rise time, at 34.52 microseconds exceeds the benchmark rise time of less than 32 microseconds which permits implementation of the aforementioned "power-good" circuit and output signal.
  • the invention enables compensation for the overdriven case, by making a coarse adjustment to n 1 and fine tuning n 2 , only this time, in the opposite direction compared to the previous case of an under-driven plant In doing so, setting n1 equal to six and n2 equal to one, the design achieves the response 1901 of simulation plot 1900 in Figure 19 .
  • vertical cursor 1904 minus vertical cursor 1903 now yields a 0% -to- 98% rise time of 35.57 microseconds and a 0% -to- 95% rise time of 30.75 microseconds, once again, allowing implementation of the same simple aforementioned "power-good" circuit and output signal despite the need for compensation for less than nominal plant component values.
  • molybdenum permalloy powder "distributed gap" cores for inductors have proliferated the marketplace availing designers to inductors that retain 5% tolerance in inductance over the range of current described therein.
  • X7R ceramic materials that retain a capacitance tolerance within 10% over the bias voltage described therein have reached a cost effective price. Both of these inductive and capacitive components of advanced materials retain these tolerances while operating over the 0 -to- 70 degree Celsius temperature range. Thus, the present invention and its ability to compensate for plant component value deviations along with components of advanced materials, satisfy a wide range of applications.
  • response plot 2100 illustrates the response curve 2101 resulting from under-driven plant components due to a load at 133% of rated current.
  • Figure 22 illustrates a block diagram of a closed loop control plant comprising the pulse width modulation controller 2200, along with the feedback block 2215, but excludes the inductive, capacitive, and switching elements needed for implementation within an exemplary embodiment of the present invention.
  • Some functional blocks within Figure 22 duplicate those described in the reference patent, but the specification of the present invention adds circuitry around, and supplemental features within these functional blocks to extend the complete system beyond the scope of the reference patent.
  • the clock output 2212 of oscillator circuit 2214 feeds a counter 2206 that derives the power supply switching frequency, F sw , and duty cycle through decoder 2208, with D flip-flop 2211 responding to signals 2209 and 2210 to form the output 2213 that feeds the gate driver Vgdrvr that drives the switching transistors 406, 407.
  • the pulse width modulation controller 2200 may hold values for power supply duty cycle relative to various supply current states.
  • the pulse width modulation controller 2200 may hold power supply duty cycle values in decode logic configurations, or stored in registers or memory locations as depicted by block 2203A, and thus fix the power supply output precisely for every power state.
  • Block 2203 or 2203A may also comprise a portion of or the entire aforementioned state machine controlling the system during transitions.
  • the decoder 2208 compares the frequency dividing clock count on bus 2207 to a value on bus 2205 that represents a duty cycle value corresponding to the present power state, or scaled pulse width during transitions, that obtains the correct output voltage or step response by resetting D flip-flop 2211 by asserting pulse signal 2209 at the correct time.
  • the present invention may use these offset values to compensate any step response or power state by adjusting n 1 , n 2 , A DE , or
  • bus 2222 from core feedback block 2215 providing an additional coefficient to the arithmetic logic unit 2203 can close the loop for an exemplary system.
  • core feedback block 2215 inherently must draw power from the output voltage source, in other words, the core voltage in the exemplary system under development, in order to accurately provide feedback.
  • a phase lock loop within the timing control block 2216 takes the clock output 2212 from an oscillator 2214 to produce a higher frequency digital clock 2217 that synchronizes the delay pulse controller 2219 and delay measurement flip-flops 2218 to the pulse width modulation controller 2200.
  • the digital clock 2217 also feeds the rest of the synchronous application logic not shown, in the digital core and may vary in speed dependent upon the application and thus affect the power state of the entire exemplary system under development.
  • the delay pulse controller 2219 controls the output 2220 providing a pulse that propagates through a delay chain symbolized by buffers 2221, as the timing control block 2216 determines using signal 2223 the exact moment the delay measurement flip-flops 2218 sample the delay chain buffers 2221.
  • the arithmetic logic unit 2203 receives from bus 2222 a vector indicating the number of delay chain buffers 2221 through which the pulse from the controller output 2220 propagated, measured by flip-flops 2218.
  • the arithmetic logic unit 2203 decodes and compares this vector to an expected value of delay that guarantees margin in the safe operating range for the rest of the synchronous application logic within the digital core.
  • the system designer may find this expected value of delay by determining the longest delay path in the synchronous application logic within the digital core as given by the design automation tools, and then replicating a delay chain of buffers 2221 of approximately twice the length of this maximum core application logic delay path plus safety margin.
  • the present invention herein defines a coefficient for this propagation time, A TP , equal to the ratio of the vector originating from buffers 2221 divided by the quantity of core application logic maximum delay path expected value plus margin.
  • any embodiment which automates these rote processes does not constitute a departure from the scope and spirit of the present invention.
  • any computer program, computer script, spreadsheet, simulation tool, or other design automation tool that automates: the aforementioned time domain tuning; the generation or adjustments to variables or coefficients n 1 , n 2 , A V , A DE , A TP , T SW ; the generation or alteration of a hardware description language that specifies or models the control plant such as, but not limited to, VHDL, Verilog HDL, or System C, et cetera; the generation of pulse width dithering; or analysis such as margining the plant component capacitance, inductance, switching loss, load current values, or Monte Carlo analysis, clearly does not present a substantial departure from the scope and spirit of the present invention.

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EP10173926A 2006-10-13 2007-10-11 Séquence d'impulsions modulées en largeur générant une réponse indicielle apériodique critique Withdrawn EP2254008A1 (fr)

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US11/549,586 US7889019B2 (en) 2006-10-13 2006-10-13 Pulse width modulation sequence generating a near critical damped step response
EP07844184A EP2076822B1 (fr) 2006-10-13 2007-10-11 Séquence de modulation d'impulsions en durée générant une réponse à amortissement quasi-critique

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