EP2250541A2 - Dispositif d'alimentation d'un circuit électronique, en particulier d'un circuit numérique, et procédé associé - Google Patents
Dispositif d'alimentation d'un circuit électronique, en particulier d'un circuit numérique, et procédé associéInfo
- Publication number
- EP2250541A2 EP2250541A2 EP09721479A EP09721479A EP2250541A2 EP 2250541 A2 EP2250541 A2 EP 2250541A2 EP 09721479 A EP09721479 A EP 09721479A EP 09721479 A EP09721479 A EP 09721479A EP 2250541 A2 EP2250541 A2 EP 2250541A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- voltage
- frequency
- hιgh
- duration
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present invention relates to a device for supplying an electronic circuit, in particular a digital circuit, and to a related method.
- a power supply module capable of delivering throughout the operation a variable voltage over a continuous range of values, generally realized in the form of a DC-DC converter.
- the presence of such a module is problematic whatever the technology envisaged: the use of external choppers is naturally not suited to the integration of all the elements in an integrated circuit; the use of internal choppers is very expensive (in terms of substrate surface or because of the processes used) because of the presence of many passive components; linear converters suffer from a low efficiency.
- the invention proposes a device for supplying an electronic circuit capable of applying to the electronic circuit at least a first voltage or a second voltage different from the first voltage, characterized in that it comprises:
- Application means adapted to apply to the circuit the first voltage and the first frequency during the first duration, and the second voltage and the second frequency during the second duration.
- the average operating point of the circuit can be set within a continuous set of operating points, in particular in order to adapt better to the received constraint, and while using a discrete number (generally equal to two) of available voltages, taking into account the operating conditions of the circuit.
- the means for determining the first frequency are also capable of determining the second frequency as a function of at least one operating parameter of the circuit, so as to also use a second frequency optimized at the current operating conditions.
- These means may use means for measuring said parameter within the electronic circuit, several examples of which are given in the description which follows.
- the information represents for example an objective frequency and the determination means can then be able to determine the first duration and the second duration so that the circuit operates at an effective average frequency greater than the objective frequency.
- the application means are able to periodically implement a period (that is to say a cycle) formed successively from the application of the first voltage and the first frequency, and the application of the second voltage and the second frequency.
- the duty cycle i.e., the relative duration of application of the first frequency and the first voltage with respect to the total duration of the period
- the means for determining the first duration and the second duration may be able to determine a ratio between the first duration and the second duration (directly linked to the duty cycle that has just been mentioned) as a function of at least the first frequency. This influences the average effective frequency.
- Said operating parameter represents for example an instantaneous operating condition of the circuit, which makes it possible to reactualize the first and second durations (for example their ratio related to the duty cycle) regularly, dynamically.
- the means for determining the first frequency may be able to also determine the second frequency as a function of at least one instantaneous operating condition of the circuit.
- the means for determining the first duration and the second duration are able to determine the ratio between the first duration and the second duration (directly related to the duty cycle) as a function of the first frequency and the second frequency. , dynamically as already indicated.
- the application means comprise a frequency selector receiving a first clock signal having the first frequency and a second clock signal having the second frequency, and applying to the electronic circuit the first signal of clock during the first duration and the second clock signal during the second duration.
- the application means comprise a clock generator capable of generating and applying to the electronic circuit a first clock having the first frequency during the first duration and a second clock having the second frequency during the second time. duration.
- the application means may also comprise a voltage selector receiving the first voltage and the second voltage, and applying to the electronic circuit the first voltage during the first duration and the second voltage during the second duration.
- This voltage selector comprises according to a possibility of implementation:
- the voltage selector can then also include:
- variable voltage means for controlling the variable voltage of a value equal to the second voltage to a value equal to the first voltage.
- the variable voltage is applied only during the transition phases between the first voltage and the second voltage (short-duration phases with respect to the total duration of operation); this variable voltage can, for example, be generated by means of a linear converter without any appreciable effect on the efficiency taken over the total duration of operation.
- the constraint is for example temporal (and expressed in this case as a time or a frequency), although other possibilities are conceivable, such as a constraint in average power consumed.
- the electronic circuit is often in practice a digital circuit, for example made in CMOS technology.
- the invention also proposes, in an original manner in itself, a device for supplying an electronic circuit capable of applying to the electronic circuit at least a first voltage or a second voltage different from the first voltage, characterized in that it comprises :
- means for receiving information defining a constraint means for determining a first number of clock cycles and a second number of clock cycles, such as the operation of the circuit at a first frequency associated with the first voltage during the first number of clock cycles; and at a second frequency associated with the second voltage during the second number of clock cycles respects said constraint;
- Application means adapted to apply to the circuit the first voltage and the first frequency during the first number of clock cycles, and the second voltage and the second frequency during the second number of clock cycles.
- synchronization means capable of synchronizing (the beginning of) the application of the first voltage and (the beginning of) a treatment to be performed with said constraint.
- the total number of clock cycles required for processing is then predetermined, for example; the constraint may in practice be the time in which it is desired to perform the treatment.
- the aforementioned frequencies are predetermined (for example at the design of the system or during a calibration phase of the circuit) in order to ensure a safe operation thereof taking into account possible variabilities and drifts. , and possibly stored within the determination means, always for the purpose of minimizing the energy consumed by the circuit.
- the invention also proposes a method of supplying an electronic circuit by means of at least a first voltage or a second voltage different from the first voltage, characterized in that it comprises the following steps:
- FIG. 1 shows the main elements of a system according to the teachings of the invention
- FIG. 2 represents such a system according to a first application example
- FIG. 3 illustrates the variations of supply voltage and clock frequency present during the implementation of the system of FIG. 2;
- FIG. 4 represents a second example of application of the invention
- FIG. 5 presents timing diagrams illustrating the operation of the system of FIG. 4.
- FIG. 1 represents the elements of a device for supplying a functional heart 10, for example a synchronous electronic circuit realized in CMOS digital logic.
- the elements of this device described in the following can be brought together in the same integrated circuit as the functional heart 10, and therefore made in CMOS technology. As a variant, all or some of these elements could however be made in the form of an external module at the functional heart 10.
- the feed device is described in the form of functional elements. Several functions could, however, be performed by the same element in certain modes of implementation.
- any synchronous digital circuit is capable of operating at a maximum frequency F max , which can not be measured directly and varies over time according to intrinsic and extrinsic factors.
- the intrinsic factors are the variability of the manufacturing process and aging; the extrinsic factors are the supply voltage and the temperature. It is also considered that operating the circuit faster than this frequency causes time delays that lead to the corruption of the circuit function.
- the power supply device of FIG. 1 comprises an adaptation controller 12 which receives on the one hand a high voltage V hig and a low voltage V
- the communication between the probes 30, 31, 32 and the adaptation controller 12 (in particular to control the probes and to increase the value of the monitored parameters towards the controller) can be done by any appropriate means, for example by means of signals analog, digital, or any combination of these types of signals.
- the adaptation controller 12 therefore drives the probes 30, 31, 32 and collects the values of the operating parameters measured by these probes, in particular for the purpose of comparing these values with stored calibration values, for example in an associated non-volatile memory. to the adaptation controller, or to values produced by reference sources (typically frequency, voltage or reference current).
- reference sources typically frequency, voltage or reference current
- the adaptation controller estimates for each of the supply voltages envisaged in the device (that is to say here for the high voltage V hig and the low voltage V
- This estimation of a frequency associated with each supply voltage value can be achieved by known voltage-frequency torque determination techniques allowing safe operation of the system as described for example in the article, for example by simulation or by calibration by means of a speed test carried out after manufacture of the circuit. Note, however, that there is provided here the determination of an operating frequency for each available voltage source, not the adaptation of the voltage to a desired frequency.
- the estimated maximum frequency F max practices _ es t ⁇ m associated with each supply voltage must be performed at regular intervals, with a period dependent constant of time variations to compensate.
- the adaptation controller 12 controls clock generators 16, 18 (and precisely here a first clock generator 16 associated with the low voltage V
- a performance controller 22 receives the different clock signals H
- the performance controller 22 could also alternatively receive the frequency values associated with each supply voltage directly from the adaptation controller 12.
- the solution proposed in FIG. 1 allows the performance controller 22 to work on the clock signals. effectively generated, as applied to the heart as described below.
- the performance controller also receives information C representing a performance constraint, for example frequency or time, to be respected by the power device.
- This constraint is determined, for example, by the application (in the "logicieP" sense) implemented by the core 10, depending in particular on the needs of this application.
- the performance controller 22 determines the respective duration of application of the two supply voltages, here for example in the form of the ratio X between the application time of the high voltage V high and the accumulated time of application of the two voltages, allowing to best comply with the constraints defined in the information C.
- C is a constraint expressed in frequency form F ta rget the system is dimensioned so that this frequency constraint F ta rget is between the possible values of F
- the ratio X determined by the performance controller 22 is transmitted to a transition sequencer 24 which drives a voltage selector 14 and a frequency selector 20 (using respectively a hopv voltage control and a control of frequency ⁇ OP F ) so that the selectors 14, 20 respectively apply the high voltage V h ⁇ gh and the associated clock signal H h ⁇ gh for the duration defined by the performance controller 22 (here a proportion X of the time), and the low voltage V
- the transition sequencer 24 ensures in particular that the low voltage V
- the voltage selector 14 receives on the one hand the voltage V h ⁇ gh and on the other hand the voltage V
- the frequency selector 20 receives the clock signals H
- V CO is referenced V CO re the voltage applied to the heart 10 by the voltage selector 14 and the Hcore F ⁇ re frequency clock signal applied to the heart 10 by the frequency selector 20.
- the performance controller 22 will take into account the interruption time of the operation of the heart 10 when determining the different durations of application of each voltage in order to respect the stress C.
- the supply device can operate in an optimized manner and adapted to a stress C (which can in turn vary over a continuous range of values) through the variable weighting of the time of use of one voltage source relative to the other and the variable performance (and therefore adaptable to the constraint) that results.
- FIG. 2 shows an embodiment of the invention in an application in which the constraint to be respected is expressed in the form of an operating frequency required by the process implemented by the digital core 110.
- FIG. 2 Each element of FIG. 2 has been assigned a numerical reference increased by 100 with respect to the element having the same function in FIG.
- a matching controller 112 drives a voltage probe 130 and a temperature probe 131.
- the voltage probe 130 measures the supply voltage actually received by the core 110, that is to say taking into account the local power supply drops due to the resistivity of the supply grid.
- the voltage measured by the probe 130 is compared with a reference voltage V r ⁇ f and can thus be converted within the adaptation controller 112 into a digital value representative of this measured voltage.
- the temperature probe 131 also makes it possible to obtain digital information representing the value of the measured temperature.
- the temperature sensor 131 measures, for example, in practice the voltage at the terminals of a diode directly biased by a reference current.
- the voltage across the diode varies depending on the temperature); the measured voltage can in this case also be converted into digital temperature information within the adaptation controller 112.
- the adaptation controller 112 Since the core 110 is subjected to two different supply voltages as explained in detail below, the adaptation controller 112 must be able to distinguish between the different supply phases in order to determine at which desired voltage the measured voltage corresponds. For this purpose, it is possible, for example, to provide a communication between the adaptation controller 112 and the transition sequencer 124 described below (as shown in dashed lines in FIG. 2) or other elements holding information on the applied voltage ( as for example the voltage selector 114).
- the adaptation controller 112 considers as invalid a measurement during which the measured voltage varies significantly (to avoid the case where the measurement takes place during the transition phase between the two voltages). feeding as described below).
- the adaptation controller 112 determines the maximum practical frequencies F max _est ⁇ m_h ⁇ gh and F ma ⁇ _ e st ⁇ m_iow respectively associated with the high voltage V h ⁇ gh and the low voltage V
- the clock generators 116, 118 are for example each of frequency-locked loop type (or FLL) and realized by means of a low-jitter voltage controlled local oscillator and a control loop which slaves the frequency generated with respect to the received frequency setpoint and at a reference frequency F r ⁇ f received by each of the clock generators 116, 118.
- Each clock generator 116, 118 transmits to a performance controller 122 information representing the frequency currently generated by this clock generator (information designated F
- 0W and H hgh generated respectively by the first clock generator 116 and the second clock generator 118 are input of a frequency selector 120 whose operation is described below.
- the performance controller 122 thus receives information representing the frequencies respectively generated by the first generator 116 and the second generator 118, that is to say respectively associated with the low voltage V
- the performance controller 122 also receives, for example in the form of a digitally encoded information, the frequency F ta rget operation required by the process implemented by the heart 110 (which expresses in the present application the constraint that must comply with the feeding device).
- the sizing of the circuit during its design is such that this frequency constraint F ta rget is between the frequencies F
- 0W and H hgh and the performance controller 122 can thus determine a proportion X (in percent) of the total calculation time such as the effective average frequency F ⁇ ff XF h ⁇ gh + (1 -X). F
- 0W is greater than the objective frequency Ftarget-
- 0W , is thus greater than the objective, and thus allows to respect the constraint defined by this one.
- F ⁇ ff is chosen to be sufficiently greater than Ftarget (for example from 1% to 10% higher) to take account of the transition periods between two phases of operation (the operation of the core 110 may in certain cases be interrupted during these periods of time. transition).
- the proportion X thus determined is transmitted to the jump sequencer 124 which controls, on the one hand, the frequency selector 120 (by means of the hopF command) so as to successively apply to the circuit 110 the two clocks H h ⁇ gh and t H
- the sequencer 124 controls the selectors 114, 120 in order to switch from the voltage mode V h ⁇ gh and frequency F h ⁇ gh to the voltage mode V
- the jump sequencer 124 controls the selectors 114, 120 to ensure a constant operation at the voltage V h ⁇ gh and the frequency F h ⁇ gh when the proportion X is 100%, while it controls a constant operation at voltage V
- the voltage selector 114 is for example of the type described in the article "Power Supply Selector for Energy and Area-Efficient Local Dynamic Voltage Scaling" S. Miermont et al.
- the frequency selector 120 is for example of the "harmless" type as described in US Pat. No. 6,501,304.
- Such a voltage selector allows, during a transition phase, to apply to the electronic circuit a variable voltage of a value equal to a first voltage (V
- This voltage selector makes it possible to manage the inverse transition phases by applying the variable voltage to the electronic circuit when this other voltage is applied, by suppressing the application of this other voltage when the variable voltage is applied and by controlling the variable voltage of a value equal to this other voltage at a value equal to the first voltage.
- variable voltage proposed for use in the example described above is used only during the brief transition phases and that a linear converter can therefore be used for the generation this variable voltage without significant impact on the electrical efficiency (the voltage generated by the converter during the operating phases at the voltage V h ⁇ gh corresponding to the maximum voltage thereof and therefore not involving resistive losses).
- FIG. 4 represents an embodiment of the invention applied in the case where the functional heart (here referenced 210) is a block receiving periodically (that is to say all the T da ta) input data, then having a maximum time T ta rget (sometimes referred to as "block latency") to process this input data (the processing requiring N clock cycles) and communicate the processed data to the next block.
- the elements having a function corresponding to an element of FIG. 1 carry an increased reference of 200 relative to this element of FIG. 1.
- the probes 230, 231, 232 used in this embodiment are ring oscillators, as described for example in the article "Product-
- an oscillator with "long-wire" links 230 an oscillator based on high-voltage threshold transistors 231 and an oscillator based on low-voltage threshold transistors 232 can be used.
- oscillator with capacitive elements An adaptation controller 212 regularly measures the frequency of each of the oscillators 230, 231, 232, in particular through a frequency reference F re fi - During the design phase, the operation of the heart 210 was simulated in order to to determine the variations of its maximum operating frequency as a function, in particular, of the supply voltage and the temperature.
- the variations of the frequency of each of the oscillators mentioned above as a function of the same parameters are known so that one can determine the maximum usable frequencies F max _est ⁇ m_h ⁇ gh and F ma ⁇ _ e st ⁇ m_iow respectively at the high voltage V h ⁇ gh and at the low voltage V
- the Monte-Carlo type simulations can for example be used in this context.
- 0W are transmitted on the one hand to a clock generator 220, for example made by a phase locked loop (or PLL Phase Locked Loop) receiving a reference signal F r ⁇ f2 and other Part of a performance controller 222.
- a phase locked loop or PLL Phase Locked Loop
- the performance controller 222 determines the number of cycles d clock to which the heart 210 must work the high frequency F max _est ⁇ m_h ⁇ gh (from the N clock cycles necessary for processing data as mentioned above), taking into account also the transition time T tra ns ⁇ t ⁇ on necessary to transition from one mode of operation to the other, so that the processing time does not exceed the target time T ta rget- This amounts to saying that the performance controller 222 determines the number K which verifies:
- T i.sag ei. * + N ⁇ K + T. .
- the number K of operating cycles at the frequency Fmax_est ⁇ m_h ⁇ gh (and therefore at the voltage V h ⁇ gh ) is communicated by the performance controller 222 to a jump sequencer 224 which controls the clock generator 220 by means of a hopF signal of so that the generator 220 operates at the frequency F max _est ⁇ m_h ⁇ gh (received from the adaptation controller 212) during the first K clock cycles of the processing and at the frequency Fmax_est ⁇ m_iow (also received from the adaptation controller 212) during the NK cycles following.
- the operation of the jump sequencer 224 and that of the heart 210 is synchronized, for example by exchanging synchronization information (referenced synchro in FIG. 4).
- the jump sequencer 224 also controls a voltage selector 214 so that it applies the high voltage V hig during the first K clock cycles and the low voltage V
- the voltage selector 214 is for example of the type described in the article "VDD-Hopping Accelerator for On-chip Power Supplies Achieving
- a time constraint (expressed as frequency or latency time to be complied with) has been considered above, the constraint could be of a different nature; it could be for example a mean power consumption constraint (the operating time at high frequency is limited so as to respect this constraint).
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Power Sources (AREA)
- Logic Circuits (AREA)
- Control Of Voltage And Current In General (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0851471A FR2928496B1 (fr) | 2008-03-06 | 2008-03-06 | Dispositif d'alimentation d'un circuit electrique, en particulier d'un circuit numerique |
PCT/FR2009/050369 WO2009115744A2 (fr) | 2008-03-06 | 2009-03-06 | Dispositif d'alimentation d'un circuit électronique, en particulier d'un circuit numérique, et procédé associé |
Publications (1)
Publication Number | Publication Date |
---|---|
EP2250541A2 true EP2250541A2 (fr) | 2010-11-17 |
Family
ID=40001372
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP09721479A Withdrawn EP2250541A2 (fr) | 2008-03-06 | 2009-03-06 | Dispositif d'alimentation d'un circuit électronique, en particulier d'un circuit numérique, et procédé associé |
Country Status (5)
Country | Link |
---|---|
US (1) | US8621257B2 (fr) |
EP (1) | EP2250541A2 (fr) |
JP (2) | JP2011518364A (fr) |
FR (1) | FR2928496B1 (fr) |
WO (1) | WO2009115744A2 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103731031B (zh) * | 2012-10-16 | 2018-01-02 | 中兴通讯股份有限公司 | 电源及电源调压方法 |
JP2015216267A (ja) * | 2014-05-12 | 2015-12-03 | キヤノン株式会社 | 電源圧制御システム |
US9978437B2 (en) | 2015-12-11 | 2018-05-22 | Micron Technology, Inc. | Apparatuses and methods for dynamic voltage and frequency switching for dynamic random access memory |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11118845A (ja) | 1997-10-16 | 1999-04-30 | Matsushita Electric Ind Co Ltd | 周波数−電圧変換回路およびその方法、並びに周波数−電圧変換回路を備えたシステム |
US6023641A (en) * | 1998-04-29 | 2000-02-08 | Medtronic, Inc. | Power consumption reduction in medical devices employing multiple digital signal processors |
JP4380986B2 (ja) | 2000-09-08 | 2009-12-09 | 富士通株式会社 | クロック制御装置及びその記録媒体 |
US7596709B2 (en) * | 2000-12-30 | 2009-09-29 | Intel Corporation | CPU power management based on utilization with lowest performance mode at the mid-utilization range |
US6845456B1 (en) * | 2001-05-01 | 2005-01-18 | Advanced Micro Devices, Inc. | CPU utilization measurement techniques for use in power management |
JP4139579B2 (ja) | 2001-06-19 | 2008-08-27 | 株式会社ルネサステクノロジ | 半導体装置および半導体装置の動作モード制御方法 |
US6501304B1 (en) * | 2001-10-11 | 2002-12-31 | International Business Machines Corporation | Glitch-less clock selector |
JP3979062B2 (ja) | 2001-11-08 | 2007-09-19 | ソニー株式会社 | 周波数制御回路 |
EP1462915A3 (fr) * | 2003-03-26 | 2009-01-21 | Panasonic Corporation | Appareil et procédé de contrôle d'horloge |
JP4033066B2 (ja) * | 2003-05-07 | 2008-01-16 | ソニー株式会社 | 周波数制御装置、情報処理装置、周波数制御方法及びプログラム |
US7770034B2 (en) * | 2003-12-16 | 2010-08-03 | Intel Corporation | Performance monitoring based dynamic voltage and frequency scaling |
US7282966B2 (en) * | 2004-09-28 | 2007-10-16 | Intel Corporation | Frequency management apparatus, systems, and methods |
US7386737B2 (en) * | 2004-11-02 | 2008-06-10 | Intel Corporation | Method and apparatus to control temperature of processor |
US7346787B2 (en) * | 2004-12-07 | 2008-03-18 | Intel Corporation | System and method for adaptive power management |
WO2007049100A1 (fr) * | 2005-10-27 | 2007-05-03 | Freescale Semiconductor, Inc. | Systeme et procede pour la commande de niveau de tension et de frequence d'horloge fournies a un systeme |
US7444528B2 (en) * | 2005-12-06 | 2008-10-28 | Intel Corporation | Component reliability budgeting system |
US8135966B2 (en) * | 2006-06-22 | 2012-03-13 | Freescale Semiconductor, Inc. | Method and device for power management |
DE102006055638B4 (de) * | 2006-11-24 | 2008-10-30 | Infineon Technologies Ag | Schaltungsanordnung und Verfahren zur Energieversorgung und Taktung für getaktete Verbraucher |
EP2147362B1 (fr) * | 2007-04-23 | 2011-12-14 | ST-Ericsson SA | Dispositif électronique et procédé pour y réaliser la gestion de l'alimentation |
JP2009122922A (ja) * | 2007-11-14 | 2009-06-04 | Panasonic Corp | データ処理装置 |
US8239694B2 (en) * | 2008-03-31 | 2012-08-07 | Qualcomm, Incorporated | Dynamic frequency scaling of a switched mode power supply |
TWI374355B (en) * | 2008-08-22 | 2012-10-11 | Asustek Comp Inc | Computer system capable of dynamically changing core voltage/frequency of cpu |
TWI372330B (en) * | 2008-08-22 | 2012-09-11 | Asustek Comp Inc | Computer system capable of dynamically cahaging operation voltage and frequency of cpu |
US8458498B2 (en) * | 2008-12-23 | 2013-06-04 | Intel Corporation | Method and apparatus of power management of processor |
US8064197B2 (en) * | 2009-05-22 | 2011-11-22 | Advanced Micro Devices, Inc. | Heat management using power management information |
US8190939B2 (en) * | 2009-06-26 | 2012-05-29 | Microsoft Corporation | Reducing power consumption of computing devices by forecasting computing performance needs |
FR2947924A1 (fr) * | 2009-07-07 | 2011-01-14 | Thales Sa | Procede et dispositif pour la gestion dynamique de la consommation dans un processeur |
US8510582B2 (en) * | 2010-07-21 | 2013-08-13 | Advanced Micro Devices, Inc. | Managing current and power in a computing system |
-
2008
- 2008-03-06 FR FR0851471A patent/FR2928496B1/fr not_active Expired - Fee Related
-
2009
- 2009-03-06 US US12/921,103 patent/US8621257B2/en not_active Expired - Fee Related
- 2009-03-06 JP JP2010549185A patent/JP2011518364A/ja active Pending
- 2009-03-06 EP EP09721479A patent/EP2250541A2/fr not_active Withdrawn
- 2009-03-06 WO PCT/FR2009/050369 patent/WO2009115744A2/fr active Application Filing
-
2013
- 2013-12-27 JP JP2013272476A patent/JP2014089748A/ja active Pending
Non-Patent Citations (1)
Title |
---|
See references of WO2009115744A2 * |
Also Published As
Publication number | Publication date |
---|---|
WO2009115744A3 (fr) | 2009-12-03 |
JP2011518364A (ja) | 2011-06-23 |
US8621257B2 (en) | 2013-12-31 |
FR2928496A1 (fr) | 2009-09-11 |
US20110029795A1 (en) | 2011-02-03 |
WO2009115744A2 (fr) | 2009-09-24 |
FR2928496B1 (fr) | 2015-09-25 |
JP2014089748A (ja) | 2014-05-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10651683B2 (en) | Harvesting power from ambient energy in an electronic device | |
Tschanz et al. | Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging | |
EP1759460B1 (fr) | Commande adaptative d'alimentation electrique de circuits integres | |
US8615687B2 (en) | Data processing system and method for regulating a voltage supply to functional circuitry of the data processing system | |
JP6185741B2 (ja) | 周波数同期ループ回路及び半導体集積回路 | |
US20040183588A1 (en) | Adaptive power supply and substrate control for ultra low power digital processors using triple well control | |
JP2010118746A (ja) | 半導体集積回路及びクロック同期化制御方法 | |
CN111106831B (zh) | 振荡频率控制系统及方法 | |
TWI441009B (zh) | 用於電腦系統之處理單元的時脈頻率調整方法及相關裝置 | |
EP2250541A2 (fr) | Dispositif d'alimentation d'un circuit électronique, en particulier d'un circuit numérique, et procédé associé | |
EP1993019A1 (fr) | Dispositif d'alimentation d'un circuit électronique et circuit électronique | |
WO2015118145A1 (fr) | Procédé de caractérisation du fonctionnement d'un circuit électronique numérique et circuit électronique numérique | |
CN107769774B (zh) | 具有提高的精度的振荡器装置及相关方法 | |
EP4038476B1 (fr) | Dispositif de generation d'une tension d'alimentation / polarisation et d'un signal d'horloge pour un circuit numerique synchrone | |
EP3120458B1 (fr) | Procédé et circuit d'ajustement de la fréquence d'un signal d'horloge | |
FR2916061A1 (fr) | Variation de frequence d'horloge d'un consommateur de courant synchronise. | |
US8055925B2 (en) | Structure and method to optimize computational efficiency in low-power environments | |
JP5131370B2 (ja) | 電源電圧調整装置および電源電圧調整方法 | |
US9824773B1 (en) | Apparatus and method to adjust power and performance of integrated circuits | |
JP5890998B2 (ja) | 半導体装置および電源供給方法 | |
De | Energy efficient computing in nanoscale CMOS: Challenges and opportunities | |
EP3627680A1 (fr) | Procédé de réglage d'un signal de modulation de largeur d'impulsion pilotant un régulateur de tension à découpage du type abaisseur de tension, et dispositif correspondant | |
Cochet et al. | Experimental model of adaptive body biasing for energy efficiency in 28nm UTBB FD-SOI | |
WO2014199545A1 (fr) | Circuit intégré à semi-conducteurs et système d'interface de données doté de ce dernier | |
FR2992073A1 (fr) | Dispositif d'alimentation d'un circuit electronique |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20100902 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK TR |
|
AX | Request for extension of the european patent |
Extension state: AL BA RS |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: VIVET, PASCAL Inventor name: REBAUD, BETTINA Inventor name: BEIGNE, EDITH Inventor name: MIERMONT, SYLVAIN |
|
DAX | Request for extension of the european patent (deleted) | ||
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
INTG | Intention to grant announced |
Effective date: 20151021 |
|
RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: BEIGNE, EDITH Inventor name: VIVET, PASCAL Inventor name: MIERMONT, SYLVAIN Inventor name: REBAUD, BETTINA |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
18D | Application deemed to be withdrawn |
Effective date: 20160301 |