EP2243160A2

EP2243160A2 - Contactless object with integrated circuit connected to circuit terminals by capacitive coupling

Info

Publication number: EP2243160A2
Application number: EP09722630A
Authority: EP
Inventors: Yannick Grasset
Original assignee: Individual
Current assignee: Individual
Priority date: 2008-02-13
Filing date: 2009-02-13
Publication date: 2010-10-27
Also published as: FR2927441A1; US20110139878A1; US9142485B2; WO2009115673A3; WO2009115673A2; FR2927441B1

Abstract

The invention relates to integrated circuits (1) that comprise, on the active surface thereof, a first dielectric layer defining a passivation layer (6) and contact pads (5) flush through openings (7) in said passivation layer, wherein said integrated circuits are to be incorporated in contactless portable objects (10) for connection by capacitive coupling to the terminals (13) of an antenna-forming circuit (11) mounted on a substrate (12) of said object. The invention also relates to contactless portable objects including such circuits. The invention is characterised in that the capacitive coupling is carried out using connection plates (8) of the integrated circuits, positioned at the surface of the passivation layer and electrically connected to the contact pads. The invention can particularly be used in UHF RFID objects.

Description

CONTACTLESS OBJECT WITH INTEGRATED CIRCUIT CONNECTED TO THE TERMINALS OF A CIRCUIT BY CAPACITIVE COUPLING

The invention relates to portable non-contact objects comprising integrated circuits, as well as methods of manufacturing these non-contact objects. It relates more particularly to objects whose integrated circuits comprise, at their active face, a first passivation layer of dielectric layer and connection pads flush through openings of said passivation layer, for a connection, by capacitive coupling, at the terminals of an antenna circuit mounted on a support of said objects.

The portable non-contact objects referred to in the present invention are card-sized objects, called smart cards, having a non-contact mode of operation, or else objects of various formats, intended in particular for radio frequency identification (RFID). ), for example, replacing barcodes. These last objects of various formats are commonly called electronic tags ("tags" in English) or inlay (English).

Such portable non-contact objects of the prior art comprise, on the one hand, an integrated circuit and, on the other hand, an antenna conducting circuit. The terminals of the antenna circuit are connected to the integrated circuit for transmitting and receiving radio frequency signals between a remote reader and said circuit.

The connection of the contact pads of the integrated circuit to the terminals of an antenna conducting circuit is carried out according to different methods. Generally, it is performed using the so-called wire bonding method. In that case, the contact pads of the integrated circuit are connected to the contact terminals of the antenna conductor circuit by generally gold connection wires. Two welding operations are then necessary for each contact. A first, on the connection pads of the integrated circuit and, a second, on the terminals of the antenna circuit. Alternatively, the connection can be made using a method of connection by means of protrusions ("bumps", in English). In this case, a ball, usually made of gold, is deposited on the contact pads of the integrated circuit. This is subsequently returned ("flip-chip" in English) for a connection to the terminals of the antenna conductor circuit.

The above methods have the following disadvantage of requiring a low tolerance to the positioning of the connection means, in practice, of the order of a few tens of microns. Indeed, in RFID applications in particular and, more particularly, in RFID applications operating at Ultra High Frequency (UHF), in practice from 400 MHz, the dimensions of the integrated circuit, like those of the contact terminals of the circuit. antenna, are very small, a few hundred microns. The surface of the contact pads of this circuit is even smaller, since it is generally in a square shape of less than 100 μm side. Due to this low positioning tolerance, production rates are reduced. Also, the aforementioned methods known from the prior art are not suitable for mass production of non-contact objects at low costs.

That's why a new method has been devised. This method is disclosed in the patent document published under the number FR-2894714-A1. In this method, the dimensions of the contact pads of the integrated circuit are considerably increased and the connection between said contact pads and the contact terminals of the antenna is made, not by ohmic contact, but by capacitive coupling. The tolerance to the positioning of the circuit for the connection to the terminals of the antenna circuit is then substantially improved.

Nevertheless, the latter method has different disadvantages.

First, the realization of said contact pads requires derogations from the design rules of the integrated circuits, which must be obtained from the founders in order to allow a modification of the dimensions of the contact pads. Indeed, these drawing rules impose global density limits of metal in the integrated circuit and local, at each metallization layer of said circuits. By considerably increasing the dimensions of the contact pads of the last metallization layer of the circuit, these rules are no longer respected, not only locally, but also, and sometimes, globally. In addition, the almost exclusive use of the last metal layer of the integrated circuit for the wide contact pads imposes a different positioning of the interconnections normally present on the latter layer and therefore a new drawing, different masks. Finally, this last layer can not be exploited anymore. It is no longer possible to simply include blocks of intellectual property ("IP blocks" in English) using connections on the last metal layer. Finally, given the large dimensions of the contact pads, parasitic capacitances are generated in the integrated circuit, which are likely to cause faulty behavior of this circuit. This is not acceptable.

With regard to the design rules of integrated circuits. Note that there is a number minimum of contact areas for said drawing rules to be respected. However, in the aforementioned patent FR-2894714-A1, the contact plates do not constitute connection pads. A new derogation from the drawing rules is therefore necessary. Finally, in this patent, the integrated circuit must be drawn with these connection plates making it unsuitable for any other mode of packaging. The object disclosed in this prior patent is therefore not compatible with all the integrated circuits.

In view of the foregoing, an objective technical problem to be solved by the invention is to realize, at lower cost, a portable object comprising an integrated circuit, as well as a method of manufacturing this portable object, which overcomes the The above-mentioned drawback of the state of the art, which, in particular, is compatible with all the integrated circuits produced, does not require derogation from the design rules of the integrated circuits, allows the positioning of IP blocks freely using the Last metal layer and limits the existence of parasitic capacitances in the circuit, and this, while having an important positioning tolerance, for mass production of non-contact objects at low costs, with high production rates.

The solution of the invention to this problem has as its first object a contactless portable object comprising, on the one hand, an integrated circuit comprising, on its active face, a first dielectric layer forming a passivation layer and flush contact pads through openings of said passivation layer, and, on the other hand, terminals of an antenna circuit (11) carried by a support (12), characterized in that said circuit further comprises connected to said terminals of the antenna circuit by capacitive coupling, these connecting plates being positioned on the surface of the passivation layer and electrically connected to the contact pads.

Its second object is an integrated circuit for manufacturing a portable object without contact as above.

Its third object is a method of manufacturing a non-contact object as above, characterized in that it comprises the following steps according to which: there are provided wafers of integrated circuits (wafers in English language) carrying a layer passivation provided with openings to which contact pads are flush; positioning plates are positioned on the surface of the passivation layer, so that said plates are electrically connected to the contact pads; and positioning the integrated circuits on supports carrying an antenna circuit so that the connection plates are arranged opposite terminals of said antenna circuit.

Thus, contrary to the teaching of the state of the art contained in the aforementioned patent document FR-2894714-A1, the contact plates, which perform the capacitive coupling, are positioned on the surface of the passivation layer. It is therefore not necessary to modify the design drawings of the integrated circuits. A post-processing of the integrated circuits is enough. The costs of manufacturing non-contact objects are considerably reduced. The parasitic capacitances due to the presence of the plates are limited because the passivation layer moves said plates away from the different connections of the internal electronic functions of the integrated circuit. The same goes for the reproducibility of the parasites due to variations in circuit mounting on its support.

The invention will be better understood on reading the description which follows, and with reference to the appended drawings, in which: FIG. 1 shows, in perspective, an integrated circuit according to the invention; Figure 2 shows, in cross section, a portion of an integrated circuit according to the invention carrying connecting plates; Figure 3 shows, in cross section, a portion of a non-contact object according to the invention; and Figure 4 illustrates, in perspective, the positional tolerance of the integrated circuit according to the invention; FIGS. 5A and 5B illustrate, in top view, the extreme tolerated variations that may occur in the assembly of an integrated circuit at the terminals of an antenna circuit according to the prior art; FIGS. 6A and 6B illustrate, always in top view, these same variations, in the case of the invention; and FIGS. 7A and 7B compare the zones at the origin of the variations of interference of mounting, in the case of the prior art and in the case of the invention, respectively.

The integrated circuit 1 presented in FIGS. 1 and 2 is in the form of a rectangular parallelepiped of more or less a hundred microns thick, and a few hundred microns wide and long, for example 900 μm long. and 600 μva wide. This circuit 1 comprises a silicon substrate 2 composed of a superposition of layers, for example of the number 10, each layer comprising integrated circuits 3, the circuits of two superposed layers being interconnected. by means of vias 4. The last metal layer of the integrated circuit according to the invention, which defines its active face, has 2 contact pads 4 or more, for example 3, 4,

6 or 8. These ranges 4 have, in one example, a surface of the order of 80 μm x 80 μm, much smaller than the surface of the integrated circuit 1. The last metal layer is covered with a layer of dielectric: the Passivation layer 6. This passivation layer 6, for example made of insulating silicon, has a substantially constant thickness of between 1 and 7 μm, for example of the order of 3 μm on average. It has openings

7 located opposite the contact pads 5, so as to allow access to said pads 5 for connection. The contact pads 5 are flush through these openings 7.

According to the invention, the integrated circuit 1 further comprises connection plates 8. These plates 8 are positioned on the surface of the passivation layer 6. They are electrically connected to the contact pads 5 of the integrated circuit, through the openings

7. The dimensions of the connecting plates 8 are much greater than those of the contact pads 5, at least as regards the width and the length of these plates

8. For example, for an integrated circuit whose dimensions of the active face, advantageously rectangular, are 900 μm and long and 600 μm wide, and which respects a preferred length / width ratio greater than or equal to 1.25, the dimensions of each connection plate are 200 μm x 500 μm. Due to this difference in size, the positioning constraints as well as the orientation constraints of the integrated circuits are released during the packaging operation of the non-contact objects incorporating the integrated circuits. In practice, when the integrated circuit comprises 2 connection plates 8, the surface of each plate is of the order of one third of the total surface of the integrated circuit. The thickness of the plates 8 is relatively small, of the order of a few microns, for example 6 microns.

The optimum distance between the plates is between 100 μm and 300 μm. In the above example, the plates are spaced about 250 microns.

In practice, the surface of the plates is advantageously chosen so as to optimize the constraints and manufacturing costs of the non-contact objects and, in particular, the antenna circuit of said objects. Indeed, the capacitance values formed by the plates and the antenna terminals are directly proportional to the surface of said plates. As a result, it is possible to modify said capacitance values in order to optimize the antenna circuit. Note further that it is possible to modify the impedance presented to the antenna by playing only on the dimensions of said plates. This is a substantial advantage over the prior art. Indeed, according to the prior art, the impedance presented to the antenna could be modified only by taking up, at least partially, the internal structure of the integrated circuit. Such a recovery requires significant developments, and a considerable time, for example of the order of 12 months.

The connection plates 8 are at least partly covered with a dielectric layer 9 formed, as is the passivation layer, of silicon. Advantageously, this layer 9 completely covers the plates 8 and the passivation layer 6. This provides better protection against electrostatic shock (ESD), which is the cause of many failures of integrated circuits. The thickness of this dielectric layer 9 is substantially constant, in one example, of the order of 10 microns.

The invention applies preferentially to UHF RFID circuits of frequencies greater than 400 MHz, in particular 433 MHz, from 800 to 900 MHz and beyond GHz, the active face of which have an area of approximately 0.5 mm ² , for example 625 μm x 800 μm. In order to make a capacity connection according to the invention, the addition of an additional interface for the capacitive connection can only justify this for connection plates whose surface (length x width) is at least four times greater than the surface (length x width) of the original contact pads, ie at least 200 μm x 200 μm. On the other hand, in order to maintain the positioning flexibility due to the mechanical tolerances released for mounting, it must be considered that, in the case of two contact plates, each of the plates can cover a maximum of only two fifths of the active face. of the integrated circuit, in our case, 250 microns x 800 microns. With an average thickness of the insulating layer of 3 μm for a relative permittivity of 4, and a reference permittivity (for vacuum Epsilon ⁰ = 8.85, 10 ¹² F / m), this makes it possible to achieve a nominal capacity per plate connection of the order of 500 fF to 2.4 pF.

It will be noted that by adding, in an equivalent electrical circuit, a capacitance in series such as that which is constituted by the connection plates above, then it is possible to realize antennas with or without a short test circuit ( DC current). As a result, the rules for drawing and optimizing antennas are relaxed.

The portable non-contact objects according to the invention are standardized objects whose format can be any. They are for example in card format, or then, in smaller formats, and then constitute RFID tags. In some cases, the format of the non-contact objects of the invention is greater than that of a card. This is the case, for example, of so-called electronic portfolios. The RFID objects more particularly targeted in the present invention are RFID-UHF objects meeting EPC Class 1 Gen II or ISO 18000-6C standards.

As is more particularly shown in FIG. 3, these portable objects 10 comprise an integrated circuit 1 as described above, as well as a second circuit: the antenna-forming conductive circuit 11. The antenna forming circuit 11 is for example printed on the surface of a dielectric support 12 of the object, in particular by screen printing, flexography or gravure, offset or ink jet. The conductive ink used is preferably a polymer ink loaded with conducting elements such as silver, copper or carbon. In another example, the antenna circuit 11 is constituted by a stamped metal strip laminated to the surface of the support 12 or a wound wire. The support 12 is for example a support of flexible material. It will be paper or plastic. In another example, the support 12 is a support made of rigid material. It will be hard plastic or resin. The antenna circuit 11 defines a track on its support 12 whose end ends constitute connection terminals 13 intended to be connected to the connection plates 8 of the integrated circuit, by capacitive coupling.

Indeed, in the non-contact portable objects 10 according to the invention, the connection between the connection plates 8 of the integrated circuit 1 and the antenna connection terminals 13 is a capacitive connection, the capacitor being formed between said plates 8 and said terminals 13 of the antenna circuit, separated by the dielectric layer 9.

As shown in FIG. 4, the coupling capacitor (s) are made by facing the plates (8) and the terminals (13).

From the moment when there is an internal link capacity in the integrated circuit 1, a new optimization of the assembly is obtained thanks to an even greater positioning tolerance. Indeed, in the case where the coupling capacity has a value greater than the internal capacitance of the integrated circuit 1, it is necessary to choose, for obvious production reasons, a positioning accepting an error of plus or minus 20% of the plates 8 Thanks to the invention, the positioning of the integrated circuit 1 on the support 12 carrying the antenna circuit 11 accepts a certain tolerance. Indeed, two capacitors C1 and C2, arranged in series in a circuit, are equivalent to a capacitance CE = (Cl x C2) / (C1 + C2). If the capacitance C2 is greater than C1, which is the case in the assembly of the invention, then the equivalent capacitance CE tends to a value equal to C1. In other words, when two capacitors of different values are arranged in series, the value of the capacitance of the circuit thus formed is close to the value of the capacitance of lower value in this circuit. For example, if the coupling capacitance C2 is equal to 5 times the internal capacitance C1, then the equivalent capacitance CE is equal to 5/6 x Cl. In the case where C2 increases by 20%, ie C2 = 6 x Cl, then CE = 6/7 x Cl which gives a CE dispersion of 2.8%. Similarly, if this C2 capacity loses 20% and goes to four times Cl, then CE = 4/5 and we have a dispersion of 4%. In other words, 20% error in the nominal value of the coupling capacitor due to a positioning error of 20% of the conductive surfaces arranged facing each other only causes a variation in circuit capacity of a few percent. The positioning tolerance is further increased according to the invention. It will be further noted that the aforementioned values of 2.8% and 4% correspond to acceptable dispersions in the semiconductor industry.

Moreover, and as is illustrated in FIGS. 5A, 5B, 6A, 6B, 7A and 7B, the connecting plates 8 constitute a shield ("shield", in Anglo-Saxon language), which ensure good reproducibility of the parasites. mounting. Indeed, according to the prior art, the integrated circuit can be mounted with a shift to the right (Figure 5A) or left (Figure 5B). Noise is not reproduced in the same way, depending on the editing offsets. The zone Sl of variation of the parasites in the case of an assembly according to the prior art is shown in FIG. 7A. This area is important and the operation of the portable object must therefore withstand significant delays in the reproducibility of parasites, in a mounting according to the prior art. On the other hand, as regards the invention, this zone S2, which is represented in FIG. 7B, is limited. Indeed, and as is shown in Figure 6A and 6B ₇ the lack of conductive zones, during mounting offset to the right (Figure 6B) or to the left (Figure 6A), are limited surface. A good reproducibility of mounting parasites is thus provided, according to the invention.

Of course, the performances of the non-contact objects according to the invention are improved, given that the plates are positioned not in the last metal layer of the integrated circuit, but on the upper surface of the passivation layer. As a result, the plates are remote from the internal circuits of the integrated circuit. The effect is immediate: The reduction of parasitic capacitances is at the origin of improved performances of the functions working with signals which can be capacitively coupled with the plates.

Note that, in other embodiments of the invention, the support is a connection ("strap" in English), for example described in the JEDEC-MO283 standard, provided with antenna terminals and intended for to be incorporated in a second support, this second support comprising an antenna circuit. In still other variants, the antenna circuit is a looped circuit, that is to say a circuit provided with a closed loop, for example intended for a near field communication ("Near Field Communication", in English language) . The presence of capacitors at the terminals of the antenna circuit allows the possibility of implementing such looped circuits, in particular for circuits which are not compatible a priori with such a closed antenna loop.

For the manufacture of integrated circuits according to the invention, it is carried out in a conventional manner, by producing masks defining the circuits and used for the production of wafers ("wafers" in English) using the photolithography technique. Wafers have several tens of thousands of integrated circuits. As has been indicated previously, contrary to the state of the art disclosed in patent document FR-2894714-A1, it is not necessary, for the manufacture of the integrated circuits according to the invention, to modify the drawings of the integrated circuits carried by the wafers and, in particular, the drawings relating to the last metal layer of the integrated circuits carrying the contact pads. Indeed, this layer remains intact. The same goes for the passivation layer and the openings are practiced there. It is thus possible to include all IP blocks, without any restriction of drawing. The semiconductor process is standard. The wafers delivered by the smelters to RFID cardholders or manufacturers of objects are thus unchanged. Unlike the aforementioned patent, there is no additional cost associated with the production of wafers.

On the other hand, for the realization of the integrated circuits according to the invention, the wafers must undergo a post-treatment.

This post-processing comprises the following steps according to which connection plates are positioned on the surface of the passivation layer of the integrated circuits of the wafers. These contact plates are for example screen printed on the surface of the passivation layer. They comprise a first part, located in the openings and a second part on the passivation layer.

It further comprises a step according to which the connection plates are covered, at least partially, with a dielectric layer.

Once wafer prepared and then refined back ("back grinding" in English). At the end of this step, their thickness is reduced to about 100 microns against about 600 microns at the origin for a simpler integration. Then, the integrated circuits are cut (sawing step) and the entire wafer is positioned on a particular adhesive plastic ("blue tape" in English), as usually practiced in the semiconductor industry. Then, the integrated circuits are positioned one by one on the supports of the antenna circuit. The plates of the integrated circuit are placed opposite the terminals of the antenna circuit. Adhesive material may be deposited between the connection terminals of the antenna circuit prior to placement of the integrated circuit on the carrier. A once the adhesive material deposited, the circuit is positioned on the support so that the metal plates of the chip are facing the connection terminals of the antenna circuit. Under the effect of the pressure exerted, the adhesive spreads and covers the entire surface of the chip, between the connection terminals of the antenna circuit. A capacitive connection is thus made between each metal plate and each corresponding connection terminal. The value of the capacitance obtained is proportional to the surface of the plates opposite and to the value of the permittivity of the insulating layer which separates them, and is inversely proportional to the thickness of this insulating layer.

Thanks to the invention, there is no longer an arm's length relationship between the integrated circuit suppliers and the contactless object manufacturers. The production costs of non-contact objects are considerably reduced.

Claims

A non-contact portable object (10) comprising, on the one hand, an integrated circuit (1) having, on its active side, a first passivation layer (6) and contact pads (5) flush with the through openings (7) of said passivation layer, and, secondly, terminals of an antenna circuit carried by a support (12), characterized in that said circuit further comprises connection plates (8) connected to said terminals (13) of the circuit by capacitive coupling, these connection plates (8) being positioned on the surface of the passivation layer (6) and electrically connected to the contact pads (5).

2. Object according to claim 1, characterized in that the connecting plates (8) are covered with a second dielectric layer (9) of said integrated circuit (1).

3. Object according to one of claims 1 or 2, characterized in that the length and width of the connecting plates (8) is greater than the length and width of the contact pads (5).

4. Object according to one of claims 1, 2 or 3, characterized in that the surface of the connecting plates (8) is at least four times greater than the surface of the contact pads (5).

5. Object according to one of the preceding claims, characterized in that each plate covers a maximum of two fifths of the active face of the integrated circuit (1).

6. Object according to one of the preceding claims, characterized in that the surface of the integrated circuit is rectangular and has a length to width ratio greater than 1.25.

7. Object according to one of the preceding claims, characterized in that the passivation layer (6) is of substantially constant thickness, between 1 and 7 microns.

8. Object according to one of the preceding claims, characterized in that it is an RFID object.

9. Object according to claim 8, characterized in that it is a UHF RFID object.

10. Object according to one of claims 2 to 9, characterized in that the thickness of the dielectric layer (9) is substantially constant.

11. Object according to one of the preceding claims, with near field communication.

12. Integrated circuit (1) for manufacturing a portable non-contact object (10) according to one of the preceding claims.

13. A method of manufacturing a portable non-contact object (10) according to one of claims 1 to 11, characterized in that it comprises the following steps according to which: there are provided wafers of integrated circuits (1) carrying a passivation layer (6) provided with openings to which contact pads are flush

(5); connecting plates (8) are positioned on the surface of the passivation layer (6), so that said plates (8) are electrically connected to the contact pads (5); and positioning the integrated circuits (1) on supports (12) carrying an antenna circuit (11) so that the connecting plates (8) are arranged facing terminals (13) of said antenna circuit.