EP2208078A4 - IMPROVING THE SIMULATION SPEED OF IC DESIGN DURING CHECKING SCAN CIRCUITS - Google Patents

IMPROVING THE SIMULATION SPEED OF IC DESIGN DURING CHECKING SCAN CIRCUITS

Info

Publication number
EP2208078A4
EP2208078A4 EP08782101A EP08782101A EP2208078A4 EP 2208078 A4 EP2208078 A4 EP 2208078A4 EP 08782101 A EP08782101 A EP 08782101A EP 08782101 A EP08782101 A EP 08782101A EP 2208078 A4 EP2208078 A4 EP 2208078A4
Authority
EP
European Patent Office
Prior art keywords
simulation
design
scan circuitry
testing scan
enhancing speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08782101A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP2208078A1 (en
Inventor
Yogesh Pandey
Vijay Sankar
Manish Jain
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Synopsys Inc
Original Assignee
Synopsys Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Synopsys Inc filed Critical Synopsys Inc
Publication of EP2208078A1 publication Critical patent/EP2208078A1/en
Publication of EP2208078A4 publication Critical patent/EP2208078A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G01R31/318591—Tools

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
EP08782101A 2007-10-17 2008-07-18 IMPROVING THE SIMULATION SPEED OF IC DESIGN DURING CHECKING SCAN CIRCUITS Withdrawn EP2208078A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/873,800 US7925940B2 (en) 2007-10-17 2007-10-17 Enhancing speed of simulation of an IC design while testing scan circuitry
PCT/US2008/070563 WO2009051871A1 (en) 2007-10-17 2008-07-18 Enhancing speed of simulation of an ic design while testing scan circuitry

Publications (2)

Publication Number Publication Date
EP2208078A1 EP2208078A1 (en) 2010-07-21
EP2208078A4 true EP2208078A4 (en) 2013-03-20

Family

ID=40564711

Family Applications (1)

Application Number Title Priority Date Filing Date
EP08782101A Withdrawn EP2208078A4 (en) 2007-10-17 2008-07-18 IMPROVING THE SIMULATION SPEED OF IC DESIGN DURING CHECKING SCAN CIRCUITS

Country Status (6)

Country Link
US (1) US7925940B2 (ja)
EP (1) EP2208078A4 (ja)
JP (1) JP5263904B2 (ja)
CN (1) CN101828120B (ja)
TW (1) TWI457777B (ja)
WO (1) WO2009051871A1 (ja)

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TWI425795B (zh) * 2010-07-29 2014-02-01 Univ Nat Chiao Tung 追蹤網路封包之處理程序的方法
US8589835B2 (en) 2012-01-17 2013-11-19 Atrenta, Inc. System and method for inferring higher level descriptions from RTL topology based on naming similarities and dependency
US8656335B2 (en) 2012-04-27 2014-02-18 Atrenta, Inc. System and methods for inferring higher level descriptions from RTL topology based on connectivity propagation
US8782587B2 (en) 2012-07-30 2014-07-15 Atrenta, Inc. Systems and methods for generating a higher level description of a circuit design based on connectivity strengths
TWI477794B (zh) 2012-10-02 2015-03-21 Realtek Semiconductor Corp 積體電路掃描時脈域分配方法以及相關機器可讀媒體
US9274171B1 (en) 2014-11-12 2016-03-01 International Business Machines Corporation Customer-transparent logic redundancy for improved yield
EP3435545B1 (en) * 2015-10-15 2023-06-07 Menta System and method for testing and configuration of an fpga
TWI670617B (zh) * 2018-10-31 2019-09-01 財團法人工業技術研究院 模擬系統與方法
US11231462B1 (en) * 2019-06-28 2022-01-25 Synopsys, Inc. Augmenting an integrated circuit (IC) design simulation model to improve performance during verification
WO2022043675A2 (en) 2020-08-24 2022-03-03 Unlikely Artificial Intelligence Limited A computer implemented method for the automated analysis or use of data
US11977854B2 (en) 2021-08-24 2024-05-07 Unlikely Artificial Intelligence Limited Computer implemented methods for the automated analysis or use of data, including use of a large language model
US11989527B2 (en) 2021-08-24 2024-05-21 Unlikely Artificial Intelligence Limited Computer implemented methods for the automated analysis or use of data, including use of a large language model
US11989507B2 (en) 2021-08-24 2024-05-21 Unlikely Artificial Intelligence Limited Computer implemented methods for the automated analysis or use of data, including use of a large language model
US12067362B2 (en) 2021-08-24 2024-08-20 Unlikely Artificial Intelligence Limited Computer implemented methods for the automated analysis or use of data, including use of a large language model
US12073180B2 (en) 2021-08-24 2024-08-27 Unlikely Artificial Intelligence Limited Computer implemented methods for the automated analysis or use of data, including use of a large language model
CN114253862B (zh) * 2021-12-29 2024-10-01 湖南泛联新安信息科技有限公司 一种hdl代码仿真覆盖率异步事件驱动自动分析方法
CN114546596B (zh) * 2022-02-23 2024-11-01 安天科技集团股份有限公司 指令集仿真方法、装置、计算机设备
CN117907812B (zh) * 2024-03-20 2024-06-25 英诺达(成都)电子科技有限公司 电路检测方法及装置、电子设备、存储介质、程序产品

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6205567B1 (en) * 1997-07-24 2001-03-20 Fujitsu Limited Fault simulation method and apparatus, and storage medium storing fault simulation program
US20040205681A1 (en) * 2003-01-16 2004-10-14 Yasuyuki Nozuyama Calculation system of fault coverage and calculation method of the same

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JP3064552B2 (ja) * 1991-09-18 2000-07-12 日本電気株式会社 演算制御シミュレーション方式
JPH0926981A (ja) * 1995-07-11 1997-01-28 Fujitsu Ltd 回路の故障シミュレーション方法および故障シミュレーション装置
US5854752A (en) * 1996-01-19 1998-12-29 Ikos Systems, Inc. Circuit partitioning technique for use with multiplexed inter-connections
US6046984A (en) * 1997-04-11 2000-04-04 Digital Equipment Corp. Pruning of short paths in static timing verifier
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
JPH1115860A (ja) * 1997-06-20 1999-01-22 Toshiba Microelectron Corp 論理シミュレーション方法、論理シミュレーション装置及び論理シミュレーションプログラムを格納したコンピュータ読み取り可能な記録媒体
US6134689A (en) * 1998-02-12 2000-10-17 Motorola Inc. Method of testing logic devices
DE19917884C1 (de) * 1999-04-20 2000-11-16 Siemens Ag Schaltung mit eingebautem Selbsttest
JP3555071B2 (ja) * 1999-07-06 2004-08-18 Ｎｅｃエレクトロニクス株式会社 故障伝搬経路推定方法、故障伝搬経路推定装置及び記録媒体
US6895372B1 (en) 1999-09-27 2005-05-17 International Business Machines Corporation System and method for VLSI visualization
JP3614811B2 (ja) * 2001-02-15 2005-01-26 Ｎｅｃエレクトロニクス株式会社 組合せ論理回路における故障伝搬経路推定システム及び方法並びにプログラム
US6957403B2 (en) 2001-03-30 2005-10-18 Syntest Technologies, Inc. Computer-aided design system to automate scan synthesis at register-transfer level
US7363099B2 (en) * 2002-06-07 2008-04-22 Cadence Design Systems, Inc. Integrated circuit metrology
US6993736B2 (en) 2003-12-10 2006-01-31 Texas Instruments Incorporated Pending bug monitors for efficient processor development and debug
DE602005018204D1 (de) * 2004-05-22 2010-01-21 Advantest Corp Verfahren und struktur zur entwicklung eines testprogramms für integrierte halbleiterschaltungen
US7437698B2 (en) * 2005-11-30 2008-10-14 Freescale Semiconductor, Inc. Method and program product for protecting information in EDA tool design views
JP5073638B2 (ja) * 2008-11-17 2012-11-14 本田技研工業株式会社 車体側部構造

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6205567B1 (en) * 1997-07-24 2001-03-20 Fujitsu Limited Fault simulation method and apparatus, and storage medium storing fault simulation program
US20040205681A1 (en) * 2003-01-16 2004-10-14 Yasuyuki Nozuyama Calculation system of fault coverage and calculation method of the same

Also Published As

Publication number Publication date
CN101828120A (zh) 2010-09-08
TWI457777B (zh) 2014-10-21
WO2009051871A1 (en) 2009-04-23
US20090106612A1 (en) 2009-04-23
US7925940B2 (en) 2011-04-12
JP2011501290A (ja) 2011-01-06
EP2208078A1 (en) 2010-07-21
JP5263904B2 (ja) 2013-08-14
TW200919246A (en) 2009-05-01
CN101828120B (zh) 2013-01-30

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