Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/26—Systems using multi-frequency codes
  • H04L27/2601—Multicarrier modulation systems
  • H04L27/2647—Arrangements specific to the receiver only
  • H04L27/2655—Synchronisation arrangements
  • H04L27/2689—Link with other circuits, i.e. special connections between synchronisation arrangements and other circuits for achieving synchronisation
  • H04L27/2695—Link with other circuits, i.e. special connections between synchronisation arrangements and other circuits for achieving synchronisation with channel estimation, e.g. determination of delay spread, derivative or peak tracking
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/26—Systems using multi-frequency codes
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03G—CONTROL OF AMPLIFICATION
  • H03G3/00—Gain control in amplifiers or frequency changers
  • H03G3/20—Automatic control
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03G—CONTROL OF AMPLIFICATION
  • H03G3/00—Gain control in amplifiers or frequency changers
  • H03G3/20—Automatic control
  • H03G3/30—Automatic control in amplifiers having semiconductor devices
  • H03G3/3089—Control of digital or coded signals
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
  • H04L25/0202—Channel estimation
  • H04L25/0224—Channel estimation using sounding signals
  • H04L25/0228—Channel estimation using sounding signals with direct estimation from sounding signals
  • H04L25/023—Channel estimation using sounding signals with direct estimation from sounding signals with extension to other symbols
  • H04L25/0232—Channel estimation using sounding signals with direct estimation from sounding signals with extension to other symbols by interpolation between sounding signals
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/26—Systems using multi-frequency codes
  • H04L27/2601—Multicarrier modulation systems
  • H04L27/2647—Arrangements specific to the receiver only
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/26—Systems using multi-frequency codes
  • H04L27/2601—Multicarrier modulation systems
  • H04L27/2647—Arrangements specific to the receiver only
  • H04L27/2655—Synchronisation arrangements
  • H04L27/2662—Symbol synchronisation
  • H04L27/2665—Fine synchronisation, e.g. by positioning the FFT window
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L5/00—Arrangements affording multiple use of the transmission path
  • H04L5/003—Arrangements for allocating sub-channels of the transmission path
  • H04L5/0048—Allocation of pilot signals, i.e. of signals known to the receiver
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L5/00—Arrangements affording multiple use of the transmission path
  • H04L5/0001—Arrangements for dividing the transmission path
  • H04L5/0003—Two-dimensional division
  • H04L5/0005—Time-frequency
  • H04L5/0007—Time-frequency the frequencies being orthogonal, e.g. OFDM(A), DMT

Definitions

• the present disclosure relates to timing adjustments for channel estimation in a multi carrier wireless system, and, more particularly, to adjusting timing by ensuring pilot tone interlaces have matching time bases, which also match a symbol time basis.
• Orthogonal frequency division multiplexing is a method of digital modulation in which a signal is split into several narrowband channels at different carrier frequencies orthogonal to one another. These channels are sometimes called subbands or subcarriers.
• OFDM is similar to conventional frequency- division multiplexing (FDM) except in the way in which the signals are modulated and demodulated.
• FDM frequency- division multiplexing
• One advantage of OFDM technology is that it reduces the amount of interference or crosstalk among channels and symbols in signal transmissions. Time- variant and frequency selective fading channels, however, present problems in many OFDM systems.
• pilot symbols also referred to simply as “pilots” embedded in the data of each OFDM symbol may be used for channel estimation.
• Time and frequency tracking may be achieved using the pilots in channel estimation.
• each OFDM symbol consists of N number of subcarriers and P number of pilots
• an N-P number of the subcarriers can be used for data transmission and P number of them can be assigned to pilot tones.
• P number of pilots are sometimes uniformly spread over the N subcarriers, so that each two pilot tones are separated by N/P-l data subcarriers (or, in other words, each pilot occurs every N/P* carrier).
• Such uniform subsets of subcarriers within an OFDM symbol and over a number of symbols occurring in time are called interlaces.
• OFDM has also been used in Europe and Japan, as examples, for digital broadcast services, such as with the Digital Video Broadcast (DVB-T/H (terrestrial/handheld)) and Integrated Service Digital Broadcast (ISDB-T) standards.
• DVD-T/H Digital Video Broadcast
• ISDB-T Integrated Service Digital Broadcast
• channel characteristics in terms of the number of channel taps i.e., the number of samples or "length" of a Finite Impulse Response (FIR) filter that is used to represent the channel of a received signal
• FIR Finite Impulse Response
• a receiver responds to changes in the channel profile by selecting the OFDM symbol boundary appropriately (i.e., correction of window timing) to maximize the energy captured in a fast Fourier transform (FFT) window.
• FFT fast Fourier transform
• the channel estimation algorithm takes the timing corrections into account while computing the channel estimate to be used for demodulating a given OFDM symbol.
• the channel estimate is also used to determine timing adjustment to the symbol boundary that needs to be applied to future symbols, thus resulting in a subtle interplay between timing corrections that have already been introduced and the timing corrections that will be determined for the future symbols.
• a channel estimation block in a receiver it is common for a channel estimation block in a receiver to buffer and then process pilot observations from multiple OFDM symbols, which results in a channel estimate that has better noise averaging and resolves longer channel delay spreads. This is achieved by combining the channel observations from consecutively timed OFDM symbols into a longer channel estimate in a unit called the time filtering unit. Longer channel estimates in general may lead to more robust timing synchronization algorithms.
• pilot observations from multiple OFDM symbols are processed together to generate a channel estimate, however, if the interlaces combined and the OFDM symbols to be demodulated are not aligned with respect to the symbol timing (i.e., have the same time- basis), the channel estimation may become degraded to the point that it cannot be used for successful symbol demodulation.
• a method for timing correction in a communication system includes adjusting time bases of one or more pilot interlaces and combining the one or more pilot interlaces.
• the method further includes matching the time basis of the combined pilot interlaces with a symbol to be demodulated, and then obtaining a corrected channel estimate based on combined pilot interlaces having a time basis matching the symbol.
• a processor for use in a wireless transceiver is disclosed.
• the processor is configured to adjust time bases of one or more pilot interlaces and combine the one or more pilot interlaces.
• the processor also matches the time basis of the combined pilot interlaces with a symbol to be demodulated, and obtains a corrected channel estimate based on combined pilot interlaces having a time basis matching the symbol.
• a transceiver for use in a wireless system is disclosed.
• the transceiver includes a channel estimation unit configured to adjust time bases of one or more pilot interlaces and combine the one or more pilot interlaces, match the time basis of the combined pilot interlaces with a symbol to be demodulated, and obtain a corrected channel estimate based on combined pilot interlaces having a time basis matching the symbol.
• the transceiver also includes a timing tracking unit configured to set timing of a discrete Fourier transform unit based on the corrected channel estimate.
• an apparatus for use in a wireless transceiver includes means for adjusting time bases of one or more pilot interlaces to a common time base and combining the one or more pilot interlaces, means for aligning the time basis of the combined pilot interlaces with a symbol to be demodulated, and means for obtaining a corrected channel estimate based on combined pilot interlaces having a time basis matching the symbol.
• a computer program product comprises a computer-readable medium having a code for adjusting time bases of one or more pilot interlaces and combining the one or more pilot interlaces.
• the computer-readable medium also includes code for instruction for matching the time basis of the combined pilot interlaces with a symbol to be demodulated, and code for obtaining a corrected channel estimate based on combined pilot interlaces having a time basis matching the symbol.
• FIG. 1 illustrates a block diagram of an exemplary transceiver according to the present disclosure.
• FIG. 2 is a diagram of an exemplary pilot tone staggering scheme used in particular OFDM standards.
• FIG. 3 is a diagram of a visualization of combining pilot tone of the exemplary pilot tone staggering scheme of FIG. 2.
• FIG. 4 illustrates a time-domain channel estimate split into four segments according to an exemplary method for combining interlaces.
• FIG. 5 illustrates an exemplary conceptual signal processing view of generating interlaces.
• FIG. 6 illustrates FFT timing windows for three different timing occurrences in a transceiver.
• FIG. 7 illustrates an arrangement of carriers and mapping of those carriers for
• FIG. 8 illustrates a method for performing timing corrections in a wireless device.
• FIG. 9 illustrates another apparatus for performing timing corrections in a wireless device.
• FIG. 10 illustrates a visualization of performing timing updates in a wireless communication system.
• the present disclosure discusses apparatus and method for determining timing adjustments for channel estimation and timing tracking in a multi carrier system.
• FIG. 1 illustrates a block diagram of an exemplary OFDM transceiver or portion of a transceiver according to the present disclosure.
• the system of FIG. 1 may employ the disclosed techniques for making timing adjustments using pilot tones, which are used for channel estimation.
• the system 100 which may be a transceiver or one or more processors, hardware, firmware, or a combination thereof, receives a transmitted RF signal as shown.
• a front end processing block 102 receives the RF signal and performs various processing functions including analog-to-digital conversion, down conversion, and AGC (Automatic Gain Control).
• the resultant signals are sent to s sample server 104, which effects the actual timing window (e.g., the FFT timing window) for sampling the subcarriers within the signal.
• the output of the sample server 106 which is a synchronized digital signal, then is input to an optional frequency rotator 106.
• the optional frequency rotator 106 operates in conjunction with and under control of a frequency tracking block 108 to cause rotation or shifting of the phase of the signal in frequency in order to make fine adjustments or corrections in frequency.
• the signals from either sample server 104 or frequency rotator 106, if utilized, are sent to a fast Fourier Transform (FFT) 110, which performs a discrete Fourier transform of the signal. More particularly, the FFT 110 extracts the data carriers and the pilot carriers.
• the data is sent to a demodulator 112 for demodulation of the data, and a subsequent decoder 114 for decoding of the data according to any suitable encoding scheme utilized.
• the output of the decoder is a bit steam for use by other processors, software, or firmware within a transceiver device.
• the pilot tones extracted by FFT 110 are sent to a pilot buffer 116, which buffers a number of pilot interlaces from one or more OFDM symbols.
• the buffer 116 may be configured to buffer seven (7) pilot interlaces for use in combining the interlaces for DVB-T/H or ISDB-T systems, which will be discussed in further detail later.
• the buffered pilot interlaces are delivered by buffer 116 to a channel estimation unit or block 118, which estimates the channels using the interlaced pilot tones inserted by the transmitter (not shown) into the symbols of the digital signal.
• the channel estimation yields a channel impulse response (CIR) h k n to be used in timing tracking and a channel frequency
• channel impulse response (CIR) h k n is delivered to a timing tracking unit or block 120, which effects a timing tracking algorithm or method to determine a timing decision for the FFT window that is used by sample server 104.
• a channel estimation unit e.g., 118
• H k n the channel transfer function estimate of the channel at each carrier k and OFDM symbol time n for demodulation of the data symbols and an estimate h k n of the corresponding channel impulse response (CIR) for use in time tracking.
• the pilot tones are transmitted according a predetermined interlace staggering scheme 200 as illustrated by FIG. 2, which illustrates the scheme for the first few carriers k and symbol times n.
• FIG. 2 illustrates the scheme for the first few carriers k and symbol times n.
• pilot tones p are inserted at every 12 th carrier for a total of up to N ⁇ /12 pilots tones per OFDM symbol n (e.g., at symbol time 0 in FIG. 3 there can be a N ⁇ /12 number of pilot tones where carrier 0 is used for a pilot tone, but N K / 12-1 for symbols having pilots staggered such as a OFDM symbol time 1, 2, and 3 in FIG. 2), where N K is the total number of carriers.
• the pattern repeats after four OFDM symbols (e.g., OFDM symbol times 0-3). For example, FIG.
• pilot interlaces from seven (7) consecutive OFDM symbols, which are buffered in a pilot interlace buffer (not shown), in a paired fashion to find a channel estimate for a time n.
• each pair of pilot tones corresponds to the same pilot (i.e., / th pilot) at different OFDM symbol time instances and they are combined to estimate the channel corresponding to the time of data.
• FIG. 3 illustrates a diagram 300 of the exemplary interlacing of pilot symbols p shown in FIG. 2 with further visual representation of the combining of pilot tones.
• a pair 302, 304 of pilots (po,i) at carrier 3 i.e., an offset of 3 carriers (3 ⁇ n mod4), thus part of same m+1 interlace) and times n+1 and n-3, respectively, are combined to the time of symbol time n (n being 0 in this example) as indicated with vertical arrows.
• an interpolated pilot tone 306 may then be interpolated in frequency with other interpolated pilot tones 308 or a pilot tone extant in the n time OFDM symbol 210, as illustrated by the horizontal arrows in FIG. 3.
• Combining pilot tones may be effected using any known techniques including interpolation techniques. It is further noted that the interlaces may be combined in the frequency or time domain, as will be explained in detail below. From a theoretical point of view, both strategies of combining (frequency or time domain) yield the same performance. It is noted, however, that combining in time may present less stress on a channel IFFT in a fixed point implementation (since its shorter).
• a first strategy for combing pilot tones of the interlaces is combining in the frequency domain, as mentioned above, using a filter. Combining the pilot tones in the frequency domain can be mathematically expressed as shown in equation (1) below providing the pilot tone estimate H k n .
• N P is the length of the final time-domain channel estimate
• m l,[n-k] 4 are the filter coefficients of the filter
• N c and N nc are the causal and non- causal filter lengths, respectively.
• the filter coefficients Wi 1 , _ k] are chosen to effect linear interpolation between two pilot-
• a more general filter could incorporate pilot tones from other interlaces (i.e., also work diagonally), with an according increase in complexity.
• taps below a certain threshold are set to zero, and after zero-padding with 2N F zeros (to interpolate in frequency), an FFT is taken to arrive at the final channel estimate H k n , where Np is the length of the final time-domain channel estimate.
• an IFFT of the pilot tones of each interlace is taken. More specifically, zero-padding (i.e., extending a signal (or spectrum) with zeros to extend the time (or
• N K represents the number of carriers
• Nn represents the length of interlaces in frequency after zero padding.
• the number of carriers N ⁇ is 1705, 3409, or 6817 dependent on the mode of operation.
• ISDB-T segment-0 systems as a further example typically have 108, 216, or 432 carriers N K dependent on the mode of operation.
• the length of the interlaces Nn are 256 or 512 or 1024, dependent on the mode of operation.
• ISDB-T systems would have interlaces lengths of 16 or 32 or 64 dependent on the mode of operation.
• each interlace channel estimate is to be used four (4) times for the calculation of channel estimates at consecutive OFDM symbol times, the b k m are buffered, requiring 7N IL complex storage spaces for the presently disclosed examples.
• the channel estimate h k n may then be split into four segments as illustrated in FIG. 4. Each of the four u segments has a length of N IL , where each of the segments u can be obtained from the buffers as proved by the following relationship:
• the time-domain channel taps obtained here are simply the IFFT of the combined pilot tones of equation (1) above. Combining in the time domain may simply be viewed as one way of implementing a fast algorithm for the discrete Fourier transform (DFT) of the pilot tones combined in frequency. More particularly, the equivalence is derived as follows for the case that we use exactly four consecutive interlaces and all 4 filter coefficients M 1 k are one (a more general case with filtering will be considered later). Then each time interlace h k m can be viewed as being obtained from a frequency-domain channel H k n by down-sampling and advancing (in frequency). Fig 5 illustrates the down-sample and advance operation that can be thought of as generating the h k m in a conceptual signal processing view.
• DFT discrete Fourier transform
• the channel sampled at every carrier frequency is input and first down-sampled by 3 at block 502 (corresponding to a pilot every 3 tones, if all interlaces are combined), and further down-sampled by 4 (block 504) for interlace 0.
• the frequency indices are shifted by one (the F operator in block 506 signifies a forward shift) and then down-sampled by 4 as illustrated by blocks 508. Since down-sampling in frequency corresponds to aliasing in time and shifting in frequency to a phase shift in time one skilled in the art will appreciate that the following relationship in equation (5) below governs.
• N p 4 combining coefficients can be extracted from this solution.
• the additional filtering introduced with the coefficients Wi 1 k can be viewed to only operate on a given interlace, so that it is equivalent in time and frequency domain (i.e., linear operations are interchangeable). Whether the filtered interlaces are then combined in frequency or time domain is the same according to the presently disclosed methodologies. Accordingly, equation (4) above can be rewritten as the following equation (9): +HiV IL ,B m l,rK,n-(r-l A) > (9)
• the inner sum corresponds to the interlace filtering and the outer-sum corresponds to the phase deramping and interlace combining in time domain.
• Timing adjustments are necessitated due to phase shift between pilot tones at a current n OFDM symbol and previous interlaces.
• Known fine timing tracking algorithms for example, retard or advance the position of the FFT window at a sample server (to be discussed later). These timing adjustments correspond to phase shifts in the frequency-domain and thus affect channel estimation:
• the pilot tones at time n have a phase shift compared with the previous interlaces.
• channel estimation should be configured to correct for this phase shift to combine the interlace buffers.
• the advance or retarding of the FFT window may be also referred to as an advance or retard of the sampling of the OFDM symbol.
• FIG. 6 illustrates three different FFT window position scenarios for a particular string of three consecutive OFDM symbols (n-1, n, n+1).
• the first scenario indicated by reference number 600 shows timing windows 602 where the timing between windows shown by arrow 604, is essentially constant with no change from one symbol (i.e., n-1) to the next (n).
• an advance of the FFT window leads to a delay of the channel.
• the second scenario 606 in FIG. 6 illustrates that the FFT window 608 is advanced as indicated by shortened arrow 610, thus causing the samples in the window to be delayed.
• a delay of the FFT window leads to an advance of the channel as illustrated by scenario 612, where the window 614 is delayed as indicated by longer arrow 616.
• FIG. 7 illustrates an exemplary
• phase shift initially shows up in the front-end FFT, where the
• N ⁇ N. carriers of interest are located at 0... - 1 and N 1 RX FFT . . . NRX FFT - I
• N RX FFT being the size of the front-end FFT.
• front-end FFT are mapped to N.
• a consideration with timing updates and channel estimation is that the interlaces that are combined by the channel estimation algorithm need to have the same time- basis. If the interlaces that are combined do not have the same time-basis, for example, the resulting channel estimate is severely degraded, to the point that it cannot be used successfully for demodulating the data symbols.
• the time basis of the channel estimate and the OFDM symbol that is to be demodulated with the estimate need to match. Accordingly, it is has been recognized that the time-bases of the interlaces need to match, and further that the time-basis of the interlaces match the time -basis of the OFDM symbol to be demodulated. In order to effect such alignment and matching, the following subject matter addresses exemplary methodologies and apparatus for effecting this.
• adjusting or aligning the time basis of pilot interlaces may be accomplished in either time or domain.
• the following discussion relates in a concise manner how to change the time-basis of a single interlace.
• Adjusting the time-basis in frequency domain is beneficial if interlaces are combined in frequency. It may also be useful when the interlaces are combined in time- domain to know that the time-basis of an interlace needs to be changed before taking the IFFT.
• equation (10) can be rewritten as follows:
• timing update is generalized from time m to n and wherein, for example, in the cases of ISDB-T and DVB-T/H systems
• h l m is replaced with b l m e Nf and it is recognized that the b k m for « ⁇ A: ⁇ N IL -1 are simply ⁇ _ ⁇ m . Accordingly, for 0 ⁇ k ⁇ a - ⁇ , the following relationship can be obtained.
• the channel estimate obtained for time n to be used for demodulating OFDM symbol n should have the time-basis corresponding to FFT window used for obtaining Y k n , where Y k n is the receiver FFT output at a carrier k and an OFDM symbol time n. .
• the time-basis of the channel estimate for time n matches the one for Y k n .
• H k n a channel estimate that has the correct time -basis
• H k n an estimate with the incorrect time -basis.
• the first option is to correct in the frequency domain.
• the channel estimate for carrier k is multiplied by Y k n with the data carrier and the phase shift caused by the different time-bases can be corrected by the following relationship:
• a second option is to correct the channel estimate in time- domain. As discussed previously, the channel estimate H k n is obtained through an
• h k n (which in turn is just a thresholded version of h k n obtained from combining interlaces in time-domain or the IFFT of the combined interlaces in frequency domain) with zero-padding.
• the zero-padded h k n can be cyclically shifted by
• 3N a — a positions (assuming as above that or is an integer or rounded to the
• H k n can be determined by taking the FFT of the following:
• FIG. 8 illustrates a flow diagram of a method for performing timing corrections in a multi carrier OFDM system, such as DVB-T/H and ISDB-T systems.
• the process 800 begins at a start block 802.
• Flow then proceeds to block 804 where an adjustment or "alignment" of the time bases of one or more pilot interlaces to a common time base and then combining the one or more pilot interlaces.
• This adjustment may be according to the methodology discussed previously in this disclosure, including adjusting in frequency or time domains. It is further noted that this adjustment may be effected by the channel estimation block 118, for example, a digital signal processor (DSP), a combination thereof, or any other suitable means.
• DSP digital signal processor
• block 806 the time basis of the combined interlaces are aligned or matched with a time basis of the OFDM symbol that is to be demodulated. This matching may be in accordance with the methodology discussed previously herein, including correcting the channel estimate in frequency domain or in time domain. Additionally, this functionality of block 806 may be effected by, for example, the channel estimation block 118, a digital signal processor (DSP), a combination thereof, or any other suitable means.
• DSP digital signal processor
• block 807 a channel estimate (i.e., a corrected channel estimate) is obtained based on the combined pilot interlaces having a time basis matching the symbol to be.
• process 800 when viewed as a process for obtaining a corrected channel estimate, may proceed to termination block 810 where the process ends as shown in FIG. 8.
• flow may proceed from block 807 to block 808 (shown with dashed lines) where the channel estimate is provided to timing tracking to determine a timing decision to set the timing window (e.g., the FFT window) for the subsequent OFDM symbol (e.g., the symbol n to be demodulated) based on the obtained corrected channel estimate.
• the functionality of block 808 may be effected by the channel estimation block 118 in conjunction with the time tracking block 120, as examples.
• FIG. 9 illustrates another apparatus for performing timing corrections in a wireless device.
• the apparatus 900 receives a wireless signal, such as an OFDM signal, at an antenna 902, which delivers the signal to a module 904 for adjusting the time basis of pilot interlaces to a common time base and combining the interlaces.
• module 904 may be implemented by one or more of elements 102, 104, 106, 108, 110, 116, and 118 illustrated in FIG. 1, as an example.
• the interlaces are delivered to a module 906 for matching the time basis of the combined pilot interlaces with a time base of a symbol to be demodulated.
• Module 906 may be implemented by channel estimation block 118 in FIG. 1, a DSP, a combination thereof, or any other suitable hardware, software, or firmware.
• module 907 determines a corrected channel estimate based on combined pilot interlaces having a time basis matching the symbol. It is noted that module 907 may be implemented by channel estimation block 118 in FIG. 1, a DSP, a combination thereof, or any other suitable hardware, software, or firmware. Module 907 outputs the corrected channel estimate to a module 908 for determining a timing tracking decision based on the channel estimate. Module 908 may be implemented, for example, by channel estimation block 118, timing tracking block 120, the sample server 104, or any combination thereof.
• the timing decision derived by module 908 may be used by the sample server 104, for example, to set (e.g., advance/retard) the FFT window for sampling the received communication signals.
• apparatus 900 may be implemented within a transceiver, such as an OFDM transceiver, and may consist of hardware, software, firmware, or any combination thereof.
• timing updates in frequency may be efficiently executed with a 7 interlace combining channel estimation algorithm.
• the combining of the interlaces is performed by the DSP in the frequency domain to avoid additional direct memory access (DMA) transfers between the FFT engine and DSP memory.
• DMA direct memory access
• the time resolution could be correspondingly higher.
• a fine resolution is, however, not required by the fine-time tracking algorithms.
• a resolution of 1 ex 1 in DVB-T/H would require as smallest phase increment 3 -2 ⁇ /8192 while the hardware rotator used in part of the timing adjustment resolves the whole circle in only 2048 pieces.
• the fine-timing algorithm need only issue timing updates as multiples of 8cxl in DVB-T/H, which ensures that the hardware rotator and DSP can perform all required rotations described below with sufficient precision.
• 8cxl correspond to 0.875 ⁇ s, i.e., the resolution is still sufficiently small when compared to the symbol or guard duration (smallest guard is 7 ⁇ s in mode 1 with 1/32 guard which is a highly unlikely combination).
• the strategy is to adjust the timing of the 7 interlaces combined in channel estimation for time n such that their time-basis matches the time- basis of data-symbol n. This is achieved by ensuring that the six "old" interlaces have a timing corresponding to n and rotating the pilot tones of the latest interlace to be used in the combination (obtained at time n+3) back to time n. So for the latest interlace the effect of the timing updates at times n+1, n+2, and n+3 needs to be reversed. It is possible to denote the sum of these timing updates (CUM T) with the following equation:
• P 1 m is the pilot tone with timing corresponding to n+3.
• This rotation may be performed with a hardware rotator (e.g., 106) under the direction of a DMP (Data Mover Processor).
• DMP Data Mover Processor
• the timing of the buffered pilot interlaces lags the time-tracking algorithm by 3 symbols.
• the update corresponding to the adjustment a n+l is performed in the DSP according to the algorithm visualized in FIG. 10. The idea is to calculate
• the staggering chosen for implementation includes only two stages. One rotator moves over 4 pilot tones, as indicated by arrow 1002, from interlace 0 and pilot tone position 9 to interlace 0 and pilot tone position 10, as an example, which is a rotation of e - J2 ⁇ ml2IW24 or?
• tones may also be easily determined with the complex conjugates of e ⁇ ⁇ and
• the conjugates can be applied in a symmetrical correspondence, as illustrated by arrows 1006 from carrier frequencies 3, 6, and 9, to corresponding symmetrical negative frequencies -3, -6, and -9 in order to determine rotation for the negative carrier tones.
• the disclosed apparatus and methods effect to adjusting timing by ensuring pilot tone interlaces have matching time bases, which also match a symbol time basis.
• DSP digital signal processor
• ASIC application specific integrated circuit
• FPGA field programmable gate array
• a general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
• a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
• a software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
• An exemplary storage medium e.g., memory 122 in FIG. 1 is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
• the processor and the storage medium may reside in an ASIC.
• the ASIC may reside in a user terminal.
• the processor and the storage medium may reside as discrete components in a user terminal.
• the examples described above are merely exemplary and those skilled in the art may now make numerous uses of, and departures from, the above-described examples without departing from the inventive concepts disclosed herein.
• Various modifications to these examples may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other examples, e.g., in an instant messaging service or any general wireless data communication applications, without departing from the spirit or scope of the novel aspects described herein.
• the scope of the disclosure is not intended to be limited to the examples shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

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• Computer Networks & Wireless Communication (AREA)
• Power Engineering (AREA)
• Circuits Of Receivers In General (AREA)
• Synchronisation In Digital Transmission Systems (AREA)
• Mobile Radio Communication Systems (AREA)
• Control Of Amplification And Gain Control (AREA)
• Cash Registers Or Receiving Machines (AREA)
• Control Of Metal Rolling (AREA)
• Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
• Detection And Prevention Of Errors In Transmission (AREA)

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• 2008
  • 2008-03-04 CN CN2008800070878A patent/CN101641920B/zh not_active Expired - Fee Related
  • 2008-03-04 JP JP2009552836A patent/JP5242599B2/ja not_active Expired - Fee Related
  • 2008-03-04 ES ES08731357T patent/ES2376016T3/es active Active
  • 2008-03-04 AT AT08731357T patent/ATE539530T1/de active
  • 2008-03-04 RU RU2009136569/09A patent/RU2009136569A/ru not_active Application Discontinuation
  • 2008-03-04 KR KR1020097020683A patent/KR101126989B1/ko not_active IP Right Cessation
  • 2008-03-04 KR KR1020097020684A patent/KR101129207B1/ko not_active IP Right Cessation
  • 2008-03-04 BR BRPI0808484-0A patent/BRPI0808484A2/pt not_active IP Right Cessation
  • 2008-03-04 EP EP08731357A patent/EP2130338B1/en not_active Not-in-force
  • 2008-03-04 EP EP08743672A patent/EP2130339A1/en not_active Withdrawn
  • 2008-03-04 BR BRPI0808485-8A patent/BRPI0808485A2/pt not_active IP Right Cessation
  • 2008-03-04 RU RU2009136568/09A patent/RU2009136568A/ru not_active Application Discontinuation
  • 2008-03-04 WO PCT/US2008/055797 patent/WO2008109600A1/en active Application Filing
  • 2008-03-04 CA CA002678113A patent/CA2678113A1/en not_active Abandoned
  • 2008-03-04 JP JP2009552837A patent/JP5204131B2/ja not_active Expired - Fee Related
  • 2008-03-04 CA CA002677971A patent/CA2677971A1/en not_active Abandoned
  • 2008-03-04 WO PCT/US2008/055807 patent/WO2008109607A1/en active Application Filing
  • 2008-03-05 TW TW097107712A patent/TWI379559B/zh not_active IP Right Cessation
  • 2008-03-05 TW TW097107709A patent/TWI370650B/zh not_active IP Right Cessation

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