EP2118903A4 - Systeme et procede de fonctionnement de dispositifs de memoire de types combines - Google Patents

Systeme et procede de fonctionnement de dispositifs de memoire de types combines

Info

Publication number
EP2118903A4
EP2118903A4 EP07855464A EP07855464A EP2118903A4 EP 2118903 A4 EP2118903 A4 EP 2118903A4 EP 07855464 A EP07855464 A EP 07855464A EP 07855464 A EP07855464 A EP 07855464A EP 2118903 A4 EP2118903 A4 EP 2118903A4
Authority
EP
European Patent Office
Prior art keywords
memory devices
mixed type
operating memory
operating
mixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07855464A
Other languages
German (de)
English (en)
Other versions
EP2118903A1 (fr
Inventor
Hakjune Oh
Hong Beom Pyeon
Jin-Ki Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/622,828 external-priority patent/US8271758B2/en
Priority claimed from US11/771,241 external-priority patent/US7925854B2/en
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Publication of EP2118903A1 publication Critical patent/EP2118903A1/fr
Publication of EP2118903A4 publication Critical patent/EP2118903A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Memory System (AREA)
  • Information Transfer Systems (AREA)
EP07855464A 2006-12-06 2007-12-04 Systeme et procede de fonctionnement de dispositifs de memoire de types combines Withdrawn EP2118903A4 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US86877306P 2006-12-06 2006-12-06
US87089206P 2006-12-20 2006-12-20
US11/622,828 US8271758B2 (en) 2006-12-06 2007-01-12 Apparatus and method for producing IDS for interconnected devices of mixed type
US11/771,241 US7925854B2 (en) 2006-12-06 2007-06-29 System and method of operating memory devices of mixed type
PCT/CA2007/002182 WO2008067658A1 (fr) 2006-12-06 2007-12-04 Système et procédé de fonctionnement de dispositifs de mémoire de types combinés

Publications (2)

Publication Number Publication Date
EP2118903A1 EP2118903A1 (fr) 2009-11-18
EP2118903A4 true EP2118903A4 (fr) 2010-01-06

Family

ID=39491613

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07855464A Withdrawn EP2118903A4 (fr) 2006-12-06 2007-12-04 Systeme et procede de fonctionnement de dispositifs de memoire de types combines

Country Status (5)

Country Link
EP (1) EP2118903A4 (fr)
JP (3) JP5683813B2 (fr)
KR (3) KR101441280B1 (fr)
TW (1) TWI470645B (fr)
WO (1) WO2008067658A1 (fr)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8463959B2 (en) * 2010-05-31 2013-06-11 Mosaid Technologies Incorporated High-speed interface for daisy-chained devices
TWI425362B (zh) * 2010-12-07 2014-02-01 Alpha Imaging Technology Corp 對應不同記憶體之記憶體介面晶片及建立記憶體傳輸通道之方法
US9697872B2 (en) * 2011-12-07 2017-07-04 Cypress Semiconductor Corporation High speed serial peripheral interface memory subsystem
US8614920B2 (en) 2012-04-02 2013-12-24 Winbond Electronics Corporation Method and apparatus for logic read in flash memory
JP5467134B1 (ja) * 2012-09-27 2014-04-09 華邦電子股▲ふん▼有限公司 フラッシュメモリ装置およびメモリ装置の操作方法
US10067903B2 (en) 2015-07-30 2018-09-04 SK Hynix Inc. Semiconductor device
KR102366767B1 (ko) * 2015-07-30 2022-02-23 에스케이하이닉스 주식회사 반도체 장치
US11755255B2 (en) 2014-10-28 2023-09-12 SK Hynix Inc. Memory device comprising a plurality of memories sharing a resistance for impedance matching
KR102358177B1 (ko) 2015-12-24 2022-02-07 에스케이하이닉스 주식회사 제어회로 및 제어회로를 포함하는 메모리 장치
US10146608B2 (en) * 2015-04-06 2018-12-04 Rambus Inc. Memory module register access
FR3041806B1 (fr) * 2015-09-25 2017-10-20 Stmicroelectronics Rousset Dispositif de memoire non volatile, par exemple du type eeprom, ayant une capacite memoire importante, par exemple 16mbits
GB2568724B (en) * 2017-11-24 2021-08-18 Ge Aviat Systems Ltd Method and apparatus for initializing a controller module
GB2568725B (en) * 2017-11-24 2021-08-18 Ge Aviat Systems Ltd Method and apparatus for initializing a controller module
CN110413197B (zh) * 2018-04-28 2023-06-27 伊姆西Ip控股有限责任公司 管理存储系统的方法、设备和计算机程序产品
TWI696113B (zh) * 2019-01-02 2020-06-11 慧榮科技股份有限公司 用來進行組態管理之方法以及資料儲存裝置及其控制器
US20210081318A1 (en) * 2019-09-17 2021-03-18 Micron Technology, Inc. Flexible provisioning of multi-tier memory
TWI749598B (zh) * 2020-06-18 2021-12-11 華邦電子股份有限公司 一種記憶體裝置及其連續讀寫方法
US11120851B1 (en) 2020-07-12 2021-09-14 Winbond Electronics Corp. Memory apparatus and burst read and burst write method thereof
CN113641595B (zh) * 2021-07-30 2023-08-11 珠海一微半导体股份有限公司 独立块保护模式的spi flash在brom阶段的类型识别方法及系统

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040256638A1 (en) * 2000-01-05 2004-12-23 Richard Perego Configurable width buffered module having a bypass circuit
US20050120136A1 (en) * 2003-10-18 2005-06-02 Samsung Electronics Co., Ltd. Method and system for discovering a mobility anchor point and managing mobility of a mobile node in a network system supporting mobile IP
US20060031593A1 (en) * 2004-08-09 2006-02-09 Sinclair Alan W Ring bus structure and its use in flash memory systems

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US4360870A (en) * 1980-07-30 1982-11-23 International Business Machines Corporation Programmable I/O device identification
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
JPH0484351A (ja) * 1990-07-27 1992-03-17 Sony Corp アドレス設定方法
JPH07105121A (ja) * 1993-09-30 1995-04-21 Nabco Ltd 分散制御装置
JP3168552B2 (ja) * 1993-12-17 2001-05-21 インターナショナル・ビジネス・マシーンズ・コーポレ−ション メモリ・アクセス制御システム及びその方法
US5404460A (en) * 1994-01-28 1995-04-04 Vlsi Technology, Inc. Method for configuring multiple identical serial I/O devices to unique addresses through a serial bus
US5636342A (en) * 1995-02-17 1997-06-03 Dell Usa, L.P. Systems and method for assigning unique addresses to agents on a system management bus
US5708773A (en) * 1995-07-20 1998-01-13 Unisys Corporation JTAG interface system for communicating with compliant and non-compliant JTAG devices
US5860080A (en) * 1996-03-19 1999-01-12 Apple Computer, Inc. Multicasting system for selecting a group of memory devices for operation
JP3850067B2 (ja) * 1996-04-24 2006-11-29 株式会社ルネサステクノロジ メモリシステムおよびそれに用いられる半導体記憶装置
US6175891B1 (en) * 1997-04-23 2001-01-16 Micron Technology, Inc. System and method for assigning addresses to memory devices
US6453365B1 (en) * 1998-02-11 2002-09-17 Globespanvirata, Inc. Direct memory access controller having decode circuit for compact instruction format
US6144576A (en) * 1998-08-19 2000-11-07 Intel Corporation Method and apparatus for implementing a serial memory architecture
JP2002236611A (ja) * 2000-12-04 2002-08-23 Hitachi Ltd 半導体装置と情報処理システム
US6996644B2 (en) * 2001-06-06 2006-02-07 Conexant Systems, Inc. Apparatus and methods for initializing integrated circuit addresses
US7073022B2 (en) * 2002-05-23 2006-07-04 International Business Machines Corporation Serial interface for a data storage array
US7032039B2 (en) * 2002-10-30 2006-04-18 Atmel Corporation Method for identification of SPI compatible serial memory devices
US7308524B2 (en) * 2003-01-13 2007-12-11 Silicon Pipe, Inc Memory chain
US7031221B2 (en) * 2003-12-30 2006-04-18 Intel Corporation Fixed phase clock and strobe signals in daisy chained chips

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040256638A1 (en) * 2000-01-05 2004-12-23 Richard Perego Configurable width buffered module having a bypass circuit
US20050120136A1 (en) * 2003-10-18 2005-06-02 Samsung Electronics Co., Ltd. Method and system for discovering a mobility anchor point and managing mobility of a mobile node in a network system supporting mobile IP
US20060031593A1 (en) * 2004-08-09 2006-02-09 Sinclair Alan W Ring bus structure and its use in flash memory systems

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2008067658A1 *

Also Published As

Publication number Publication date
WO2008067658A1 (fr) 2008-06-12
JP5351130B2 (ja) 2013-11-27
JP2014063523A (ja) 2014-04-10
TWI470645B (zh) 2015-01-21
KR20120135334A (ko) 2012-12-12
TW200845037A (en) 2008-11-16
JP5683813B2 (ja) 2015-03-11
JP2011054204A (ja) 2011-03-17
JP2010511943A (ja) 2010-04-15
KR101441225B1 (ko) 2014-09-17
KR20090102787A (ko) 2009-09-30
JP5695724B2 (ja) 2015-04-08
KR101441154B1 (ko) 2014-09-17
EP2118903A1 (fr) 2009-11-18
KR20140019478A (ko) 2014-02-14
KR101441280B1 (ko) 2014-09-17

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Effective date: 20091204

RIC1 Information provided on ipc code assigned before grant

Ipc: G11C 16/02 20060101ALI20091130BHEP

Ipc: G11C 8/06 20060101ALI20091130BHEP

Ipc: G06F 13/40 20060101ALI20091130BHEP

Ipc: G06F 13/16 20060101ALI20091130BHEP

Ipc: G11C 7/10 20060101ALI20091130BHEP

Ipc: G11C 11/34 20060101ALI20091130BHEP

Ipc: G11C 8/18 20060101AFI20080701BHEP

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Ipc: G11C 7/20 20060101ALI20091130BHEP

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Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

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