EP2100206A1 - Systèmes, circuits, puces et procédés avec protection au niveau de frontières d'îlots de puissance - Google Patents

Systèmes, circuits, puces et procédés avec protection au niveau de frontières d'îlots de puissance

Info

Publication number
EP2100206A1
EP2100206A1 EP07871754A EP07871754A EP2100206A1 EP 2100206 A1 EP2100206 A1 EP 2100206A1 EP 07871754 A EP07871754 A EP 07871754A EP 07871754 A EP07871754 A EP 07871754A EP 2100206 A1 EP2100206 A1 EP 2100206A1
Authority
EP
European Patent Office
Prior art keywords
island
integrated circuit
isolation
protected
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP07871754A
Other languages
German (de)
English (en)
Other versions
EP2100206B1 (fr
EP2100206A4 (fr
Inventor
Darmin Jin
Brian Cheung
Steve Skala
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Technologies LLC
Original Assignee
SanDisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SanDisk Corp filed Critical SanDisk Corp
Publication of EP2100206A1 publication Critical patent/EP2100206A1/fr
Publication of EP2100206A4 publication Critical patent/EP2100206A4/fr
Application granted granted Critical
Publication of EP2100206B1 publication Critical patent/EP2100206B1/fr
Not-in-force legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit

Definitions

  • the present application relates to systems and integrated circuits which include multiple independently powered-up "power islands" inside a single integrated circuit.
  • the present application discloses new approaches to power island architecture: overvoltage and/or undervoltage protection is added to the isolation circuitry.
  • the isolation circuitry including the protection circuitry, is used on every line which crosses a power island boundary.
  • Isolation is commonly used at the boundaries of power islands (and elsewhere), to suppress propagation of unknown states or transients.
  • the isolation cells may force a line low, or force it high, or (less commonly) preserve the last valid state of the line.
  • the disclosed innovations replace standard isolation cells, in designs having power islands, with protected-isolation cells.
  • the protected-isolation cells are used for every digital line which crosses a power island boundary.
  • protected-isolation cells are used for every digital line which crosses a power island boundary, except for clock lines where skew or phase shift are particularly undesirable.
  • Figure 1 shows an example of the protection circuit which is added to the appropriate isolation cell, in the presently preferred embodiment.
  • Figure 2 shows how the protection stage of Figure 1 is preferably combined with signal isolation at power island boundaries.
  • Figure 3 shows an example of a chip in which the cells of Figure 1 have been used advantageously.
  • Figure 4 is a detail view of a particular example, within the chip of Figure 3, where isolation as in Figure 2 is advantageously used.
  • Figure 5A is a flowchart of the general sequence of shutting down a power island
  • Figure 5B is a flowchart of the general sequence of restoring power.
  • Island power down of logic modules and RAM blocks can be physically accomplished with Analog power gating/switching cells.
  • careful consideration is required to ensure that Logical state of the rest of the controller is maintained during island power removal, un-powered logic standby, and re-application of power to one or more islands.
  • Figure 1 shows an example of the protection circuit which is added to the appropriate isolation cell, in the presently preferred embodiment.
  • the illustrated structure shows overvoltage/undervoltage clamping for two lines, OUTl and OUT2. (The other connections of OUTl and OUT2 are not affected by this block.)
  • the isolation component is provided by a capacitor from OUTl to ground, and another from OUT2 to ground. This provides the complete protected isolation cell 100.
  • MNI2 if OUTl exceeds the positive supply voltage VDD by more than a diode drop, MNI2 will turn on to pull OUTl down to VDD+VTN. Similarly, if OUTl goes below ground by more than a diode drop, MNIl will turn on to pull OUTl up to -VTN.
  • MNl and MN2 have a W/L ratio of 6: 1, but this ratio can be as large as layout permits. Preferably this ratio is at least 3:1, to provide adequately low clamping impedance.
  • Figure 2 shows how the protection stage of Figure 1 is preferably combined with signal isolation at power island boundaries.
  • the isolation logic is simply shown as an OR, but of course many other logic relations can be used if desired.
  • a logic output from power island 200 is not only gated by the isolation gate, but also clamped by a clamp circuit 100.
  • a single line running from a power island to always-on logic is shown, but the illustrated implementation is also applicable to isolation between independent power islands.
  • Figure 2 shows an example of the protected-isolation block 100'.
  • Figure 3 shows an example of a chip in which the cells of Figure 1 have been used advantageously. Note, for example, the diamond- shaped blocks between NVM and Crypto blocks; these are discussed in more detail below. This particular design includes a number of dynamically- switched power islands, but the detailed operation of these power islands is not essential to understand the operation of the disclosed protected-isolation blocks 100'.
  • FIG 4 is a detail view of a particular example, within the chip of Figure 3, where isolation as in Figure 2 is advantageously used.
  • This example shows a detail of the interface between the nonvolatile memory 406 ("NVM") and the crypto logic 408 of Figure 3. Note that, as also shown in Figure 3, the crypto logic 408 is inside a dynamic power island.
  • NVM nonvolatile memory 406
  • the crypto logic 408 is inside a dynamic power island.
  • Step 210) Make sure that all pending transactions to/from power island to be shut down are completed and the interface to the island is idle
  • Step 220 Isolate output signals from the power island that will be shut down.
  • Step 230 Soft reset the power island that is to be shut down (and hold in reset).
  • Step 240 Disable clocks to the power island that will be shut down.
  • Step 250 Isolate input signals from power island that will be shut down.
  • Step 260 Switch off power delivery to island.
  • step 260 All of these steps, and especially step 260, are accompanied by the important simultaneous action 270 of clamping overvoltages or undervoltages, using, for example, a stage like the stage 100 shown in Figure 1.
  • Step 310 Check that the island soft reset, clock gate, and isolation cell control bits are ON and the interface to island is still in idle state
  • Step 320 Switch on power delivery to the island. (From step A, reset is still driven to island, clocks are blocked and island outputs are still isolated)
  • Step 330 Remove isolation of input signals from power island.
  • Step 340 Enable clocks to island (while island is still held in reset)
  • Step 350 Remove isolation of output signals from power island (while island is still held in reset)
  • step 320 All of these steps, and especially step 320, are accompanied by the important simultaneous action 380 of clamping overvoltages or undervoltages, using, for example, a stage like the stage 100 shown in Figure 1.
  • Island control registers provide bit-per-island control of the Island Power ON and OFF sequences.
  • a fifth register provides bit-per-island status of the power island Analog switches.
  • Firmware has full control of the sequencing procedure, so timing can be optimized for product reliability and performance.
  • Power islands refer to sections of the chip that can be powered on/off independently from other areas of the chip to minimize total power budget during non-operation, standby or test modes. The rest of the chip will always be powered on. This always-on section of the chip should include the following items (BE, most RAM, PWR_CONTROL, ACOMP/ASECURE blocks, IO pad ring and miscellaneous glue logic).
  • Tripoli handles three major Power functions:
  • All registers mentioned in this preferred embodiment are hardware reset only by power on reset (POR_N).
  • POR_N power on reset
  • the registers will also be accessible in the jtag domain for test mode access.
  • BE PAM Peripheral Access Mode
  • the system clock must be running for firmware to have access to these registers.
  • JTAG access to those registers in order to sequence the power islands for test mode functions both jtag clock and system clock must be running.
  • a method for operating an integrated circuit which contains multiple power islands comprising the actions of: a) clamping the voltage of at least some digital signals at power island boundaries; and b) isolating at least some digital signals at said power island boundaries; wherein said actions (a) and (b) are jointly performed, for a respective line at a respective boundary, by a respective protected-isolation cell.
  • a method for operating an integrated circuit which contains multiple power islands comprising the actions of: a) clamping at least some digital signals at power island boundaries, to thereby suppress both overvoltages and undervoltages; and b) isolating at least some digital signals at said power island boundaries; wherein said actions (a) and (b) are jointly performed, for a respective line at a respective boundary, by a respective protected-isolation cell.
  • a method for operating an integrated circuit which contains multiple power islands comprising the actions of: a) clamping substantially all digital signals which cross any power island's boundary, to thereby suppress overvoltages and undervoltages; and b) isolating substantially all non-clock digital signals at said power island boundaries, to thereby suppress propagation of signals across a powered-down island's boundary; wherein said actions a and b are jointly performed, for a respective line at a respective boundary, by a respective protected-isolation cell.
  • An integrated circuit comprising: at least one power island; and protected—isolation cells, where digital signals connect to said power island, which both clamp voltage excursions of the signals when the island is ON, and isolate the island when it is OFF.
  • An integrated circuit comprising: multiple power islands; and protected—isolation cells, at substantially all locations where non-clock digital signals connect to one of said power islands, which both clamp voltage excursions of the signals when the island is powered on, and isolate the island when it is powered off.
  • An integrated circuit comprising; at least one power island, containing electrical circuits which are not always powered up; and a plurality of protected-isolation cells, electrically interposed between said circuits and digital signal lines; wherein ones of said protected-isolation cells also contain voltage clamps; wherein, when said island is powered up, said protected-isolation cells connect digital signals between said circuits and said digital signal lines, while limiting voltage excursions on said lines; and wherein, when said island is not powered up, said protected-isolation cells prevent propagation of signals from said circuits onto said digital signal lines.
  • a circuit comprising: a power island; circuit elements within said power island, which are operatively connected to receive and send signals on a plurality of input/output lines; and a protection and isolation circuit, located on a respective one of said input/output lines, which both disconnects said respective line when said power island is powered down separately, and clamps voltage excursions on said respective line.
  • overvoltage clamp circuit illustrated in the sample embodiment is merely an example, and many others can be substituted.
  • the preferred embodiment clamps undervoltages as well as overvoltages. This is preferable, but it is contemplated that alternative embodiments can use a clamp structure which only clamps overvoltages.
  • clamp circuits used should be compatible with core logic design rules, and should not require use of deep diffusions or other process steps which are not normally used within core logic.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

L'invention concerne des circuits intégrés où la cellule d'isolation standard, au niveau de frontières d'îlots de puissance, comprend également un dispositif de protection, qui fixe des tensions transitoires.
EP07871754.3A 2006-12-31 2007-12-31 Systèmes, circuits, puces et procédés avec protection au niveau des frontières des îlots de puissance Not-in-force EP2100206B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US93492306P 2006-12-31 2006-12-31
US99976006P 2006-12-31 2006-12-31
PCT/US2007/089190 WO2008083369A1 (fr) 2006-12-31 2007-12-31 Systèmes, circuits, puces et procédés avec protection au niveau de frontières d'îlots de puissance

Publications (3)

Publication Number Publication Date
EP2100206A1 true EP2100206A1 (fr) 2009-09-16
EP2100206A4 EP2100206A4 (fr) 2013-06-26
EP2100206B1 EP2100206B1 (fr) 2014-08-27

Family

ID=39589009

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07871754.3A Not-in-force EP2100206B1 (fr) 2006-12-31 2007-12-31 Systèmes, circuits, puces et procédés avec protection au niveau des frontières des îlots de puissance

Country Status (7)

Country Link
US (1) US8072719B2 (fr)
EP (1) EP2100206B1 (fr)
JP (1) JP2010515276A (fr)
KR (1) KR101424534B1 (fr)
CN (1) CN101627347B (fr)
TW (1) TWI390391B (fr)
WO (1) WO2008083369A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10318102A (ja) * 1997-05-20 1998-12-02 Honda Motor Co Ltd 副燃焼室付き火花点火式２サイクル内燃機関
US20080162957A1 (en) * 2006-12-31 2008-07-03 Paul Lassa Selectively powering data interfaces
US20080162954A1 (en) * 2006-12-31 2008-07-03 Paul Lassa Selectively powered data interfaces
US8135944B2 (en) * 2007-03-14 2012-03-13 Sandisk Technologies Inc. Selectively powered data interfaces
US8022727B2 (en) 2008-01-29 2011-09-20 Nxp B.V. Electronic clamps for integrated circuits and methods of use
US10810337B2 (en) * 2017-11-03 2020-10-20 Mediatek Singapore Pte. Ltd. Method for modeling glitch of logic gates
US11093019B2 (en) 2019-07-29 2021-08-17 Microsoft Technology Licensing, Llc Integrated circuit power domains segregated among power supply phases
US11693472B2 (en) 2021-08-31 2023-07-04 Apple Inc. Multi-die power management in SoCs

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040158750A1 (en) * 2003-02-10 2004-08-12 Syed Masood U. Reduced power consumption for embedded processor
WO2005024910A2 (fr) * 2003-09-09 2005-03-17 Robert Eisenstadt Appareil et procede de gestion d'energie de circuits integres

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529551A (ja) * 1991-07-19 1993-02-05 Fujitsu Ltd 半導体集積回路
JPH0837238A (ja) * 1994-07-21 1996-02-06 Hitachi Ltd 半導体集積回路装置
US5528190A (en) * 1994-10-03 1996-06-18 Delco Electronics Corporation CMOS input voltage clamp
EP0740344B1 (fr) * 1995-04-24 2002-07-24 Conexant Systems, Inc. Procédé et appareil pour le couplage de bus on-chip Vdd multiples, indépendants à un verrouillage ESD
KR970051262A (ko) * 1995-12-29 1997-07-29 김주용 비트라인 클램프 회로
US5917220A (en) * 1996-12-31 1999-06-29 Stmicroelectronics, Inc. Integrated circuit with improved overvoltage protection
US6414533B1 (en) * 1999-11-23 2002-07-02 Texas Instruments Incorporated Over-voltage tolerant, active pull-up clamp circuit for a CMOS crossbar switch
US6388503B1 (en) * 2000-09-28 2002-05-14 Intel Corporation Output buffer with charge-pumped noise cancellation
US6631502B2 (en) * 2002-01-16 2003-10-07 International Business Machines Corporation Method of analyzing integrated circuit power distribution in chips containing voltage islands
US7444524B2 (en) * 2002-12-30 2008-10-28 Intel Corporation Dynamic voltage transitions
US7428675B2 (en) 2003-02-20 2008-09-23 International Business Machines Corporation Testing using independently controllable voltage islands
US7512521B2 (en) 2003-04-30 2009-03-31 Fisher-Rosemount Systems, Inc. Intrinsically safe field maintenance tool with power islands
EP1623349B1 (fr) * 2003-05-07 2018-01-24 Conversant Intellectual Property Management Inc. Gestion d'energie sur des circuits integres utilisant des ilots de puissance
US7000214B2 (en) * 2003-11-19 2006-02-14 International Business Machines Corporation Method for designing an integrated circuit having multiple voltage domains
US7111266B2 (en) * 2003-11-24 2006-09-19 International Business Machines Corp. Multiple voltage integrated circuit and design method therefor
US7227383B2 (en) * 2004-02-19 2007-06-05 Mosaid Delaware, Inc. Low leakage and data retention circuitry
US7529958B2 (en) * 2004-11-15 2009-05-05 Charles Roth Programmable power transition counter
JP4188974B2 (ja) * 2006-02-06 2008-12-03 株式会社ルネサステクノロジ 半導体集積回路
US7511528B2 (en) * 2006-08-02 2009-03-31 International Business Machines Corporation Device and method to eliminate step response power supply perturbation
US7739533B2 (en) * 2006-09-22 2010-06-15 Agere Systems Inc. Systems and methods for operational power management
US7511550B2 (en) * 2006-09-26 2009-03-31 Agere Systems Inc. Method and apparatus for improving reliability of an integrated circuit having multiple power domains
US20080080107A1 (en) * 2006-09-29 2008-04-03 Huaya Microelectronics, Ltd. ESD protection for integrated circuits with multiple power domains
US8135944B2 (en) * 2007-03-14 2012-03-13 Sandisk Technologies Inc. Selectively powered data interfaces
US7904838B2 (en) * 2007-08-15 2011-03-08 Ati Technologies Ulc Circuits with transient isolation operable in a low power state
US7830039B2 (en) * 2007-12-28 2010-11-09 Sandisk Corporation Systems and circuits with multirange and localized detection of valid power
US20090204837A1 (en) * 2008-02-11 2009-08-13 Udaykumar Raval Power control system and method
US20090204835A1 (en) * 2008-02-11 2009-08-13 Nvidia Corporation Use methods for power optimization using an integrated circuit having power domains and partitions

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040158750A1 (en) * 2003-02-10 2004-08-12 Syed Masood U. Reduced power consumption for embedded processor
WO2005024910A2 (fr) * 2003-09-09 2005-03-17 Robert Eisenstadt Appareil et procede de gestion d'energie de circuits integres

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
KAIJIAN SHI: "Dual threshold voltages and power-gating design flows offer good results", EDN ELECTRICAL DESIGN NEWS.(TEXAS INSTRUMENT), REED BUSINESS INFORMATION, HIGHLANDS RANCH, CO, US, 2 February 2006 (2006-02-02), pages 65-70, XP002503531, ISSN: 0012-7515 *
See also references of WO2008083369A1 *

Also Published As

Publication number Publication date
US20080297961A1 (en) 2008-12-04
WO2008083369A8 (fr) 2009-09-11
EP2100206B1 (fr) 2014-08-27
TWI390391B (zh) 2013-03-21
KR101424534B1 (ko) 2014-08-01
EP2100206A4 (fr) 2013-06-26
CN101627347B (zh) 2012-07-04
CN101627347A (zh) 2010-01-13
US8072719B2 (en) 2011-12-06
JP2010515276A (ja) 2010-05-06
TW200842564A (en) 2008-11-01
WO2008083369A1 (fr) 2008-07-10
KR20090094314A (ko) 2009-09-04

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