EP2093614A1 - Directives pour la division et le design de motifs doubles - Google Patents

Directives pour la division et le design de motifs doubles Download PDF

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Publication number
EP2093614A1
EP2093614A1 EP08160666A EP08160666A EP2093614A1 EP 2093614 A1 EP2093614 A1 EP 2093614A1 EP 08160666 A EP08160666 A EP 08160666A EP 08160666 A EP08160666 A EP 08160666A EP 2093614 A1 EP2093614 A1 EP 2093614A1
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EP
European Patent Office
Prior art keywords
design
features
metric
stitching
patterning
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Withdrawn
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EP08160666A
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German (de)
English (en)
Inventor
Vincent Jean-Marie Pierre Paul Wiaux
Staf Verhaegen
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Interuniversitair Microelektronica Centrum vzw IMEC
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Interuniversitair Microelektronica Centrum vzw IMEC
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Application filed by Interuniversitair Microelektronica Centrum vzw IMEC filed Critical Interuniversitair Microelektronica Centrum vzw IMEC
Priority to EP09153324A priority Critical patent/EP2093616A1/fr
Priority to US12/390,377 priority patent/US20090217224A1/en
Priority to JP2009038912A priority patent/JP2009200499A/ja
Publication of EP2093614A1 publication Critical patent/EP2093614A1/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70475—Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G03F1/44—Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging

Definitions

  • the present invention relates to the field of lithographic processing, used e.g. in the manufacturing of semiconductor devices such as integrated circuits, and process optimisation in general. More particularly, the present invention relates to methods and systems for optimising double patterning techniques for lithographic processing, to devices thus obtained and to lithographic masks used with such methods for double patterning techniques.
  • the 2D printability of the patterns needs to be taken into account to validate the benefit of a split. Indeed, small gaps at line-ends and critical 2D topologies are as important as sub-resolution- or forbidden-pitches. Because the cutting of polygons is not always sufficient to solve the split conflicts, there is a need for split- or even design- rules to ensure the benefit of double patterning.
  • cutting of polygons in the design for double patterning may be a suitable solution to colouring, i.e. the assigning of polygons or parts thereof to two different layers to be patterned separately, because methods and systems are provided allowing recombination of polygons in a robust way through double patterning process variations.
  • the present invention relates to a method for optimizing multiple patterning lithographic processing of a pattern in a single layer, the pattern comprising a plurality of design features, the multiple patterning lithographic processing comprising a first patterning step and at least a second patterning step, the method comprising, for at least one and optionally a plurality of process conditions, obtaining values for at least one metric expressing a splitting correlated process quality as function of design parameters of the pattern and/or split parameters for the multiple patterning lithographic processing, and evaluating said values of the at least one metric as function of design and/or split parameters taking into account said at least one process condition. It is an advantage of embodiments according to the present invention that double patterning lithographic processing can be optimized as function of the at least one process condition. Said evaluating of the values for the metric may be performed with respect to predetermined criteria.
  • Obtaining values for at least one metric expressing a splitting correlated process quality may comprise obtaining values for at least one metric expressing a stitching correlated process quality.
  • Obtaining values for at least one metric expressing a stitching correlated process quality may comprise obtaining values for a parameter expressing a degree of stitching between design features patterned in the first patterning step and design features patterned in the at least a second patterning step.
  • Said evaluating values of the at least one metric may comprise evaluating whether the stitching width, being the smallest internal distance between merged contours of the design features patterned in the first patterning step and the design features patterned in the second patterning step, is larger than a predetermined value. It is an advantage of embodiments according to the present invention that a good metric for expressing splitting quality, e.g. stitching quality and stitching failure, is used. An insufficient stitching quality may be determined by a stitching width being smaller than a predetermined value, such as e.g. smaller than 90% of the nominal critical dimension obtainable or 60% of the nominal critical dimension obtainable or 30% of the nominal critical dimension obtainable or 10% of the nominal critical dimension obtainable.
  • the metric expressing a splitting correlated process quality may comprise any of a circuit performance, an electric metric or a patterning metric. It may for example comprise reliability as quality parameter.
  • the method may furthermore comprise determining values for at least one further metric, not correlated to the splitting process, the metric expressing an incomplete optical proximity correction, for expressing bridging and/or for expressing pinching as function of design parameters of the pattern and/or splitting parameters for the multiple patterning lithographic processing and evaluating said at least one further metric. It is an advantage according to embodiments of the present invention that different process failure causes can be taken into account simultaneously.
  • the method may comprise topologically organising said values of said at least one metric so that for a given value of the first and second design and/or split parameters, values of the at least one metric are positioned equidistant for subsequent values of the third design and/or split parameter in said topologically organised values. It is an advantage of embodiments according to the present invention that a large number of design and/or process parameters can be taken into account for evaluating the at least one metric. It is an advantage of embodiments according to the present invention that a good comparison between metric values can be obtained, such that for example a size for a usable process window can be relatively easy determined.
  • the topologically organised values may be organised in matrix form.
  • Evaluating values of the at least one metric may comprise determining a process window for performing said lithographic processing so as to obtain a predetermined value for the metric expressing the splitting correlated process quality. It is an advantage of embodiments according to the present invention that a process window for the lithographic processing can be determined wherein the splitting, e.g. stitching, is appropriate throughout the process window.
  • the method further may comprise, based on said evaluating, deriving design and/or split guidelines for splitting patterns to be processed using multiple patterning lithographic processing. It is an advantage of embodiments according to the present invention that for appropriate test structures suitable information can be obtained in general, without the need for performing this for each specific structure in the devices to be made. Obtaining a value may be performed based on simulation of the multiple patterning lithographic process. Obtaining a value may be performed based on experimentally obtained measurement data. Obtaining a value may be performed by determining, e.g. experimentally, a value for the at least one metric for a plurality of test structures under a plurality of process conditions.
  • the method further may comprise deriving working values for design and/or split settings for multiple patterning lithographic processing of a pattern in a single layer.
  • the present invention also relates to a design for test patterns, wherein the test pattern are adapted for use in a method for optimising multiple patterning lithographic processing of a pattern as described above.
  • the present invention also relates to a design for test patterns comprising a plurality of features for being processed, the design being a split design comprising a first sub-design with a first set of sub-features and at least a second sub-design with a second set of sub-features so as to obtain said plurality of features when using the design for multiple patterning lithographic processing, wherein said plurality of features have at least one parameterised property so that a systematic variation of the property between different features is present.
  • the plurality of features may comprise a first, a second and a third parameterised property, whereby the features may be topologically organised so that features having the same value for the first parameterised property are positioned equidistant from each other, features comprising the same value for the second parameterised property are positioned equidistant and features comprising the same value for the third parameterised property are positioned equidistant from each other.
  • the present invention furthermore relates to a set of reticles for optimising multiple patterning lithographic processing of a pattern in a single layer, the reticles comprising test patterns according to a design as described above.
  • the present invention also relates to a system for optimising multiple patterning lithographic processing of a pattern in a single layer, the pattern comprising a plurality of design features, the multiple patterning lithographic processing comprising at least a first patterning step and a second patterning step, the system comprising a metric determination means for obtaining, for at least one and optionally a plurality of process conditions, values for a metric expressing a splitting correlated process quality as function of design parameters of the pattern and/or split parameters for the double patterning lithographic processing, and an evaluation means for evaluating said values of the at least one metric as function of the design and/or split parameters taking into account said at least one process condition.
  • the splitting correlated process quality may be a stitching correlated process quality.
  • the invention also relates to a method for multiple patterning lithographic processing of a pattern in a single layer, wherein the method comprises splitting a design to be patterned according to predetermined splitting rules in a first set of design features and a the at least a second set of design features, performing a first patterning step for the first set of pattern features and a second patterning step for second set of pattern features, wherein said predetermined splitting rules are obtained using a method for optimising multiple patterning lithographic processing as described above.
  • the present invention also relates to a reticle or set of reticles optimised using a method according to an embodiment of the present invention. The first set of design features and the at least a second set of design features used in the multiple patterning lithographic processing thereby may combine to the target pattern to be applied in the layer.
  • the present invention furthermore relates to a device made by multiple patterning lithographic processing, the device being made with a multiple patterning lithographic processing of a pattern in a single layer optimised using a method according to an embodiment of the present invention.
  • the present invention also relates to a computer program product adapted for, when executed on a computer, performing the method of optimising multiple patterning lithographic processing of a pattern in a single layer as described above.
  • the present invention also relates to a machine readable data storage device storing the computer program product as described above and/or to the transmission of the computer program product as described above over a local or wide area telecommunications network.
  • teachings of the present invention permit the design of improved lithographic processing methods, having a good yield, thus resulting in good lithographically processed devices fulfilling the required specifications.
  • splitting or design splitting refers to the division of design features in two or more sets of features, the design features being design features of a pattern to be applied in a single layer. The latter thus results in the application of multiple patterning for forming a pattern in a single layer.
  • Splitting of the design also may refer to cutting and stitching, i.e. cutting of certain features in sub-features, at least partly patterning them and stitching the sub-features together so as to obtain the features as targeted in the single layer. Splitting thus refers to both dividing in between features and cutting features in smaller pieces and thereafter bringing them back together after at least part of the processing.
  • FIG. 1a and FIG. 1b both illustrate examples of design splitting patterns, whereas only the second example ( FIG. 1 b) illustrates an example of a cutting and stitching pattern.
  • the first example ( FIG. 1a ) illustrates an example of dividing a set of design features into two separate subsets of design features.
  • the dashed line illustrates for both examples the splitting line. In both schematic figures, the original pattern is given on the left hand side whereas the split pattern is given on the right hand side.
  • the present invention relates to a method for optimising multiple patterning lithographic processing of a pattern in a single layer comprising a plurality of design features.
  • Such multiple patterning lithographic processing may for example be double patterning processing, whereby the creation of features in a pattern in a single layer comprises at least a first patterning step and a second patterning step.
  • creation of features in a pattern using more than 2 patterning steps before developing the resist also is envisaged.
  • the optimisation method comprises, for at least one process condition, optionally for a plurality of process conditions, obtaining values for at least one metric expressing a splitting correlated process quality as function of design parameters and/or split parameters for the multiple patterning lithographic processing.
  • the metric may be expressing a stitching correlated process quality. It is to be noticed that, whereas the method already provides advantages for optimising splitting processes, the method is especially suitable for the particular category of cut and stitching of designs.
  • the metric may express an electric property, a patterning property, a circuit performance, ... that is a function of the stitching process that is performed.
  • the metric may for example express the lack of bridging occurring around the stitching point.
  • the metric may also be directly express a stitching parameter, for example it may express a degree of stitching between design features patterned in the first patterning and design features patterned in the second patterning step.
  • the method also comprises evaluating the values of the at least one metric as function of design and/or split parameters taking into account the plurality of process conditions. Furthermore, the method may comprise selecting, based on the evaluation, the design and split parameters to be used in a particular application thereby taking into account the at least one process condition and optionally evaluation for a plurality of process conditions. Alternatively or in addition thereto, the method furthermore may comprise determining, based on the evaluation, guidelines for design and/or split parameters. In some embodiments according to the present invention, taking into account the plurality of process conditions comprises selecting the design and split parameters so that good metric values are obtained for a sufficiently large process window.
  • methods of multiple patterning may be subject to split, including cut and stitch, restrictions and design restrictions.
  • the methods of multiple patterning may assist in determination of split parameters for performing appropriate splitting in order to obtain good multiple patterning lithographic processing.
  • the latter may for example involve complex polygon splitting.
  • Methods according to the present invention may be especially suitable for complex structures, such as for example random logic structures, although the invention is not limited thereto.
  • good split and design guidelines can be derived for ensuring robust splitting, e.g. stitching, through process variations for multiple patterning lithographic processing of patterns.
  • embodiments of the present invention allow to identify a parameter space in which the splitting, e.g. stitching, obtained is robust through process variations.
  • guidelines for design parameters and/or splitting parameters for structures to be patterned using multiple patterning lithographic processing can be derived, even for structures with added complexity.
  • FIG. 2 an overview of standard and optional steps according to a method for optimising multiple patterning lithographic processing 100 is shown in FIG. 2 .
  • the method 100 may comprise in a first step 110 obtaining representative two dimensional test patterns.
  • Such test patterns may comprise generic structures for the application of interest. By performing the method on test patterns, split and design parameters and guidelines for these parameters may be derived more efficient then when a real pattern to be patterned would be used in the optimisation method.
  • the test structures advantageously comprise features wherein a variation of design parameters is present, such as for example a variation in pitch, target critical dimension, gaps, topology, etc.
  • the test structures also may comprise features split so that a variation of split parameters for the features is present.
  • Such features may be split in at least first sub-features to be patterned in at least a first step and at least second sub-features to be patterned in at least a second step.
  • the variation of split parameters may for example be a variation in split position, variation in stitching overlap etc.
  • the test structures may be implemented as layout or they may be implemented as physical structures on a mask.
  • the test patterns used for the structures may be particularly designed, may be obtained from a database, may be obtained from previous experiments, etc.
  • the test patterns may be topologically organised. Such topological organisation may be such that test patterns having a variation in a value for one parameter while having the same values for other parameters are positioned equidistant from each other or positioned at fixed or systematically varied distances.
  • test patterns may be particularly selected so as to provide appropriate information for applications of interest, e.g. for the patterning of random logic patterns.
  • the test patterns used may be such that design and split parameters are varied systematically.
  • an application of interest indicating a 45nm half pitch random logic metal layout and possible test patterns that can be used therefore are shown in FIG. 3 .
  • The.45nm half pitch random logic metal layout is shown at the left hand side, while three possible test patterns are shown at the right hand side.
  • the method may comprise performing an optical proximity correction (OPC) for one selected patterning process.
  • OPC optical proximity correction
  • OPC may be performed in a conventional manner, e.g. by using a calibrated resist model or e.g. by using a non-calibrated resist model, such as a non-calibrated constant threshold resist model, although the invention is not limited thereto.
  • parameters describing an optional optical proximity correction may be incorporated in the determination of the metric expressing a stitching correlated process quality. Parameters describing the optical proximity correction therefore may be considered design parameters and used in the metric determining step 130.
  • the method comprises determining results for at least one metric expressing a splitting correlated process quality, e.g. a stitching correlated process quality.
  • a splitting correlated process quality e.g. a stitching correlated process quality.
  • the latter is performed as function of design parameters of the pattern and/or as function of split parameters for the multiple patterning process, e.g. by using different test structures for obtaining such values for the at least one metric and/or by using different sub-features for the first patterning step and an at least second patterning step.
  • Obtaining results furthermore may be performed as function of different process conditions, i.e. for a plurality of process conditions.
  • the different process variables that may be taken into account may be any variable expressing the variation of the patterning process such as for example the illumination conditions in general, the dose, the depth of focus, the illumination source used, the overlay on the wafer, etc.
  • Obtaining results for the metric may be achieved based on simulations with a calibrated model, based on experiments, based on aggregate imaging system (AIMS) measurements. Simulations may be performed using any conventional simulation packet for lithographic patterning such as for examle ProlithTM, Solid ETM, Mentor OPC VerifyTM or Synopsis SiVlTM.
  • the results of the metric may be expressed as a value for the metric, e.g. a numerical value for the metric.
  • stitching, correlated process parameter may advantageously be the stitching width.
  • the stitching width may be the smallest internal distance between merged contours of the design features patterned in the first patterning step and the design features patterned in at least the second patterning step.
  • FIG. 4 an example of how the stitching width is defined is shown in FIG. 4 .
  • the distance is indicated for three different stitches, being the (smallest) distance between the two arrows. It is an advantage of embodiments according to the present invention that the splitting, e.g. stitching, parameters and design parameters derived with these methods are not only good under optimum process conditions, but that the yield obtained through process variations still is sufficiently high.
  • the stitching quality therefore is judged based on a metric determined under various process conditions, e.g. in detuned process conditions.
  • the detuned process parameters may for example be obtained by varying the dose, in best focus, over a predetermined value such as for example over ⁇ 3%, by varying the focus, in best dose, over a predetermined value such as for example over ⁇ 50nm. Variation of the other process parameters also may be performed, such as for example varying the illumination type.
  • Other metrics expressing a stitching correlated process quality may for example be the occurrence of or the amount of bridging or pinching that occurs at the stitching area, an electric parameter influenced by the stitching, a circuit performance influenced by the stitching, etc.
  • the metric may be evaluated only for a limited number of parameter values, e.g. for particularly selected parameter sub-spaces, for particularly selected parameter groups and/or for particularly selected process conditions, for selected sets of process conditions, etc.
  • predetermined sets thus may be selected, predetermined parameter ranges to be checked may be selected, predetermined parameter relationships may be taken into account, etc.
  • values may be determined for other metrics.
  • metrics also may express a degree of splitting, e.g. stitching, between design features.
  • such metrics also may express different features of the lithographic processing such as for example expressing an incomplete optical proximity correction, expressing bridging and/or pinching.
  • an evaluation of the results for the at least one metric is performed.
  • Such an evaluation may express whether or not the obtained results correspond with a sufficiently good lithographic processing result or not.
  • Such an evaluation may comprise defining process failure flags.
  • Such process failure flags may indicate whether or not the determined results for the at least one metric are according to predetermined criteria.
  • stitching can suffer from overlay errors between the different patterning steps. Overlay errors may be induced in X and Y direction. Stitching may be checked between contours experiencing overlay shift, with the multiple patterning steps performed in defocus, decreased dose and downsized mask.
  • Such criteria may be determined based on previously performed experiments, calculations, etc.
  • One example of such an evaluation may be evaluation whether a stitching width is smaller or larger than a predetermined value.
  • a stitching width being smaller than a predetermined value, such as e.g. smaller than 90% of the nominal critical dimension obtainable or 60% of the nominal critical dimension obtainable or 30% of the nominal critical dimension obtainable or 10% of the nominal critical dimension obtainable.
  • the evaluation may be expressed as binary result, indicating either sufficient or insufficient quality, although also more detailed evaluation expressing intermediate quality levels for the lithographic processing may be obtained. It is an advantage of embodiments according to the present invention to use stitching width as a metric, as the area of overlap in stitching between two contours may be marginal while still a robust stitching is obtained.
  • FIG. 5 illustrates from left to right different process failure criteria, being an incomplete OPC (a), the occurrence of bridging (b), the occurrence of pinching (c) and the occurrence of a stitching errorn (d).
  • the first three may be referred to as imaging failure errors.
  • An incomplete OPC may be defined as an Edge Placement Error (EPE) that is larger than a predetermined value at a trench-end, when process conditions are in best dose, best focus and for a nominal mask. The process may for example be considered failed when the EPE is larger than 3nm at a trench-end in best dose, best focus and nominal mask.
  • EPE Edge Placement Error
  • a process failure may be considered based on bridging as soon as the contours come closer than a predetermined value, e.g. closer than 15nm.
  • a process failure may be established based on pinching when a trench becomes critically too narrow, e.g. having an internal width smaller than a predetermined value such as for example smaller than 35nm, in defocus, decreased dose and downsized mask.
  • the obtained results for the metric or the obtained evaluation for the metric results may be arranged so that an easy evaluation as function of different parameters such as design parameters and/or split parameters may be obtained.
  • the obtained results or evaluation thereof may be organised topologically, in order to allow easy evaluation.
  • the topologically organisation may be such that results obtained for variation of one parameter value, while others parameter values are maintained, are positioned equidistant.
  • the latter may be performed by arranging the selected data in a multi-dimensional matrix, wherein each dimension represents a different split or design parameter taken into account. This optional step will be illustrated in more detail below.
  • step 160 suitable design and split parameters are determined for the multiple patterning lithographic processing of the pattern in a single layer, taking into account the evaluation results for the at least one process condition or optionally for a plurality of process conditions.
  • design and split parameters can be selected such that a good process window is obtained for the multiple patterning lithographic processing that is to be performed.
  • the latter may be obtained by selecting design and split parameters so that upon variation of the process, design and split conditions, the obtained metric results are still sufficient.
  • determination of suitable design and split parameters may be performed by screening the matrix for success areas, i.e. for a parameter space where a sufficient or suitable lithographic process is obtained, e.g. where no error flags are obtained.
  • the obtained design and split parameters resulting in successful lithographic processing may be translated into design and split guidelines, as shown in step 170, for multiple-patterning lithographic processing of other patterns of interest.
  • the guidelines thereby may ensure a robust multiple patterning process through process variations.
  • the method furthermore comprises the optional step of arranging the obtained evaluation results or values so that an easy evaluation as function of different parameters such as design parameters and/or split parameters can be done.
  • the latter may be obtained by using each variable in one direction, thus obtaining a multidimensional representation.
  • the data thus may be arranged in a multi-dimensional matrix, wherein each dimension represents a different parameter taken into account.
  • the multidimensional matrix is visualised in a two-dimensional matrix representation.
  • the values or results for the metric are represented in a two dimensional sub-matrix as function of two variables, whereby the columns of the sub-matrix correspond with values for the first variable and the rows of the sub-matrix correspond with values for the second variable.
  • FIG. 6 An example thereof is shown in FIG. 6 , illustrating a sub-matrix indicating for example for parallel lines a result for a metric expressing a degree of stitching as function of the pitch (varied in the different columns) and of the overlap (varied in the different lines).
  • Dark squares are marked 'flagged', which means stitching or bridging failures occurred, whereas light squares are marked 'success', which means stitching was successful.
  • other variables are taken into account. For example, in order to take into account a third variable, a sub-matrix is determined for each value of the third variable and the sub-matrix are arranged and outlined in a larger row or column matrix.
  • a fourth variable can be taken into account, by determining for each value of the fourth variable that is under study a larger row or column matrix and by arranging these larger row or column matrices in the columns respectively rows of a further, larger matrix. More variables can be added in a similar way.
  • FIG. 7 illustrating a representation wherein 3 different variables are taken into account, in the present example being pitch, overlap and gap.
  • sub-matrices are represented expressing different pitch values in the different columns and expressing different stitching overlap values in the different rows.
  • Such sub-matrices are determined for different values of the gap between the features, and the sub-matrices for different gap values are arranged in a larger row matrix.
  • the metric result or an evaluation thereof can be displayed.
  • the grey filled squares represent squares wherein stitching or bridging failures occurred.
  • the white squares represent squares wherein stitching was successful.
  • a fourth variable e.g. a further split or design parameter, may be taken into account and the larger row-matrix is determined for different exposure dose /focus conditions and arranged as different rows of a larger matrix. In this way, a matrix representing the metric as function of four variables is obtained.
  • the corresponding metric result for the given value of the first and the second variable but for a different value of the third variable can then easily be found in cells that are shifted over n times the sub-matrix width, whereby n is an integer number.
  • the corresponding metric result for the given value of the first and the second variable but for a different value of the fourth variable can easily be found in cells that are shifted over m times the sub-matrix height, whereby m is an integer number. It is an advantage of embodiments according to the present invention that evaluation of metric can be obtained in an efficient way.
  • the matrix may for example represent the metric as function of pitch and stitching overlap for different split of zigzag at various gaps.
  • the metric results do not need to be determined for all cells in all sub-matrices corresponding with possible values for all variables, but that this can be user determined, based on predetermined rules, based on predetermined algorithms, based on neural networks, etc. In this way, if for example in a given sub-range for a variable no appropriate metric results are to be expected, no determination of the metric result is to be determined.
  • the type of variables used do not need to be limited to split and/or design parameters, but also may include process parameters.
  • the present invention will be illustrated based on a 45nm node half pitch random logic metal design, using two dimensional split test patterns, whereby the design and the split parameters of the split test patterns are varied systematically.
  • a set of selected representative test patterns with various critical 2D topologies was used for which density and dimensions were varied in a systematic way.
  • the splitting and cutting positions and the way to recombine (polygon overlap) were also varied.
  • large matrices with varying critical parameters were screened, leading to guidelines on best split practice and also guidelines for split compliant design.
  • the simulation methodology used was as follows. The contours of the image in resist were simulated. The target in resist was 65nm. An isotropic constant etch bias was assumed to bring trenches down to 45nm in hard-mask. After insertion of the assist features, a dense OPC (using Mentor Graphics Calibre nmOPC) was run using a non-calibrated constant threshold resist model. The default OPC settings were used. At this stage, the two patterning steps was assumed to be independent from each other. Further the image contours were simulated and compared under various process conditions (using Mentor Graphics Calibre OPCVerify). Each patterning step was first considered separately.
  • the dose and focus conditions were varied on 9 different positions in the centre and along the edge of an elliptical process window, as shown in FIG. 8 .
  • the dose was varied by ⁇ 3%; in best dose, the focus was varied by ⁇ 50nm; the dose and the focus were also varied concurrently by ⁇ 2.1% and ⁇ 35nm respectively.
  • MEEF is critical for trenches and certainly at trench-ends, a ⁇ 0.5nm mask bias variation per edge, additionally to the dose variations, was induced.
  • the OPC'ed mask polygons were upsized by 0.5nm. Similarly, the mask was down-sized when the dose was decreased.
  • a stitching overlap (overlap at mask level between the polygons from patterning 1 and patterning 2) is needed to ensure a stitching without process failure flag.
  • the contours from the two patterning steps touched each other without overlapping.
  • the trench-end pullback resulted in a gap between the two patterns to be compensated by some mask overlap.
  • a 48nm overlap was needed to compensate not only for trench-end pull back but also for trench-end rounding, in order to obtain an acceptable stitching width according to the failure-flag defined.
  • the stitching overlap needed to be increased up to 56nm in order to avoid the stitching failure. It is shown based on this example that the mask stitching overlap is mainly compensating for the variations of trench-end and shape through process variations, more than for overlay, as can be seen in FIG. 9 .
  • the trench-end process is more critical for stitching than overlay, while overlay remains critical for the pattern placement. From the example, it is also suggested that more specific OPC or resolution enhancement technique (RET) should be used to ensure better trench-end pattern fidelity.
  • RET resolution enhancement technique
  • the 102nm pitch was the last one without process failures.
  • the bridging problems occurred at larger pitch, i.e. 98nm pitch, indicating an increased lack of exposure latitude at the trench-end intended for overlap.
  • An additional issue occurred at 96nm pitch when the OPC could not be fully completed resulting in an EPE > 3nm.
  • the stitching overlap made the trench-end sub-resolution at pitches below 96nm.
  • the situation of a combined aggressive pitch and gap was also studied.
  • the pattern displayed in FIG. 16 is typical for a metal1 layer and it combines both the pitch and the gap at their minimum target of 90nm and 46nm respectively.
  • the test design is such that pitch, gap, cut position and stitching overlap are varied.
  • Each litho step of the double patterning flow targeted at 65nm trenches at a minimum pitch of 115nm to 130nm, using assist features and assuming an etch bias down to 45nm.
  • the single patterning targeted at 45nm trenches at 90nm minimum pitch, while the trenches could be retargeted as the pitch is relaxed, it did not use any assist features.
  • the pitch should be relaxed above 100nm to ensure a robust stitching. This constrains on the pitch concerned the trenches around the stitching area.
  • pitch 90nm / gap 46nm the stitching width in the middle of the parallel lines was too narrow, being already an indication for failure in detuned process.
  • Stitching was improved when relaxing the pitch up to 100nm, where very aggressive gaps ⁇ 45nm were patterned with double patterning. If the gap was relaxed to ⁇ 60nm, the stitching occurred in the middle of the turns, and the 90nm pitch was patterned using double patterning.
  • the above example illustrates that the design split problem is more than just polygon cutting and coloring.
  • the yield might decrease under a detuned process due to failing stitching.
  • the example illustrates a developed methodology to study the double patterning stitching robustness through process variations according to embodiments of the present invention. Design and split parameters of representative test patterns thereby were varied in a systematic way. Process failures due to variations in dose, focus, mask CD and overlay were defined and flagged. Based on simulations, the parameters space free of process failure flags was identified.
  • the parameter space for success was used to indicate best split practice or design guidelines to ensure a robust stitching for maintaining yield with double patterning.
  • the trench-end process pattern fidelity and position
  • RET including OPC
  • the overlay remains critical for the pattern placement, rather than for stitching.
  • a global scaling from the previous node did not allow taking full advantage of the double patterning.
  • LELE metal Litho-Etch-Litho-Etch
  • Double patterning leads to denser pitch and gaps compared to single patterning. Both benefits are not always obtainable together.
  • stitching in parallel lines should be avoided.
  • making a jog larger helps to increase the stitching quality.
  • a stitching failure in a jog can be due to an insufficient overlap or to a limited process jog length.
  • an overlap at cut positions is needed to compensate for the line-end pullback and line-end shape, even more than for the overlay error. Both simulations and experiments were used to compare the patterning of 2D split test patterns varied in a systematic way.
  • the present invention also relates to a system for optimising multiple patterning lithographic processing of a pattern in a single layer comprising a plurality of design features.
  • Such multiple patterning lithographic processing may be double patterning lithographic processing or it may comprise more than two patterning steps.
  • the multiple patterning lithographic processing thus may comprise at least a first patterning step and a second patterning step.
  • FIG. 19 an exemplary system is shown in FIG. 19 .
  • the exemplary system 300 comprises a metric determination means 310 for determining, for a plurality of processing conditions, results, e.g. values, for a metric expressing a splitting correlated process quality, e.g.
  • a stitching correlated process quality such as for example a degree of stitching between design features patterned in a first patterning step and design features patterned in a second patterning step.
  • the metric may be any process property influenced by the splitting, such as for example an electric parameter, a pattern parameter, a circuit yield, reliability, etc.
  • Such a metric advantageously may be the stitching width, as defined above.
  • the system 300 furthermore comprises an evaluation means 320 for evaluating the results for the at least one metric as function of design and/or split parameters, taking into account the process conditions. Evaluation may be performed as function taking into account a plurality of process conditions.
  • the system 300 may comprise a selection means 330 for selecting based on the evaluated results, particular design and split parameters for particular applications or for deriving guidelines for design and split in multiple patterning lithographic processes.
  • the determination, evaluation and/or selection means may be operated in an automatic and/or automated way. It may operate according to predetermine algorithms, using a look up table, using a neural network, etc.
  • the system 300 furthermore may comprise an input means 305 for receiving either test pattern in layout, or in print, or test results or simulation results, on which the determination of the metric results may be performed.
  • the system furthermore may comprise an output means 335 for putting out design parameters and/or split parameters and/or for putting out guidelines for design and/or split parameters based on the selected design and/or split parameters.
  • Other components and features may be incorporated that are adapted for performing one or more steps of the method for optimising the multiple patterning lithographic process. The same features and advantages as set out in the first aspect may be present.
  • the present invention also relates to a design comprising a set of test patterns adapted for optimising multiple patterning lithographic processing.
  • a design may for example be available in electronic format in printed format.
  • the design may be adapted for use in a method according to any of the above described method embodiments. It may be adapted for providing deriving therefrom values for at least one metric expressing a splitting correlated quality parameter, such as for example a degree of splitting, e.g. stitching, between design features patterned in a first patterning step and design features patterned in an at least second patterning step of a multiple patterning lithographic processing method.
  • test patterns may be adapted so that such values can be derived as function of design parameters and/or possible split parameters in a multiple patterning lithographic processing.
  • the test patterns may be grouped so that a plurality of test patterns is present each with a different design parameter or adapted for use with a different split parameter.
  • test patterns preferably comprise one, some or all of the following structures : a set of parallel lines, a set of lines making a corner, a set of lines making at least two corners, e.g. resulting in a zigzag structure or a jog. Further features may be as set out in the following examples, embodiments of the present invention not being limited thereto.
  • test patterns that may be used are discussed in the following examples.
  • a test pattern for use for optimising multiple patterning lithographic processing is a set of parallel lines.
  • the test pattern thereby is cut in the middle in between the parallel lines.
  • the dimensions, pitch and overlap have been varied.
  • a given set of process conditions in the present example being a numerical aperture of 1.35
  • an annular illumination in the range ⁇ out 0.92 - ⁇ in 0.72 and illumination having X/Y polarisation a splitting correlated process quality parameter has been evaluated as function of pitch and overlap. It has been found that a minimum pitch of 104nm is necessary. Varying the process parameters by using a numerical aperture of 1.20 instead of 1.35 did not result in a variation of the minimum pitch required.
  • the stitching robustness depends mainly on the line-end shape and on the relative position and the variations thereof through process variations. More particularly, one or more of the following characteristics can be taken into account : line-end pull-back for the lines patterned, corner rounding at the line-end, width at the line-end the amount of necking versus stitching overlap, etc.
  • An example of such a test pattern comprising a set of parallel lines is shown in FIG. 20 .
  • a test pattern comprises lines shaped so as to form at least two corners, combining aggressive pitch and gap.
  • the lines may for example be zigzag lines, as indicated in FIG. 21 .
  • a structure with a 110nm pitch and a gap of 66nm has been used whereby the double patterning limits with no failure through process variation is obtained.
  • the double patterning is performed for processing conditions comprising a numerical aperture of 1.35, an annular illumination of ⁇ out 0.90 - ⁇ in 0.72, an illumination having an X/Y polarisation.
  • the scaling of both the pitch and the gap is not possible in this zig-zag.
  • the design needs to be adapted to avoid over-constrained topologies, i.e. to avoid aggressive gaps next to aggressive pitch. It has been found that keeping larger gaps, and thus avoiding the need for stitching in the dense parallel trenches, allows reaching the target at 90nm pitch. Furthermore small gaps are possible at looser pitch.
  • a test pattern comprises a corner. Double patterning lithographic processing is performed using a numerical aperture of 1.5 and with annular illumination of ⁇ out 0.90 - ⁇ in 0.72 and X/Y polarisation. It has been found that the minimum pitch is limited by bridging problems due to stitching overlap in dense parallel lines. A minimum pitch of 98nm to 100nm can be obtained by increasing the gap. The corner-to-corner bridging limits the gap. An example of such a test pattern is shown in FIG. 22 .
  • a test pattern comprising a jog is studied.
  • the test pattern is tested under processing conditions of a numerical aperture of 1.35, an annular illumination of ⁇ out 0.92 - ⁇ in 0.72 and an X/Y polarisation. It has been found that for a width of 88nm and an overlap of more than 19nm and for a width of 66nm and an overlap of more than 20nm any cut is fine. When using a jog with a length around 70nm, this results in a stitching failure. Overall it has been found that enlarging the jog and ensuring minimal overlap, any cut position at any pitch is ok.
  • the cut position advantageously can be chosen so that no bridging occurs between the jog-end and the next line.
  • the jog length should not be too short but also not be between 70nm and 90nm. An example of such a test pattern is shown in FIG. 23 .
  • the present invention relates to a method for multiple patterning lithographic processing of a pattern in a single layer according to a design comprising a plurality of design features according to design parameters.
  • the method thereby comprises a step of splitting a design according to predetermined split parameters in a first set of design features and in a second set of design features and performing a first patterning step for the first set of pattern features and a second patterning step for the second set of design features, whereby the predetermined split parameters and the design parameters are determined using a method according to a method for optimising as described in the first aspect.
  • the present invention relates to a set of masks for multiple patterning lithographic processing of a pattern in a single layer.
  • the set of masks thereby comprise a first mask comprising a first set of design features of the design to be patterned in the pattern and a second mask comprising a second set of design features of the design to be patterned in the pattern, whereby the masks are made according to predetermined split and design parameters obtained using a method for optimising as set out in the first aspect.
  • Fig. 24 shows one configuration of processing system 900 that includes at least one programmable processor 903 coupled to a memory subsystem 905 that includes at least one form of memory, e.g., RAM, ROM, and so forth.
  • the processor 903 or processors may be a general purpose, or a special purpose processor, and may be for inclusion in a device, e.g., a chip that has other components that perform other functions.
  • one or more aspects of the present invention can be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them.
  • the processing system may include a storage subsystem 907 that has at least one disk drive and/or CD-ROM drive and/or DVD drive.
  • a display system, a keyboard, and a pointing device may be included as part of a user interface subsystem 909 to provide for a user to manually input information. Ports for inputting and outputting data also may be included. More elements such as network connections, interfaces to various devices, and so forth, may be included, but are not illustrated in Fig. 24 .
  • the various elements of the processing system 900 may be coupled in various ways, including via a bus subsystem 913 shown in Fig. 24 for simplicity as a single bus, but will be understood to those in the art to include a system of at least one bus.
  • the memory of the memory subsystem 905 may at some time hold part or all (in either case shown as 911) of a set of instructions that when executed on the processing system 900 implement the steps of the method embodiments described herein.
  • a processing system 900 such as shown in Fig. 24 is prior art
  • a system that includes the instructions to implement aspects of the methods for optimising multiple patterning lithographic processing of a pattern in a single layer is not prior art, and therefore Fig. 24 is not labelled as prior art.
  • the present invention also includes a computer program product which provides the functionality of any of the methods according to the present invention when executed on a computing device.
  • Such computer program product can be tangibly embodied in a carrier medium carrying machine-readable code for execution by a programmable processor.
  • the present invention thus relates to a carrier medium carrying a computer program product that, when executed on computing means, provides instructions for executing any of the methods as described above.
  • carrier medium refers to any medium that participates in providing instructions to a processor for execution. Such a medium may take many forms, including but not limited to, non-volatile media, and transmission media.
  • Non volatile media includes, for example, optical or magnetic disks, such as a storage device which is part of mass storage.
  • Computer readable media include, a CD-ROM, a DVD, a flexible disk or floppy disk, a tape, a memory chip or cartridge or any other medium from which a computer can read.
  • Various forms of computer readable media may be involved in carrying one or more sequences of one or more instructions to a processor for execution.
  • the computer program product can also be transmitted via a carrier wave in a network, such as a LAN, a WAN or the Internet.
  • Transmission media can take the form of acoustic or light waves, such as those generated during radio wave and infrared data communications. Transmission media include coaxial cables, copper wire and fibre optics, including the wires that comprise a bus within a computer.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
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US12/390,377 US20090217224A1 (en) 2008-02-22 2009-02-20 Method and system for mask design for double patterning
JP2009038912A JP2009200499A (ja) 2008-02-22 2009-02-23 二重パターニングのための分割および設計指針

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