Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/06—Receivers
  • H04B1/08—Constructional details, e.g. cabinet
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04W—WIRELESS COMMUNICATION NETWORKS
  • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
  • H04W88/08—Access point devices
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/14—Structural association of two or more printed circuits
  • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K9/00—Screening of apparatus or components against electric or magnetic fields
  • H05K9/0007—Casings
  • H05K9/002—Casings with localised screening
  • H05K9/0022—Casings with localised screening of components mounted on printed circuit boards [PCB]
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0237—High frequency adaptations
  • H05K1/0243—Printed circuits associated with mounted high frequency components
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09009—Substrate related
  • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10227—Other objects, e.g. metallic pieces
  • H05K2201/10371—Shields or metal cases

Definitions

• the present invention relates to a module adapted for use on the front end of a picocell or microcell base station including a printed circuit board having a plurality of discrete electrical components mounted directly thereto and adapted to allow for the reception of cellular signals between the antenna of the picocell or microcell on one end and the respective output pad on the motherboard of the picocell or microcell at the other end.
• FIGURE 1 is a simplified block diagram depicting the flow of cellular signals through the various RF components defining the front-end Rx module of the present invention
• FIGURE 2 is an enlarged perspective view of a front-end Rx module in accordance with the present invention.
• FIGURE 3 is an enlarged top plan view of the front-end Rx module with the lid removed therefrom;
• FIGURES 4A and 4B are perspective top and bottom views respectively of the lid of the front-end Rx module of the present invention
• FIGURE 5 is an enlarged bottom plan view of the front-end Rx module of the present invention
• Module 20 is adapted to replace (and/or complement depending upon the desired application as disclosed in more detail below) the RF Rx components used in the Rx path of a UMTS Node B local area front end.
• Module 20 is compliant with TS25.104 R6 standards and allows customers to select different values for receiver sensitivity, selectivity, and output power.
• module 20 is RoHS compliant and lead-free.
• Duplexer 34 is, of course, adapted and structured as known in the art to allow the passage of the Rx signal clockwise in the direction of the Rx LPF (low pass) filter 36.
• Rx low pass filter 36 is adapted and structured to reduce the harmonics of the duplexer 34, ensuring that any spurious responses up to 12.75 GHz are attenuated to -30 dB or better.
• the Rx signal may optionally be passed through a 3 dB attenuator pad 37 (comprised of discrete resistors R5, R6, and R8 as described in more detail below), and then through a LNA (low noise amplifier) 39.
• Low noise amplifier 39 is coupled to VLNA (LNA supply voltage) pin #9 and LNA (low noise amplifier) gain select pin #10.
• the LNA has a noise figure of 1.3 dB and a gain of 14 dB typical, or in bypass mode; 4.3 dB NF and -3 dB gain typical.
• the LNA is very linear and is designed to work within the distributed duplexer architecture.
• Filter 40 additionally serves the function of providing the close-in blocking needed in order to be compliant with the TS25.104 R6 Standard.
• One of the most difficult aspects of the TS25.104 R6 standard is a blocking requirement that leads to a front-end attenuation of 15 dB to 20 dB at 1.9 GHz and 2 GHz.
• Module 20 initially comprises a printed circuit board or substrate 22 which, in the embodiment shown, is preferably made of four layers of GETEK® or the like dielectric material and is about 1 mm (i.e., .040 inches) in thickness. Predetermined regions of the substrate 22 are covered with copper or the like material and solder mask material, both of which have been applied thereto and/or selectively removed therefrom as is known in the art to create the various copper, dielectric, and solder mask regions on the substrate 22.
• the metallization system is preferably ENlG, electroless nickel/immersion gold over copper.
• Each of the side edges 46 and 48 defines a pair of spaced-apart metallized castellations 37 which are diametrically opposed from one another.
• Each castellation 37 is defined by an extended or elongated oval- shaped groove which has been carved out of each of the respective substrate side edges 46 and 48 respectively. All of the castellations are located above copper line or strip 47.
• the outer surface of each of the respective castellations 35 and 37 is coated as by electroplating or the like, with a layer of copper or the like conductive material which is initially applied to all of the surfaces of the substrate 22 during the manufacturing of the substrate 22 as is known in the art and then removed from selected portions of the surfaces to define the copper coated castellations 35 and 37.
• Castellations 35 and 37 and, more specifically, the copper thereon creates an electrical path between top surface 23 and bottom surface 27 of substrate 22.
• Corner strip 37c on the left side of substrate 22 is spaced from the strip 35a of castellation 35 defining the LNA gain select pin #10.
• a strip 37e (FIGURE 3) of copper or the like material extends between and electrically connects the castellation 35 extending along the left side substrate edge 48 to the upper castellation 37 also extending along the left side substrate edge 48.
• FIG. 3 Another short strip 37h (FIGURE 3) of copper or the like material extends along the top peripheral substrate edge 42 between and in spaced, non- contacting, relationship with the castellation 35 defining VLNA pin #9 and the castellation 35 defining LNA gain select pin #10 also extending along the top peripheral substrate edge 42.
• each of the vias 38 are surrounded by regions 38a (FIGURES 3 and 8) of dielectric substrate material, i.e., areas of the substrate 22 from which the conductive copper material has been removed as by an etching, lasing or the like process known in the art.
• Duplexer 34, Rx low pass filter 36, Rx bandpass filter 40, and Rx low noise amplifier 39 are all mounted on an area of the top surface of the board 22 above the elongate copper strip 47 and thus intended to be covered by the lid 45. More specifically, and as shown in FIGURE 3, Rx bandpass filter 40 is located in the upper right hand corner of the board 22 and extends generally longitudinally in a relationship adjacent and parallel to the top longitudinal edge 42 of board 22. Rx O/P pin #6 is located adjacent the side board edge 46 generally opposite the right end face of filter 40. Ground pin #s 7 and 8 are located along the top edge 42 in an orientation generally opposite the longitudinal top edge of filter 40.
• GND (ground) pin #1 , N/C (no connection) pin #2 and N/C (no connection) pin #3 are respectively located along the lower longitudinal edge 44 of the board 22 in spaced-apart relationship from left to right.
• Tx I/P (transmit input) pin #4, GND (ground) pin #5, and Rx C7P (receive output) pin #6 are respectively located along the right side elongate edge 46 of board 22 in a spaced-apart relationship from bottom to top.
• N/C (no connection) pin #4 is located below copper strip 47.
• the Rx O/P pin #6 and N/C (no connection) pin #4 are located above copper strip 47 and are defined by the respective vias 38 described above, while ground pin #5 is defined by one of the castellations 35.
• a castellation 37 is defined in edge 46 between strip 47 and castellation 35 defining pin #5.
• Another castellation 37 is defined in edge 46 between the via 38 defining the pin #6 and the top substrate edge 42.
• Duplexer 34 which is preferably of a ceramic monoblock construction providing an insertion loss of about 1.3 dB on the receive side, is located and positioned on the top surface of the board 22 in a relationship generally adjacent and parallel to the left side edge 48 of board 22 and above and parallel to the copper strip 47.
• RF antenna pin #12 is located adjacent board edge 48 in a relationship and position generally opposite the duplexer 34.
• Rx low noise amplifier 39 is located generally in the upper left hand corner of the board 22 to the left of, and spaced from, the Rx bandpass filter 40 and above and spaced from the duplexer 34 in a relationship adjacent to and spaced from the left side edge 48 of board 22.
• lid 45 includes a top wall or roof 46, a pair of upper and lower walls 49a and 49b, respectively, and a pair of sidewalls 51a and 51b, respectively, depending generally perpendicularly downwardly therefrom.
• the walls 49a, 49b, 51a and 51b in turn define lower longitudinal edges 53.
• each of the sidewalls 51a and 51b in turn defines at least two spaced-apart tabs 50 projecting downwardly therefrom and adapted to be fitted into the respective through-slots or castellations 37 for locating and securing the lid 45 to the board 22 in a grounded relationship with the board 22 wherein the lower longitudinal edge 53 of the respective lid walls 49a, 49b, 51a and 51b are seated over copper strip 47, the copper pads 35a of castellations 35, the copper pads 37a of castellations 37, and the copper strips 37c, 37e, 37f, 37h and 37g thus providing a grounded lid 45.
• Rx low pass filter 36 includes two output circuit lines 60 and 61 extending from output terminals #4 and #1 thereof respectively.
• the output line 60 connects the output terminal #4 of filter 36 to ground pin #11.
• Circuit line 60 is also connected to ground via circuit line 62 which is connected to circuit line 60 at node N1.
• Node N1 is located on circuit line 60 between the output terminal #4 of Rx low pass filter 36 and ground pin #11.
• the output line 61 extends between the output terminal #1 of filter 36 and the input terminal #3 of amplifier 39 (U2).
• the Rx signal passes through circuit line 61 and through the resistors R5, R6, and R8 comprising the optional attenuator pad 37.
• R6 extends along circuit line 61.
• R5 extends between a node N1a and ground on a circuit line 61a located above resistor R6, while resistor R8 extends on a circuit line 61b extending between node N1 b and ground below resistor R6.
• An inductor L7 extends on a circuit line 61c extending between a node N1c and ground below resistor R8.
• a capacitor C14 is located on line 61 between R6 and input terminal #3 of low noise amplifier 39.
• Node N1c is located on circuit line 61 between capacitor C14 and node N1b.
• Node N3 is located on circuit line 63 between the input terminal #1 of low noise amplifier 39 and node N4.
• Node N4 is located on circuit line 63 between node N3 and resistor R2.
• Resistor R2 is located on circuit line 63 between nodes N4 and a node N5.
• Node N5 is located on circuit line 63 between resistor R2 and VLNA pin #9.
• Inductor L1 is located on circuit line 70 between nodes N6 and N7.
• Node N9 is located on circuit line 72 between inductor L4 and capacitor C16.
• Node N5 is located on circuit line 63 between resistor R2 and VLNA pin #9.
• a capacitor C15 is connected between a node N10 on circuit line 74 and ground.
• Node N10 is located on circuit line 74 between node N9 and resistor R4.
• selected regions on the board 22 comprise regions of substrate dielectric material; that other selected regions on the board 22 comprise regions of the board wherein the copper material has been covered with solder mask material; and further that still other selected ones of the regions comprise regions of exposed copper material.
• printed circuit board 22 has a plurality of differently sized and shaped connection copper pads (not shown) located below the Rx bandpass filter 40, low noise amplifier 39, low pass filter 36, and duplexer 34 so as to allow the same to be direct surface solder mounted to the board 22.
• Differently sized and shaped copper connection pads (not shown) are also appropriately positioned below each of the resistors and capacitors comprising the circuit of module 20.
• Board 22 still further defines at least one aperture 150 defining a through-way for a screw or the like (not shown) adapted to allow the module 20 to be secured to the heat sink and a customer's motherboard to allow better thermal contact between the motherboard and module 20.
• aperture 150 is located below copper strip 47 and to the left of power amplifier 26.
• the present invention encompasses the embodiment wherein the module 20 has been manufactured such that it does not include the portion of the printed circuit board 22 extending below the copper strip 47 and comprising and defining the unused/unconnected Tx (transmit) section of module 20.
• the lower board edge 42 would be located adjacent the strip 47.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Structure Of Printed Boards (AREA)
• Transceivers (AREA)
• Filters And Equalizers (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=38624391

Family Applications (1)

Country Status (4)

Families Citing this family (1)

Family Cites Families (4)

• 2007
  • 2007-06-28 EP EP07810003A patent/EP2050197A1/en not_active Withdrawn
  • 2007-06-28 CN CNA2007800254453A patent/CN101485098A/zh active Pending
  • 2007-06-28 WO PCT/US2007/015031 patent/WO2008008193A1/en active Application Filing
  • 2007-06-28 KR KR1020097000225A patent/KR20090033435A/ko not_active Application Discontinuation

Non-Patent Citations (1)

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