EP1990732A4 - Einrichtung, verfahren und programm zur lru-steuerung - Google Patents

Einrichtung, verfahren und programm zur lru-steuerung

Info

Publication number
EP1990732A4
EP1990732A4 EP06714757A EP06714757A EP1990732A4 EP 1990732 A4 EP1990732 A4 EP 1990732A4 EP 06714757 A EP06714757 A EP 06714757A EP 06714757 A EP06714757 A EP 06714757A EP 1990732 A4 EP1990732 A4 EP 1990732A4
Authority
EP
European Patent Office
Prior art keywords
lru control
lru
control device
program
control method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06714757A
Other languages
English (en)
French (fr)
Other versions
EP1990732A1 (de
Inventor
Tomoyuki Okawa
Hiroyuki Kojima
Masaki Ukai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP1990732A1 publication Critical patent/EP1990732A1/de
Publication of EP1990732A4 publication Critical patent/EP1990732A4/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G06F12/125—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list being generated by decoding an array or storage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
EP06714757A 2006-02-27 2006-02-27 Einrichtung, verfahren und programm zur lru-steuerung Withdrawn EP1990732A4 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/303620 WO2007097028A1 (ja) 2006-02-27 2006-02-27 Ｌｒｕ制御装置、ｌｒｕ制御方法およびｌｒｕ制御プログラム

Publications (2)

Publication Number Publication Date
EP1990732A1 EP1990732A1 (de) 2008-11-12
EP1990732A4 true EP1990732A4 (de) 2009-09-02

Family

ID=38437087

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06714757A Withdrawn EP1990732A4 (de) 2006-02-27 2006-02-27 Einrichtung, verfahren und programm zur lru-steuerung

Country Status (4)

Country Link
US (1) US8065496B2 (de)
EP (1) EP1990732A4 (de)
JP (1) JP4369524B2 (de)
WO (1) WO2007097028A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5534912B2 (ja) * 2010-04-13 2014-07-02 三菱電機株式会社 データ記憶装置
US8468536B2 (en) * 2010-06-24 2013-06-18 International Business Machines Corporation Multiple level linked LRU priority
JP5627521B2 (ja) * 2011-03-24 2014-11-19 株式会社東芝 キャッシュシステムおよび処理装置
US10635806B2 (en) * 2017-05-04 2020-04-28 Crowdstrike, Inc. Least recently used (LRU)-based event suppression
US10838659B2 (en) 2019-02-08 2020-11-17 International Business Machines Corporation Controlling write access to a memory structure based on write request priority

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0073666A2 (de) * 1981-08-27 1983-03-09 Fujitsu Limited Fehlerverarbeitungssystem für Pufferspeicher
JPH01314359A (ja) * 1988-06-14 1989-12-19 Mitsubishi Electric Corp 最優劣決定回路
JPH06332801A (ja) * 1993-05-11 1994-12-02 Internatl Business Mach Corp <Ibm> 完全統合型キャッシュ・アーキテクチャ

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2541528B2 (ja) 1986-12-26 1996-10-09 日本電気株式会社 Ｌｒｕエラ−処理方式
JPH01154265A (ja) 1987-12-10 1989-06-16 Fujitsu Ltd キャシュ更新障害監視回路
US5140690A (en) 1988-06-14 1992-08-18 Mitsubishi Denki Kabushiki Kaisha Least-recently-used circuit
JPH0264832A (ja) 1988-08-31 1990-03-05 Nec Corp ディスク・キャッシュ・メモリ管理装置
US5249286A (en) * 1990-05-29 1993-09-28 National Semiconductor Corporation Selectively locking memory locations within a microprocessor's on-chip cache
US5353425A (en) * 1992-04-29 1994-10-04 Sun Microsystems, Inc. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature
JPH09288617A (ja) 1996-04-19 1997-11-04 Nec Corp Ｌｒｕ制御方式
US6134636A (en) * 1997-12-31 2000-10-17 Intel Corporation Method and apparatus for storing data in a memory array
US6202129B1 (en) * 1998-03-31 2001-03-13 Intel Corporation Shared cache structure for temporal and non-temporal information using indicative bits
JP3279253B2 (ja) 1998-05-27 2002-04-30 日本電気株式会社 キャッシュページの管理方法およびキャッシュページの管理プログラムを記憶した媒体
US6490666B1 (en) * 1999-08-20 2002-12-03 Microsoft Corporation Buffering data in a hierarchical data storage environment
JP2003131946A (ja) * 2001-10-19 2003-05-09 Nec Corp キャッシュメモリ制御装置及び方法
US20070118695A1 (en) * 2005-11-18 2007-05-24 International Business Machines Corporation Decoupling storage controller cache read replacement from write retirement

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0073666A2 (de) * 1981-08-27 1983-03-09 Fujitsu Limited Fehlerverarbeitungssystem für Pufferspeicher
JPS5845682A (ja) * 1981-08-27 1983-03-16 Fujitsu Ltd Ｌｒｕエラ−処理方式
JPH01314359A (ja) * 1988-06-14 1989-12-19 Mitsubishi Electric Corp 最優劣決定回路
DE3918453A1 (de) * 1988-06-14 1989-12-21 Mitsubishi Electric Corp Lru-schaltung
JPH06332801A (ja) * 1993-05-11 1994-12-02 Internatl Business Mach Corp <Ibm> 完全統合型キャッシュ・アーキテクチャ
US5640339A (en) * 1993-05-11 1997-06-17 International Business Machines Corporation Cache memory including master and local word lines coupled to memory cells

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2007097028A1 *

Also Published As

Publication number Publication date
JP4369524B2 (ja) 2009-11-25
US8065496B2 (en) 2011-11-22
JPWO2007097028A1 (ja) 2009-07-09
EP1990732A1 (de) 2008-11-12
US20080320256A1 (en) 2008-12-25
WO2007097028A1 (ja) 2007-08-30

Similar Documents

Publication Publication Date Title
EP2101313A4 (de) Anzeigesteuereinrichtung, anzeigesteuerverfahren und programm
EP2141567A4 (de) Elektronische vorrichtung, steuerungsverfahren und programm
EP1990727A4 (de) Cache-steuervorrichtung und cache-steuerprogramm
EP2071468A4 (de) Speichersteuerungsvorrichtung, speichervorrichtung und speichersteuerungsverfahren
EP1906226A4 (de) Anzeigeeinrichtung, anzeigesteuerverfahren und programm
EP2058983A4 (de) Vorrichtung, verfahren und programm zur netzsteuerung
EP2071251A4 (de) Klimaanlagensteuerungszwischenvorrichtung, klimaanlagensteuerungssystem, klimaanlagensteuerungsverfahren und klimaanlagensteuerungsprogramm
EP2058941A4 (de) Motorsteuervorrichtung, -steuerverfahren und -steuerprogramm
EP1981261A4 (de) Abbildungsvorrichtung, anzeigesteuerverfahren und programm
EP2159702A4 (de) Cache-steuereinrichtung und steuerverfahren
EP2157507A4 (de) Multiprozessoren-steuerungsvorrichtung, multiprozessoren-steuerungsverfahren und multiprozessoren-steuerungsschaltung
EP2153935A4 (de) Programmerzeugungsvorrichtung, numerische steuervorrichtung und programmerzeugungsverfahren
EP1874042A4 (de) Bilderzeugungsvorrichtung sowie verfahren und programm zu ihrer steuerung
EP1988709A4 (de) Anzeigesteuereinrichtung, anzeigesteuerverfahren und anzeigesteuerprogramm
EP2040481A4 (de) Weiterleitungssteuerungsvorrichtung, -verfahren und -programm
EP1983760A4 (de) Codierungseinrichtung, codierungsverfahren und programm
EP2045770A4 (de) Qualitätskontrollsystem, qualitätskontrollprogramm und client-einrichtung
EP2187333A4 (de) Elektronische einrichtung, passwortsteuerverfahren und programm
EP2048811A4 (de) Verschlüsselungseinrichtung, programm und verfahren
EP2096579A4 (de) Anzeigeanordnung, anzeigeverfahren und programm
EP2055360A4 (de) Spielsteuerprogramm, spielsteuerverfahren und spielvorrichtung
GB0901245D0 (en) System managing program, system managing device and system managing method
TWI371302B (en) Game program, game device, and game control method
EP1908504A4 (de) Spielsystem, steuerverfahren dafür, spielvorrichtung und programm
EP2051528A4 (de) Ausgabevorrichtung, ausgabeverfahren, ausgabeprogramm und ausgabesystem

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20080820

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB

DAX Request for extension of the european patent (deleted)
RBV Designated contracting states (corrected)

Designated state(s): DE FR GB

A4 Supplementary search report drawn up and despatched

Effective date: 20090805

17Q First examination report despatched

Effective date: 20131218

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20160803