Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
  • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
  • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses

Definitions

• the present invention relates to a wired logic binary frequency divider receiving a determined frequency input signal and providing an output signal having a frequency lower than the input frequency.
• the hard-wired logic frequency divisors have the advantage of their simple structure, which is inexpensive to implement and occupies a small area of silicon.
• the counterpart of this simplicity is that they have various limitations.
• the period of the output signal they provide can be incremented only by a constant value equal to the period of the input signal applied to them.
• the duty cycle of the output signal is not quite constant and is a function of the value of a division setpoint applied thereto.
• Fig. 1A shows the conventional structure of a DIVF1 binary frequency divider.
• the divider is arranged here to provide an output signal having a duty cycle of 0.5 and operates in 4 bits. It comprises a CMPT binary counter, a divider DIV2, two synchronous comparators CP1, CP2 and an asynchronous RS1 RS type flip-flop.
• the counter CMPT is clocked by a frequency input signal CK0 FO and provides a count value VAL which is incremented at each rising edge of the signal CKO.
• the count value VAL is applied to an input of each comparator CP1, CP2.
• the comparator CP1 receives on a second input a threshold value REF1 and the comparator CP2 receives on a second input a threshold value REF2.
• the threshold value REF1 is equal to B1 / 2 and is provided by divider DIV2 from the setpoint B1.
• the threshold value REF2 is equal to the setpoint B1.
• the divider DIV2 is an asynchronous shift circuit which performs a division by 2 of the instruction B1 by shifting the bits b3, b2, b1, b1, of the setpoint without transfer after the comma, so that the rounding error on the threshold value REF1 is equal to 1 for an odd number and is equal to 0 for an even number.
• the comparator CP1 provides a control signal DET1 synchronized with the falling edges of the signal CKO and the comparator CP2 provides a control signal DET2 also synchronized with the falling edges of the signal CKO.
• the signal DET1 is applied to the input R of the flip-flop RS1 (reset input) and the signal DET2 applied to the input S of the flip-flop RS1 (setting input 1).
• the signal DET2 is applied to an input IN1 of the counter CMPT as a reset signal to 1 of the counter.
• FIG. 2 represents the form of the signals CK2, DET1, DET2 and the counting value VAL as a function of the input signal, for a setpoint B1 equal to 8 (ie 1000 in binary).
• the signal CK2 goes to 0 when the control signal DET1 goes to 1 and goes to 1 when the control signal DET2 goes to 1, in synchronization with the falling edges of the signal CKO, while the reset to 1 of the count value intervenes on rising edge of the signal CKO, as its incrementation.
• the division by 2 of an odd value without postponement after the comma gives the same result as the division by 2 of the previous pair value. For example, the division of 4 (0100) gives 2
• the accuracy of the duty cycle is therefore a function of the period TO of the input signal CKO and of the division setpoint.
• the pitch of the period T2 of the output signal CK2 (minimum increment) is equal to the period TO of the input signal. Indeed, if the reference B1 changes from a value B to a value B + 1, the period T2 of the output signal CK2 goes from B * T0 to (B + 1) * T0 is B * T0 + T0.
• the corresponding frequency step equal to F0 / B 2 + B, is also dependent on the input frequency FO, although it is nonlinear and depends on the value B of the instruction B1.
• the power consumption of such a divider increases proportionally with the input frequency FO, it is desirable, in practice, to choose an FO frequency which is as low as possible for an output frequency F 2 which is generally determined by a specification.
• the minimum frequency FO to be applied to the input of the divider is determined according to the characteristics of the output signal CK2.
• a step of 200 ns for the period of the output signal thus imposes a TO period of the input signal of 200 ns, ie a FO input frequency of 5 MHz (1 / T0).
• the minimum period T2 of 1.2 microseconds corresponds to a frequency F2 of 833 KHz and imposes a division setpoint equal to 6.
• the maximum error on the duty cycle, for the setpoint of The odd value closest to 6, or 7, is half a period of the input signal over a total of seven periods, an error of 7% falling within the tolerance range defined by the specification.
• a FO input frequency of 5 MHz is a very high frequency involving a considerable electrical consumption, not very compatible with an application to a passive transponder which is powered electrically from an ambient electric field emitted by a reader. contactless integrated circuit.
• the present invention is directed to a binary frequency division method and a binary frequency divider structure that allows the input frequency to be decreased without loss of precision with respect to the fineness of the frequency step and the error in the frequency. cyclical report.
• This object is achieved by providing a method for dividing the frequency of an input signal and providing an output signal having a frequency lower than the input frequency, comprising the steps of: defining a division instruction , define a first threshold value and a second threshold value which are a function of the division setpoint, increment a count value at the rate of the input signal, compare the count value with the first threshold value and with the second threshold value and produce, in synchronization with fronts of variation of a first type of the input signal, a first control signal and a second control signal, the method further comprising the steps of generating at least a third control signal shifted by half a period of input to one of the first or second control signals, and outputting the output signal from selected control signals as a function of the value of at least one least significant bit of the division setpoint, so as to adjust the period of the output signal or the duty cycle of the output signal with an accuracy at least equal to the half-period of the input signal.
• the method comprises the steps of producing a third control signal shifted by half a period of the input signal from the first control signal, producing a fourth control signal shifted by one half -period of the input signal with respect to the second control signal, producing a fifth frequency control signal equal to half the frequency of the output signal, and generating the output signal from control signals selected from the four control signals as a function of the value of at least two least significant bits of the division setpoint and the value of the fifth control signal.
• the method comprises a step of cyclically resetting the count value to 0 or 1 as a function of the value of the least significant bits of the division setpoint and the value of the fifth control signal.
• the output signal is controlled by means of an asynchronous wired logic circuit receiving as input the five control signals and at least the least significant bit of the division setpoint, and providing set to 0 and set the output signal.
• the frequency of the output signal is equal to the frequency of the input signal divided by the division instruction and multiplied by two
• the first threshold value is equal to the result of the binary division by 4 of the division setpoint, without carryover after the decimal point
• the second threshold value is equal to the result of the binary division by 2 of the division setpoint, without postponement after the decimal point.
• the frequency of the output signal is equal to the frequency of the input signal divided by the division setpoint
• the first threshold value is equal to the result of the binary division by 2 of the division setpoint, without postponement after the comma
• the second threshold value is equal to the division setpoint
• the invention also relates to a wired logic binary frequency divider, receiving an input signal having a determined frequency and providing an output signal having a frequency lower than the input frequency, and having an input for receiving a setpoint of division, a counter clocked by the input signal, containing a count value, - means for providing a first and a second threshold value as a function of the division setpoint, means for comparing the count value with the first and second threshold values and providing first and second synchronized control signals with variation edges of a first type of the input signal, means for providing at least a third control signal shifted by half a period of the signal input to one of the first or second control signals, and control means for generating the output signal from co signals. control selected according to the value of at least one least significant bit of the division setpoint, such that the step of the period of the output signal or the ratio cyclic output signal can be adjusted with a precision at least equal to the half-period of the input signal.
• the divider comprises means for providing a third control signal shifted by half a period of the input signal with respect to the first control signal, means for providing a fourth control signal shifted by a half-period of the input signal with respect to the second control signal, means for producing a fifth frequency control signal equal to half of the output signal frequency, and the control means are arranged to generate the output signal from control signals selected from the four control signals as a function of the value of at least two least significant bits of the division setpoint and the value of the fifth control signal.
• control means provide signals for cyclically resetting the counter with a count value equal to 0 or equal to 1 as a function of the value of the least significant bits of the division setpoint and the value fifth control signal.
• control means comprise an asynchronous wired logic circuit receiving as input the five control signals and at least the least significant bit of the division setpoint, and providing setting signals of 0 and set the output signal.
• the divider comprises a first bit divider for providing the first threshold value from the division setpoint, a second binary divider for providing the second threshold value from the division setpoint, a first comparator.
• the frequency of the output signal is equal to the frequency of the input signal divided by the division instruction and multiplied by two
• the first threshold value is equal to the result of the binary division by 4 of the division setpoint without carryover after the decimal point
• the second threshold value is equal to the result of the binary division by 2 of the division setpoint without carryover after the decimal point.
• the frequency of the output signal is equal to the frequency of the input signal divided by the division setpoint
• the first threshold value is equal to the result of the binary division by 2 of the division setpoint, without postponement after the comma
• the second threshold value is equal to the division setpoint
• the invention also relates to an integrated circuit, in particular a passive transponder, comprising a divider according to the invention.
• the input signal of the divisor is an internal clock signal
• the divisor is arranged to provide an output signal whose frequency is equal to the input frequency divided by the division setpoint and multiplied by two
• the division setpoint is provided by a counting circuit of the number of periods of the clock signal internally occurring during the duration of an external event, divided by a predetermined value.
• FIGS. 1A and 1B respectively represent a conventional binary frequency divider and an embodiment detail of a divider element
• FIG. 2 is a timing diagram representing signals or binary values appearing in the frequency divider of FIG. IA
• FIG. 3 represents a binary frequency divider according to the invention
• FIG. 4 is a more detailed view of the structure of certain elements present in the frequency divider according to the invention.
• FIG. 5 is a truth table describing the operation of a logic control block present in the frequency divider according to the invention
• FIG. 6 is a timing diagram representing signals or binary values appearing in the frequency divider according to FIG. 1, the invention schematically represents the structure of a UHF transponder, and
• FIG. 8 represents a clock synchronization circuit present in the transponder of FIG. 7 and comprising a frequency divider according to the invention.
• a first technical limitation of a conventional binary divider as represented in FIG. 1A is imposed by the need to synchronize the steps of incrementation of the count value VAL and the steps of production of the control signals DET1, DET2. For this reason, the count value VAL is incremented on the rising edge of the input signal CKO while the control signals DET1, DET2 are provided on the falling edge of the signal CKO (or vice versa).
• the output signal CK2 is generated from the control signals DET1, DET2, the variations of the output signal (rising edges and falling edges) are necessarily synchronized on edges of the same type of the input signal, here descending fronts. As a result, the duty cycle of the output signal CK2 and the period T2 of the output signal CK2 can not be adjusted with an accuracy better than the period TO of the input signal CKO.
• a frequency divider receiving an input signal CK1 of frequency F1 and supplying an output signal CK2 of frequency F2 by using additional control signals which are shifted by one. half-period of the input signal with respect to the conventional control signals DET1, DET2.
• the output signal CK2 is generated using both the additional control signals and the control signals DET1, DET2.
• the second possibility, forming the second aspect of the invention is very advantageous in applications where the electrical consumption of the divider must be reduced.
• the step dT of the period T2 of the output signal generally fixed by a specification, imposes in a conventional divider a minimum frequency equal to 1 / dT at the input of the divider .
• the output frequency F2 is equal to 2F1 / B instead of Fl / B
• the step dT then imposes a minimum input frequency equal to 1/2 * dT, which is half the minimum input frequency of a classic divider.
• the divider can therefore be clocked by an input signal whose frequency is divided by two, for an identical output signal.
• FIG. 3 shows the structure of a DIVF2 frequency divider implementing both aspects of the invention.
• the divider DIVF2 comprises a counter CMPT clocked by an input signal CK1 of frequency F1, two synchronous logic comparators CP1, CP2 and an asynchronous RS1 RS type flip-flop whose output Q supplies a signal CK2 of frequency F2 forming the output signal of the divisor.
• the count value VAL present in the counter CMPT here of four bits, is applied to an input of the comparator CP1 and to an input of the comparator CP2.
• the comparator CP1 receives on a second input a threshold value REF1 and the comparator CP2 receives on a second input a threshold value REF2, the threshold values being also coded on four bits.
• the comparator CP1 provides a control signal DET1 and the Comparator CP2 provides a control signal DET2.
• the signals DET1, DET2 are synchronized here with the falling edges of the input signal CK1 while the counting value VAL is incremented in synchronization with the rising edges of the signal CK1.
• the frequency divider comprises a synchronous block FFB providing two additional control signals SDET1, SDET2.
• the signal SDET1 is shifted by half a period of the signal CK1 with respect to the signal DET1 and the signal SDET2 is shifted by half a period of the signal CK1 with respect to the signal DET2.
• the signals DET1, DET2, SDET1 and SDET2 are applied to an asynchronous logic block ALCT which generates, from these signals, signals SET and RST.
• the signal SET is applied to the input S of the flip-flop RS1 as a setting signal, while the signal RST is applied to the input R of the flip-flop RS1 as a reset signal.
• the signal SET thus makes it possible to set the output signal CK2 (rising edge) to 1 and the signal RST to set it to 0 (falling edge).
• the logic circuit ALCT can thus adjust the rising edges of the output signal CK2 with a precision of half a period of the input signal CK1. Similarly, it can adjust the falling edges of the output signal CK2 with a half-period accuracy of the signal CK1.
• the divisor also includes a DIV4 bit divider performing a division by 4 without carry over after the decimal point, and a divider DIV2 dividing by 2 without carry over after the decimal point.
• the FFB block supplies a phase signal PH to the logic block ALCT and the logic block ALCT applies to the counter CMPT two separate STO, ST1 reset signals.
• the signal STO makes it possible to reinitialize the counter with the value 0 (ie 0000 in binary) and the signal STl makes it possible to reinitialize the counter with the value 1 (0001 in binary).
• the logical block ALCT also receives the last two bits b1 of the B2 division setpoint, which it uses to generate the SET, RST, STO and ST1 signals in a manner described in Table 1 below as well as in FIG.
• the divisor DIV4 receives the division setpoint B2 and makes two offsets on the right, by switching the bits b3, b2 of the setpoint B2 to the bits b1, b0 of the result B2 / 4, while setting to 0 the bits b3, b2 of the result.
• the divider DIV2 thus provides the value B2 / 4 with a rounding error relating to the two low-order bits of the setpoint B1.
• the result B2 / 4 is applied to the comparator CP1 as a threshold value REF1.
• Divider DIV2 whose structure is represented in FIG. 1B, also receives setpoint B2 and performs a right shift of bits b3, b2, b1 of setpoint B2, setting bit b4 of result B2 / 2 to 0.
• the divider DIV2 thus provides the value B2 / 2 with a rounding error relating to the least significant bit of the division setpoint.
• FIG. 4 represents an exemplary embodiment of the comparators CP1, CP2 and the synchronous block FFB.
• the comparator CP1 comprises an asynchronous comparator ACP1 receiving the values VAL and B2 / 4, and a synchronization flip-flop FF1 whose clock input H receives the input signal CK1 and triggers the flip-flop FF1 on the falling edge of the signal CK1.
• the comparator ACP1 provides a control signal DETIa on the input D of the flip-flop FF1.
• the output Q of the flip-flop FF1 provides the control signal DET1, which is synchronized with the falling edges of the signal CK1 (the output Q copying the input D at each falling edge).
• the comparator CP2 comprises an asynchronous comparator ACP2 receiving the values VAL and B2 / 2, and a synchronization flip-flop FF2 whose clock input receives the signal CK1 and triggers the flip-flop FF2 on the falling edge of the signal CK1.
• the asynchronous comparator ACP2 provides an asynchronous control signal DET2a and the Q output of the flip-flop FF2 provides the control signal DET2 which is synchronized with the falling edges of the signal CK1.
• the FFB block comprises three synchronous flip-flops FF3, FF4, FF5.
• the flip-flops FF3, FF4 are triggered when their clock input H receives a rising edge and the flip-flop FF5 is triggered when its clock input H receives a falling edge.
• the flip-flop FF3 receives the signal CK1 on its clock input H and receives the signal DET1 on its input D. Its output Q provides the control signal SDET1.
• the signal DET1 is copied to the output Q with a half delay period, at each rising edge of the signal CK1, to form the signal SDET1.
• the flip-flop FF4 receives the signal CK1 on its clock input H and receives the signal DET2 on its input D. Its output Q provides the control signal SDET2. Thus, the signal DET2 is copied to the output Q with a half delay period, at each rising edge of the signal CK1, to form the signal SDET2.
• the flip-flop FF5 forms a divider by 2, its inverted output / Q being connected to its input D. Its clock input H receives the signal SDET2 and its output Q supplies the signal PH. The signal PH is therefore synchronized with the signal SDET2 and passes alternately to 0 or 1 at each falling edge of the signal SDET1.
• the signal PH enables the logic block ALCT to generate the output signal control signals SET, RST in two distinct phases, each phase having the same duration as the period T2 of the output signal, so that to control with accurately the temporal positioning of the rising and falling edges of the output signal CK2.
• the logic block ALCT chooses one of the control signals DET1, DET2, SDET3, SDET4 as the signal SET and RST, taking into account on the one hand the signal PH and on the other hand the bits b1, b0 of lower weight of the division setpoint, in order to correct the rounding error on the two low-order bits made by the divider DV4 and the rounding error on the lower-order bit made by the divider DIV2.
• the setpoint is an even value but the bit bl is equal to 1, so that the rounding error concerns only the bit bl.
• the period T2 of the output signal is therefore identical during each phase and is again of the (N-O, 5) * T1 type.
• Table 1 also shows that the signal PH and the bits b0 bO allow the ALCT logic block to generate the counter reset STO signals ST1, distinguishing the following cases:
• the timing diagram of FIG. 6 represents the form of the signals CK1, DET1, SDET1, PH, DET2, SDET2, SET, RST, ST0, ST1, CK2 and the value counting VAL in the case where a division setpoint equal to 8 (1000) is applied to the frequency divider. It can be seen that the count value does not exceed the value 4 because of the division by 2 of the set point B2 to generate the control signal DET2 (which determines the duration of the period of the output signal). Thus, the period T2 of the output signal is equal to 4 * T1 instead of 8 * T1, which is an output frequency F2 doubled.
• doubling the output frequency makes it possible to apply to the divider according to the invention an input frequency P1 equal to half the input frequency FO to be applied to the divider of FIG. IA to get the same output signal CK2. This results in lower power consumption of the divider.
• FIG. 7 schematically represents the structure of a contactless integrated circuit IC1.
• the integrated circuit ICI is a UHF passive transponder comprising an ICT contactless communication interface circuit, a CCT control circuit and an electrically erasable and electrically programmable MEM memory (EEPROM or FLASH).
• the circuit ICT is connected to an antenna circuit ACT in the form of a dipole allowing it to receive coded data by modulation of an electric field EFLD oscillating at a UHF frequency, for example 800 MHz, the EFLD field being emitted by a reader contactless integrated circuit.
• the ICT circuit also transmits data, here by modulating the reflection coefficient of the ACT antenna circuit (backscattering technique).
• the control circuit CCT is preferably a wired logic circuit.
• the circuit CCT thus receives CMD commands via the ICT interface circuit (for example commands for reading or writing the memory), and transmits RSP responses via the ICT circuit.
• the contactless communication protocol used is for example defined by the EPC TM -GEN2 industrial specification.
• the synchronization circuit comprises an ICMPT counter which is controlled by an FSM logic machine ("Finite State Machine").
• FSM Finite State Machine
• the logic machine FSM applies to the counter a reset signal RST and an authorization signal count ENBL.
• the counter is clocked by a clock signal CK1 of frequency F1 supplied by an oscillator OSC.
• the counter provides a count value A.
• the value B is memorized by a reference register CREG and is applied to the frequency divider DIVF2 according to the invention, which receives the clock signal CK1 as an input signal.
• the logic machine FSM activates the counter ICMPT by carrying the signal ENBL to 1, on detection of a given event, for example the reception of a synchronization frame (continuous signal to 1 received via the interface ICT), and gives the ENBL signal at 0 when the event is no longer detected.
• the signal CK2 is thus synchronized with an external clock signal used to generate the synchronization signal (for example the clock signal of a contactless integrated circuit reader).
• the synchronized signal CK2 is for example used as a subcarrier for retromodulation steps
• the advantage of the invention is that the frequency F1 of the internal clock signal CK1 of the transponder can be divided by 2 to obtain the synchronized frequency F2. This results in lower power consumption.
• the transponder is electrically powered by the ambient electric field, such an economy of electrical consumption improves the overall performance of the transponder and in particular its maximum distance of communication with a reader.
• the first aspect of the invention can be used to produce a frequency divider having no error on the duty cycle, whose output frequency is equal to Fl / B and is not doubled as previously.
• the signals PH 7 STO, DET 2 are not necessary.
• the truth table of the ALCT block can then be in accordance with Table 2 below.

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