EP1956612A1 - Matériau céramique utilisé pour la protection contre les surcharges électriques et varistance à puce multicouche à faible capacité l'utilisant - Google Patents

Matériau céramique utilisé pour la protection contre les surcharges électriques et varistance à puce multicouche à faible capacité l'utilisant Download PDF

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Publication number
EP1956612A1
EP1956612A1 EP07102045A EP07102045A EP1956612A1 EP 1956612 A1 EP1956612 A1 EP 1956612A1 EP 07102045 A EP07102045 A EP 07102045A EP 07102045 A EP07102045 A EP 07102045A EP 1956612 A1 EP1956612 A1 EP 1956612A1
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EP
European Patent Office
Prior art keywords
conductive
glass
semi
capacitance
multilayer chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP07102045A
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German (de)
English (en)
Other versions
EP1956612B1 (fr
Inventor
Ching-Hohn Lien
Cheng-Tsung Kuo
Jun-Nun Lin
Jie-An Zhu
Li-Yun Zhang
Xing-Guang Huang
Wei-Cheng Lien
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SFI Electronics Technology Inc
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SFI Electronics Technology Inc
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Publication date
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Priority to EP20070102045 priority Critical patent/EP1956612B1/fr
Publication of EP1956612A1 publication Critical patent/EP1956612A1/fr
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Publication of EP1956612B1 publication Critical patent/EP1956612B1/fr
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H01C7/105—Varistor cores
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H01C7/105—Varistor cores
    • H01C7/108—Metal oxide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H01C7/105—Varistor cores
    • H01C7/108—Metal oxide
    • H01C7/115—Titanium dioxide- or titanate type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H01C7/105—Varistor cores
    • H01C7/118—Carbide, e.g. SiC type

Definitions

  • the invention relates to a low-capacitance multilayer chip varistor, and more particularly, to a low-capacitance multilayer chip varistor having capacitance lower than 0.5pF at 1MHz for suppressing electrical overstress and electrostatic shock and protecting electronic circuits.
  • varistor is mainly composed of ZnO or SrTiO 3 , and completed by sintering after oxides are added.
  • ZnO varistor is composed of ZnO and oxides of Bi, Sb, Si, Co, Mn, Cr and so on.
  • Bi 2 O 3 and oxides of Co, Mn, Cr and so on form a grain boundary among ZnO particles which has a microstructure like a grain boundary barrier capacitor.
  • varistor composed of such materials has higher capacitance ranging from tens of pF to thousands of pF.
  • the varistor capacitance ranges from about 3pF to hundreds of pF at 1MHz. In circuits for high frequencies, when capacitance of the component for providing protection exceeds 3pF, signals will distort. Therefore, the above component for providing protection is not suitable for high frequencies circuits.
  • varistor component composed of SrTiO 3 has capacitance more than thousands of pF and is not suitable for circuits for high frequencies.
  • the capacitance should be lower to prevent the signals from distortion.
  • U.S. Pat. No. 5,976,420 disclosed a chip type multilayer varistor having a low capacitance and high non-linearity coefficient, mainly composed of SiC containing at least two oxides selected from among SiO 2 , Bi 2 O 3 , PbO, B 2 O 3 and ZnO in an amount of from 0.1 to 20 mol %, and then combined with toluene and a binder agent and mixed by using a ball mill to obtain slurries, and thereafter become ceramic green sheets by using a doctor blade process. A paste was printed on the surface of the green sheets to form an inner electrode thereon. A predetermined number of ceramic green sheets were stacked to form a layered body. The resultant layered body was bonded by pressing at a constant pressure.
  • the resultant green compact was cut into small-sized chips.
  • the green chip was baked at a temperature in the range from 700 to 1100°C to complete a ceramic multilayer chip type varistor resisting electrostatic shock and having surge voltage suppressing capability and a high non-linear coefficient from 10 to 20.
  • the chip has a capacitance in the range from 10 to 40pF, though not quite high, being much greater than 3pF, and thus not suitable for using in high frequency circuits.
  • U.S. Pat. No. 6,251,513 disclosed a component for providing protection.
  • Materials of the component comprise conductive and semi-conductive particles having a particle size of less than 10 ⁇ m and they are mixed with a polymer insulating binder to become a paste-like material.
  • Left and right conductive electrodes are printed on a same surface of an insulating substrate and the paste-like material is filled in the gap between two conductive electrodes and then baked.
  • the capacitance thereof is low and smaller than 0.25pF at 1MHz, the component is suitable for providing protection for high frequencies circuits.
  • the insulating material is composed of polymer material, it is meant that heat generated by electrostatic shock or surge electrical overstress will carbonize the polymer material, make the component to be conductive and lose protection effect for electronic circuits or components. Thus, this component will not have good electrostatic shock withstanding capability and the lifetime thereof is short. Failure will occur only after 500 times of electrostatic shock when static electricity of direct contact 8KV is applied.
  • One objective of the present invention is to provide a low-capacitance multilayer chip varistor with capacitance smaller than 0.5pF at 1MHz.
  • the varistor has surge withstanding capability and a protection effect against static electricity, and more particularly, has a characteristic of resisting more than thousands of times of 8KV electrostatic shock, and maintains original function after thousands times of electrostatic shock.
  • Another objective of the present invention is to provide a protective material against electrical overstress with tiny holes, and the material is used between the positive and negative electrodes for suppressing surge voltage and electrostatic shock.
  • the material comprises inorganic glass of 3 ⁇ 50wt% and semi-conductive or conductive particles of 50 ⁇ 97wt% with particle size of more than 0.1 ⁇ m.
  • a layer of inorganic glass film covers the surface of semi-conductive or conductive particles.
  • the inorganic glass film comprises of semi-conductive or conductive of submicron or nanometer particles, which size is smaller than 1 micron.
  • the quantity contained of semi-conductive or conductive particles is less than 20wt% of that of inorganic glass.
  • Still another objective of the present invention is to provide a low-capacitance multilayer chip varistor with capacitance smaller than 0.5pF at 1MHz.
  • the varistor comprises a ceramic main body, a pair of outer electrodes disposed at two ends of ceramic main body and several inner electrodes disposed therein.
  • the ceramic body is made of a protective material against electrical overstress with tiny holes.
  • the material comprises inorganic glass of 3 ⁇ 50wt% and semi-conductive or conductive particles of 50 ⁇ 97wt% with particle size of more than 0.1 ⁇ m.
  • a layer of inorganic glass film covers the surface of semi-conductive or conductive particles.
  • the inorganic glass film comprises of semi-conductive or conductive materials of submicron or nanometer particles, which size is smaller than 1 micron. The quantity contained of semi-conductive or conductive particles is less than 20wt% of that of inorganic glass.
  • Still another objective of the present invention is to provide a low-capacitance and low-breakdown-voltage multilayer chip varistor.
  • the trigger voltage of the varistor can be controlled by thickness of ceramic green sheets, sintering temperature of ceramic compact, glass layer thickness of grain boundary, size of conductive or semi-conductive particles and the quantity added of conductive or semi-conductive particles of nanometer sizes for secondary dispersion.
  • a low-capacitance multilayer chip varistor 10 in one preferred embodiment of the present invention is made by multilayer technology process.
  • the varistor 10 is made by multilayer ceramic processes comprising high-temperature sintering and so on, and comprises a ceramic main body 11, outer electrodes 13 disposed at two ends of the ceramic main body 11 and inner electrodes 12 disposed therein.
  • the ceramic main body 11 is made by a protective material against electrical overstress with tiny holes, e.g. pores, and the microstructure thereof is shown in FIG. 2 , which has high proportion of holes.
  • the material of this specimen comprises inorganic glass of 3 ⁇ 50wt% and semi-conductive or conductive particles 14 of 50 ⁇ 97wt% with a particle size of more than 0.1 ⁇ m.
  • a layer of inorganic glass film 15 that resists high temperature covers the surface of semi-conductive or conductive particles 14.
  • the inorganic glass film 15 further comprises of the submicron or nanometer of semi-conductive or conductive particles 16, which is smaller than 1 micron for secondary dispersion.
  • the quantity contained of semi-conductive or conductive particles is less than 20wt% of that of inorganic glass.
  • the microstructure of the ceramic body 11 has high proportion of holes and low capacitance, which is less than 0.5pF at 1MHz.
  • the inorganic glass film 15 that resists high temperature exists among the semi-conductive or conductive particles 14 of the ceramic main body 11 for resisting heat generated when suppressing electrostatic shock or surge electrical overstress.
  • the inorganic glass film 15 comprises semi-conductive or conductive particles 16 of 0.1 micron or nanometer for secondary dispersion, and the gap among the particles 16 is quite small, so that when abnormal electrical overstress occurs the tunnel effect will occur. Consequently, the low-capacitance multilayer chip varistor 10 disclosed in the present invention suppresses electrical overstress, resists electrostatic shock and has a long lifetime.
  • the process of making the low-capacitance multilayer chip varistor 10 comprises steps of:
  • the low-capacitance multilayer chip varistor in the preferred embodiment of the invention made by above processes has advantages of low capacitance, low breakdown voltage and so on, and suppresses thousands of times of 8KV electrostatic shock, while the capacitance thereof is smaller than 0.5pF and thus can be used to protect electronic circuits for high frequencies.
  • the following paragraphs will describe some preferred embodiments of the low-capacitance multilayer chip varistor according to the present invention, wherein the varistor has characteristics of 0.5pF capacitance at 1MHz, suppressing thousands of times of 8KV electrostatic shock, suppressing electrical overstress, suppressing electrostatic shock and protecting electronic circuits for high frequencies.
  • SiC powder of particle size ranging from 0.1 ⁇ 20 ⁇ m and nano-metal Pt of particle size ranging from 0.01 ⁇ 2 ⁇ m are added into the gel-like solution composed of nano-silicate glass, which made by sol-gel process, and well stirred the previous mixed solution.
  • the SiC powder uniformly surrounded a layer of organic film containing glass component.
  • Eight samples with different solutions are obtained according to the weight proportion of the SiC powder, nano-Pt and glass as shown in following Table 1.
  • the mixed solutions as shown in Table 1 are dried to become powders and disposed in a calcining oven for being calcined at 700°C to become SiC powders coated with glass film.
  • the calcined powder is milled roughly and then finely, and a solution (such as toluene or butanol), a binder agent (such as polyvinyl butyral) and a dispersing agent are put together into a ball mill to be milled to obtain slurries. Then, it becomes ceramic green sheets of 30 ⁇ m thickness by using a doctor blade process.
  • a solution such as toluene or butanol
  • a binder agent such as polyvinyl butyral
  • a dispersing agent such as polyvinyl butyral
  • the more glass is contained the high breakdown voltage and the less capacitance. This phenomenon is related to the high resistance of the glass.
  • the grain boundary insulating layer is thicker, and thus the multilayer chip varistor has higher breakdown voltage and smaller capacitance.
  • the multilayer chip varistor has preferred electro-static discharge (ESD) suppressing capability.
  • ESD electro-static discharge
  • the insulating resistance will be not enough, and the variation of breakdown voltage at 1mA will be larger than 10% for the multilayer chip varistor after ESD.
  • the electrical characteristics are better when the glass contained is more than 15wt%.
  • the breakdown voltage and trigger voltage will be too high (the trigger voltage is more than 800V) and not suitable as protective component. Therefore, the quantity of glass addition is preferred to be controlled between 15wt% to 20wt%.
  • Oxides such as ZnO powder, Bi 2 O 3 , CoO and so on of particle size ranging from 0.1 ⁇ 20 ⁇ m and nano-metal Pd of particle size ranging from 0.01 ⁇ 2 ⁇ m are added into the gel-like solution composed of nano-silicate glass, which made by sol-gel process, well stirred the previous mixed solution.
  • the SiC powder uniformly surrounded a layer of organic film containing glass component.
  • Table 4 shows that when oxides such as ZnO and so on are taken as semi-conductive particles and the process of the present invention is used, the low-capacitance and static electricity suppressing multilayer chip varistor can be made.
  • Table 4 also shows that the multilayer chip varistor using ZnO as material has higher trigger voltage.
  • the thickness of sheets among electrodes is changed from 30 ⁇ m to 15 ⁇ m, and then the result is shown in Table 5.
  • Table 5 Sheet Thickness ( ⁇ m) Breakdown Voltage (V1mA) Capacitance (pF at 1MHz) Trigger Voltage (V) Breakdown Voltage Variation After 1000 Times of Electrostatic Shock (%) 15 143 0.43 257 15
  • SiC powder of particle size ranging from 2 ⁇ 7 ⁇ m and nano-metal Pt of particle size ranging from 0.03 ⁇ 0.5 ⁇ m are added into the gel-like solution composed of nano-silicate glass, which made by sol-gel process, well stirred the previous mixed solution.
  • the SiC powder uniformly surrounded a layer of organic film containing glass component.
  • a multilayer chip varistor is completed.
  • the electrical characteristics of the multilayer chip varistor are measured and shown in Table 6.
  • the multilayer chip varistor has lower breakdown voltage; however, the capacitance is relatively higher.
  • the multilayer chip varistor sheets made in the Example 1 are sintered at 850 ⁇ 1000°C, and the effects of different sintering conditions are shown in Table 7. It shows that when the sintering temperature is higher, the breakdown voltage is lower; however the capacitance is increased and the leakage current is decreased. Similarly, when the sintering time is increased, the breakdown voltage is lower. Table 7 Sintering Temperature (°C) Sintering Time (hr) Breakdown Voltage (V1mA) Capacitance (pF at 1MHz) Leakage Current ( ⁇ A at 24V) 850 2 265 0.10 0.67 850 5 228 0.11 0.53 950 2 185 0.13 0.50
  • Table 8 Overlapping Area of Inner Electrodes (mm 2 ) 0.12 0.06 0.03 Capacitance (pF at 1MHz) 0.12 0.07 0.03
  • the multilayer chip varistor according to the present invention has quite low capacitance, and is particularly suitable to be applied in the protection for high frequency circuits against electrical overstress such as static electricity or transient surge.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Thermistors And Varistors (AREA)
EP20070102045 2007-02-09 2007-02-09 Matériau céramique utilisé pour la protection contre les surcharges électriques et varistance à puce multicouche à faible capacité l'utilisant Not-in-force EP1956612B1 (fr)

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Application Number Priority Date Filing Date Title
EP20070102045 EP1956612B1 (fr) 2007-02-09 2007-02-09 Matériau céramique utilisé pour la protection contre les surcharges électriques et varistance à puce multicouche à faible capacité l'utilisant

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Application Number Priority Date Filing Date Title
EP20070102045 EP1956612B1 (fr) 2007-02-09 2007-02-09 Matériau céramique utilisé pour la protection contre les surcharges électriques et varistance à puce multicouche à faible capacité l'utilisant

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EP1956612A1 true EP1956612A1 (fr) 2008-08-13
EP1956612B1 EP1956612B1 (fr) 2014-12-31

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3725836A (en) * 1971-05-21 1973-04-03 Matsushita Electric Ind Co Ltd Thick film varistor and method for making the same
EP0115050B1 (fr) * 1982-12-24 1987-03-11 Kabushiki Kaisha Toshiba Varistor
US5096620A (en) * 1990-02-19 1992-03-17 Schott Glaswerke Lead-zinc-borosilicate glass
JPH0555010A (ja) * 1991-08-23 1993-03-05 Sumitomo Kinzoku Ceramics:Kk 電圧非直線性素子の製造方法
JP2001093706A (ja) * 1999-09-24 2001-04-06 Matsushita Electric Ind Co Ltd 積層セラミックバリスタ及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3725836A (en) * 1971-05-21 1973-04-03 Matsushita Electric Ind Co Ltd Thick film varistor and method for making the same
EP0115050B1 (fr) * 1982-12-24 1987-03-11 Kabushiki Kaisha Toshiba Varistor
US5096620A (en) * 1990-02-19 1992-03-17 Schott Glaswerke Lead-zinc-borosilicate glass
JPH0555010A (ja) * 1991-08-23 1993-03-05 Sumitomo Kinzoku Ceramics:Kk 電圧非直線性素子の製造方法
JP2001093706A (ja) * 1999-09-24 2001-04-06 Matsushita Electric Ind Co Ltd 積層セラミックバリスタ及びその製造方法

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