EP1955222A2 - Procede d'analyse de chute de tension d'une distribution de courant dans un circuit integre - Google Patents

Procede d'analyse de chute de tension d'une distribution de courant dans un circuit integre

Info

Publication number
EP1955222A2
EP1955222A2 EP06821443A EP06821443A EP1955222A2 EP 1955222 A2 EP1955222 A2 EP 1955222A2 EP 06821443 A EP06821443 A EP 06821443A EP 06821443 A EP06821443 A EP 06821443A EP 1955222 A2 EP1955222 A2 EP 1955222A2
Authority
EP
European Patent Office
Prior art keywords
voltage
drop
circuit
integrated circuit
ideal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06821443A
Other languages
German (de)
English (en)
Inventor
Brent Buchanan
Mark Turner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of EP1955222A2 publication Critical patent/EP1955222A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation

Definitions

  • the present invention is directed generally to voltage drop in integrated circuits and methods of analyzing such for improved circuit design.
  • Integrated circuits continue to become more complex, operating at higher data-processing speeds with increased densities in smaller IC packages. Adding to these complexities is the ever-increasing demand for decreased power consumption without impacting the distribution of power throughout the circuits.
  • modern IC designers use various tools to simplify the design process including, for example, computer-aided design (CAD) tools which can help speed up the development time of an IC by automating much of the design process. This decreases the time and cost necessary to develop an IC and helps the designer create more competitive products in the market.
  • CAD computer-aided design
  • an external power supply source is connected to the internal die circuitry via lead pins and bond pads that connect directly to the die, via power pad cells.
  • a power-bus grid of thin metal wires is typically used to route the power from the power pad cells to the die circuitry throughout the core.
  • Power distributed to the die circuitry via the power-bus grid can present significant problems to the IC designer. For example, where circuits are intended to operate at relatively low-level voltages, a slight voltage drop can result in defective operation. Such a voltage drop across a wire, or region of the die, is proportional to the amount of current the wire or region is conducting as well as the corresponding internal resistance.
  • CAD tools have become commercially available to assist with such static analysis.
  • One commonly-used tool in this regard is a power- distribution/power-grid verification CAD tool, such as VoltageStorm® as marketed by Cadence of San Jose, California.
  • This type of tool permits the IC designer to statically and dynamically map the ICs power-consumption data to an image for analysis by the IC designer. The images are color coded to indicate where the circuitry is consuming relatively large amounts of the distributed power.
  • Various uses of such tools are described, for example, in U.S. Patent No. 6,725,434 (Method of Verifying Designed Circuits), U.S. Patent No. 5,872,952 (Integrated Circuit Power Net Analysis Through Simulation), and U.S. Patent No. 6,675,139 (Floor Plan-Based Power Bus Analysis and Design Tool for Integrated Circuits).
  • One aspect of the present invention is directed to a method for analyzing voltage-drop data in integrated circuits using a signal processing imaging algorithm.
  • Various aspects of the present invention are applicable to a method for automatically analyzing voltage drop in the power distribution of an integrated circuit.
  • the method includes using a circuit-representative image that corresponds to an actual implementation of the integrated circuit to represent actual voltage-drop data for power distributed across the integrated circuit.
  • a circuit-ideal image that corresponds to an ideal implementation of the integrated circuit is then used to represent ideal voltage-drop data for power distributed across the integrated circuit.
  • the actual voltage-drop data is compared with the ideal voltage-drop data, and in response to the comparison, it is determined whether the power distribution in the integrated circuit satisfies a predetermined power distribution condition.
  • Another aspect of the present invention is directed to an approach that assumes the existence of a linear, space-invariant, equivalent IC image.
  • the voltage-drop gradient of this ideal IC image data is computed and then compared with the results of an actual ICs voltage-drop data image. Where the corresponding data points between the actual and ideal images are close in value, the voltage-drop data is acceptable. Where the corresponding data points deviate sufficiently in value from a predetermined threshold, the voltage drop is not acceptable.
  • FIG 1 is a data-flow diagram illustrating the use of an actual voltage-drop circuit image and an ideal voltage-drop circuit image, according to an example embodiment of the present invention.
  • FIG 2 is a flow chart illustrating one example of a manner for analyzing voltage drop using images such as those in FIG. 1 , according to an example embodiment of the present invention.
  • the present invention is believed to be useful for designing ICs with efficient and adequate power distribution. While the present invention is not necessarily limited to such applications, various aspects of the invention may be appreciated through a discussion of various examples using this context.
  • a method is used to automatically analyze voltage drop in the power distribution of an integrated circuit.
  • the method includes using a circuit-representative image that corresponds to an actual implementation of the integrated circuit to represent actual voltage-drop data for power distributed across the integrated circuit.
  • a circuit-ideal image corresponding to an ideal implementation of the integrated circuit, is used to represent ideal voltage-drop data for power distributed across the integrated circuit.
  • the circuit-ideal image can be developed in a variety of ways including, for example, using some of the actual or approximated voltage-drop data as a basis to generate other portions of and complete the circuit-ideal image.
  • the actual voltage-drop data is compared with the ideal voltage-drop data, and in response to the comparison, it is determined whether the power distribution in the integrated circuit satisfies a predetermined power distribution condition.
  • Voltage-drop (a.k.a., IR-drop) mapping tools are used to ensure that sufficient power is routed through an IC. Such tools typically produce an image of the IC having a color gradient indicative of the IR-drop variance across the IC. Ideally, IR-drop is expected to be at a minimum near the IC edges and at a maximum near the IC center where the power distribution is most remote from the IC edges. Thus, in the hypothetical situation where the power distribution area for an IC corresponds to concentric circles, an ideal IR-drop variance image should look like the targeted pattern (or bull's eye) on a dart board. When images of actual IR- drop data deviate from this ideal pattern, such discrepancies make the interpretation of IR-drop images difficult.
  • the present invention mitigates the likelihood of error by an IC designer in attempting to visually assess the images and subjectively (using art- like skills) ascertain whether design improvement is possible and/or necessary. Automated (e.g., computer-based) interpretation of this data reduces the variance and errors in these human interpretations.
  • the present invention is directed to automatically calculating the gradients from such irregularly spaced and dense IR- drop data points.
  • automated calculations involve modern digital/discrete signal processing (hardware and/or software) tools that employ arithmetic logic for high-speed processing outside of linear, space- invariant constraints.
  • Fig. 1 shows an approach for mapping IR-drop data points to create an idealized IR-drop image for use in automatically analyzing actual IR-drop data according to one example embodiment of the present invention.
  • the approach involves creating an IR-drop image of an actual circuit.
  • the image uses color gradients to indicate regions of varying voltage drop; in Fig. 1 these color gradients are shown using different cross-hatch shading. For example, the largest voltage drop occurs in the shaded areas 112, the next largest voltage drop occurs in the area with diagonal lines 114, the next largest voltage drop occurs in the area having horizontal lines 116, and the area with the least amount of voltage drop across the die occurs in the area with vertical lines 118.
  • the voltage drop near the center of the actual IR-drop image is typically the worst case voltage drop for the die.
  • an idea IR-drop image 120 must be created.
  • the ideal die image will correspond to the actual image's structure and circuit specifications, which must be provided to the mapping tool 122.
  • the idealized IR-drop image is created by mapping boundary-condition points which in a typical embodiment includes points at which supply voltages are provided to the IC, e.g., point A mapped to the ideal IR-drop image as point A'.
  • these boundary-condition data points also include the points from the actual voltage-drop image experiencing the largest voltage drop in the IC.
  • the mapping may incorporate grid coordinates since the structure of both the actual and ideal images is the same, and the mapping includes both the location of the data point and the value of the voltage-drop data at that point.
  • a Laplacian of these boundary- condition data points is used to complete the ideal IR-drop image.
  • the image is formed such that the 2-D differential of the image with the above constraints has no discontinuities.
  • the locations of corresponding data points in intervening regions are then mapped on the ideal IR-drop image, e.g., C mapped to C.
  • each point in the actual IR-drop image is compared to the value at that point of the ideal IR-drop image, and the resultant scalar values are used to form a histogram. Any values outside of a predetermined variance from the histogram's central lobe would be flagged by software for additional examination by the IC designers. This analysis can be further aided by weighting the data points so as to use a single predetermined variance. If none of the data points are flagged, the IC is determined to meet the power requirements of the IC specifications.
  • idealized IR-drop image data is created for a comparison with actual IR-drop image data.
  • a mapping tool is used to create an IR-drop image of the actual die being tested.
  • One commercially - available mapping tool is the above-discussed Cadence VoltageStorm®.
  • the actual ICs circuit specifications and boundary-condition IR-drop data points are used to create an initial ideal IR-drop image of a corresponding idealized die. These boundary-condition IR-drop data points generally will be data points along the edge of the die where power is supplied and data points located near the center of the die.
  • the initial ideal IR-drop image is revised using the Laplacian of the boundary condition IR-data points to identify data points in the regions between the edges and the center of the ideal die.
  • the mapping of the idealized IR-drop image data is completed by filling in the identified intervening data points.
  • value assignments for the IR-drop data points can be adjusted to perform a weighted comparison.
  • one variance threshold can be used for each of the analyzed IR-drop data points and those data points near the center of the images would be acknowledged as being more sensitive.
  • the image data of the actual IR-drop image is then compared point-for- point with the idealized IR-drop image data at block 260.
  • a data point on the actual ICs IR-drop image is not within a predetermined threshold of the corresponding idealized data point, the actual IR-drop data point is flagged. If no data points are flagged, the die is considered to be in compliance with the ICs power specifications and the analysis is complete at block 280. However, if data points are flagged on the actual IR-drop image, an IC designer will analyze the flagged data points and evaluate whether to redesign or reroute the IC power grid at block 290.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Power Sources (AREA)

Abstract

La présente invention concerne un procédé destiné à analyser automatiquement une chute de tension dans une distribution de courant d'un circuit intégré, consistant à comparer des données réelles d'image de chute de tension à des données prédites et théoriques d'image de chute de tension pour une version théorique dudit circuit. Le procédé consiste à utiliser une image représentative de circuit correspondant à une mise en oeuvre réelle du circuit intégré pour représenter des données réelles de chute de tension pour le courant distribué dans le circuit intégré. Ensuite, une image théorique de circuit correspondant à une mise en oeuvre théorique du circuit intégré sert à représenter des données théoriques de chute de tension pour le courant distribué dans le circuit intégré. Les données réelles de chute de tension sont comparées aux données théoriques de chute de tension et, suite à la comparaison, le procédé permet de déterminer si la distribution de courant dans le circuit intégré satisfait à une condition de distribution de courant préétablie.
EP06821443A 2005-11-14 2006-11-14 Procede d'analyse de chute de tension d'une distribution de courant dans un circuit integre Withdrawn EP1955222A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US73626605P 2005-11-14 2005-11-14
PCT/IB2006/054255 WO2007054925A2 (fr) 2005-11-14 2006-11-14 Procede d'analyse de chute de tension d'une distribution de courant dans un circuit integre

Publications (1)

Publication Number Publication Date
EP1955222A2 true EP1955222A2 (fr) 2008-08-13

Family

ID=37832052

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06821443A Withdrawn EP1955222A2 (fr) 2005-11-14 2006-11-14 Procede d'analyse de chute de tension d'une distribution de courant dans un circuit integre

Country Status (4)

Country Link
EP (1) EP1955222A2 (fr)
JP (1) JP2009516255A (fr)
CN (1) CN101310279A (fr)
WO (1) WO2007054925A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014031236A1 (fr) * 2012-08-23 2014-02-27 Itron, Inc. Optimisation électrique et sélection de composant dans un réseau de distribution électrique
CN112100960B (zh) * 2020-11-19 2021-03-09 北京智芯微电子科技有限公司 动态检测fpga芯片内压降的方法及fpga芯片

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5872952A (en) * 1995-04-17 1999-02-16 Synopsys, Inc. Integrated circuit power net analysis through simulation
US5933358A (en) * 1997-09-30 1999-08-03 Synopsys, Inc. Method and system of performing voltage drop analysis for power supply networks of VLSI circuits
US6675139B1 (en) * 1999-03-16 2004-01-06 Lsi Logic Corporation Floor plan-based power bus analysis and design tool for integrated circuits
JP2002197138A (ja) * 2000-12-25 2002-07-12 Sony Corp 設計回路の検証方法
US6938233B2 (en) * 2002-08-09 2005-08-30 Matsushita Electric Industrial Co., Ltd. Method and apparatus for designing semiconductor integrated circuit device based on voltage drop distribution
JP2004139181A (ja) * 2002-10-15 2004-05-13 Renesas Technology Corp レイアウト装置及びプログラム

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2007054925A2 *

Also Published As

Publication number Publication date
WO2007054925A3 (fr) 2007-10-25
JP2009516255A (ja) 2009-04-16
WO2007054925A2 (fr) 2007-05-18
CN101310279A (zh) 2008-11-19

Similar Documents

Publication Publication Date Title
US6675139B1 (en) Floor plan-based power bus analysis and design tool for integrated circuits
US7016794B2 (en) Floor plan development electromigration and voltage drop analysis tool
US6272668B1 (en) Method for cell swapping to improve pre-layout to post-layout timing
US6289412B1 (en) Layout synopsizing process for efficient layout parasitic extraction and circuit simulation in post-layout verification
JP2810341B2 (ja) 超ｌｓｉ回路のパワーネットワークの分析装置及び分析方法
US5754826A (en) CAD and simulation system for targeting IC designs to multiple fabrication processes
US6971076B2 (en) Method for estimating peak crosstalk noise based on separate crosstalk model
KR100281977B1 (ko) 집적 회로 설계 방법, 집적 회로 설계용 데이터베이스 장치 및집적 회로 설계 지원 장치
US20060277512A1 (en) Engineering change order process optimization
US20090319969A1 (en) Method and system for performing statistical leakage characterization, analysis, and modeling
US20080127020A1 (en) System and method for automatic elimination of voltage drop, also known as IR drop, violations of a mask layout block, maintaining the process design rules correctness
US20020174409A1 (en) System and method for analyzing power distribution using static timing analysis
US8954915B2 (en) Structured placement of hierarchical soft blocks during physical synthesis of an integrated circuit
US6868374B1 (en) Method of power distribution analysis for I/O circuits in ASIC designs
US8595677B1 (en) Method and system for performing voltage-based fast electrical analysis and simulation of an electronic design
US20100287515A1 (en) interactive checker in a layout editor
US6751744B1 (en) Method of integrated circuit design checking using progressive individual network analysis
US7315992B2 (en) Electro-migration (EM) and voltage (IR) drop analysis of integrated circuit (IC) designs
Baek et al. Pin accessibility and routing congestion aware DRC hotspot prediction using graph neural network and U-Net
US7065728B2 (en) Method for placing electrostatic discharge clamps within integrated circuit devices
WO2007054925A2 (fr) Procede d'analyse de chute de tension d'une distribution de courant dans un circuit integre
US8185858B2 (en) Apparatus, method, and program for predicting layout wiring congestion
JP5071081B2 (ja) 半導体装置に対する同時動作信号ノイズ見積り方法における同時動作信号ノイズ基礎特性取得方法、及びプログラム
US7559042B2 (en) Layout evaluating apparatus
US6470476B2 (en) Substitution of non-minimum groundrule cells for non-critical minimum groundrule cells to increase yield

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20080616

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA HR MK RS

17Q First examination report despatched

Effective date: 20100401

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20100812