EP1955222A2

EP1955222A2 - Method for analyzing voltage drop in power distribution across an integrated circuit

Info

Publication number: EP1955222A2
Application number: EP06821443A
Authority: EP
Inventors: Brent Buchanan; Mark Turner
Original assignee: NXP BV
Current assignee: NXP BV
Priority date: 2005-11-14
Filing date: 2006-11-14
Publication date: 2008-08-13
Also published as: JP2009516255A; WO2007054925A2; WO2007054925A3; CN101310279A

Abstract

A method for automatically analyzing voltage drop in the power distribution of an integrated circuit involves comparing actual voltage-drop image data with predicted idealized voltage-drop image data for an idealized version of the IC. The method includes using a circuit-representative image that corresponds to an actual implementation of the integrated circuit to represent actual voltage-drop data for power distributed across the integrated circuit. Then a circuit-ideal image that corresponds to an ideal implementation of the integrated circuit is used to represent ideal voltage-drop data for power distributed across the integrated circuit. The actual voltage-drop data is compared with the ideal voltage-drop data, and in response to the comparison, it is determined whether the power distribution in the integrated circuit satisfies a predetermined power distribution condition.

Description

METHOD FOR ANALYZING VOLTAGE DROP IN POWER DISTRIBUTION ACROSS AN INTEGRATED CIRCUIT

The present invention is directed generally to voltage drop in integrated circuits and methods of analyzing such for improved circuit design.

Integrated circuits (ICs) continue to become more complex, operating at higher data-processing speeds with increased densities in smaller IC packages. Adding to these complexities is the ever-increasing demand for decreased power consumption without impacting the distribution of power throughout the circuits. To address these performance requirements, modern IC designers use various tools to simplify the design process including, for example, computer-aided design (CAD) tools which can help speed up the development time of an IC by automating much of the design process. This decreases the time and cost necessary to develop an IC and helps the designer create more competitive products in the market.

One design consideration related to the decreasing size of IC components is voltage drop across the IC. Generally, an external power supply source is connected to the internal die circuitry via lead pins and bond pads that connect directly to the die, via power pad cells. A power-bus grid of thin metal wires is typically used to route the power from the power pad cells to the die circuitry throughout the core.

Power distributed to the die circuitry via the power-bus grid can present significant problems to the IC designer. For example, where circuits are intended to operate at relatively low-level voltages, a slight voltage drop can result in defective operation. Such a voltage drop across a wire, or region of the die, is proportional to the amount of current the wire or region is conducting as well as the corresponding internal resistance.

The internal resistance in the power distribution structures of ICs is therefore a subject of much scrutiny and significant research to ensure that no more than the sufficient amount of power routing is provided or designers must guess as to the appropriate amount of power routing. To avoid these failures, IC designers attempt to manage voltage (or "IR") drops throughout the design process - from the planning stage to the commercially-implemented die. Early in the design process, when it is not practicable to test an actual die, static analysis can give designers useful information for making important design decisions.

Various forms of CAD tools have become commercially available to assist with such static analysis. One commonly-used tool in this regard is a power- distribution/power-grid verification CAD tool, such as VoltageStorm® as marketed by Cadence of San Jose, California. This type of tool permits the IC designer to statically and dynamically map the ICs power-consumption data to an image for analysis by the IC designer. The images are color coded to indicate where the circuitry is consuming relatively large amounts of the distributed power. Various uses of such tools are described, for example, in U.S. Patent No. 6,725,434 (Method of Verifying Designed Circuits), U.S. Patent No. 5,872,952 (Integrated Circuit Power Net Analysis Through Simulation), and U.S. Patent No. 6,675,139 (Floor Plan-Based Power Bus Analysis and Design Tool for Integrated Circuits).

As with many CAD tools, such power-verification tools do not provide specific circuit analysis. For many design applications, such tools still require that an IC designer guess as to whether a power-distribution design is adequate per circuitry specifications. Such guessing often exposes the IC to a wide variety of problems that are difficult to identify and alleviate. To overcome such limitations, as well as time and other engineering expenses, the standard approach has been to over-design the power routing of an IC by using very conservative power estimates when designing the power-bus grid. Designers typically multiply the amount of current estimated to flow through the power-bus grid by a cushioning factor to avoid voltage drop problems. These conservative estimates generally result in integrated circuits that are significantly larger than actually necessary to distribute power throughout the IC.

One aspect of the present invention is directed to a method for analyzing voltage-drop data in integrated circuits using a signal processing imaging algorithm. These and other aspects of the present invention are exemplified in a number of illustrated implementations and applications, some of which are shown in the figures and characterized in the claims section that follows.

Various aspects of the present invention are applicable to a method for automatically analyzing voltage drop in the power distribution of an integrated circuit. The method includes using a circuit-representative image that corresponds to an actual implementation of the integrated circuit to represent actual voltage-drop data for power distributed across the integrated circuit. A circuit-ideal image that corresponds to an ideal implementation of the integrated circuit is then used to represent ideal voltage-drop data for power distributed across the integrated circuit. The actual voltage-drop data is compared with the ideal voltage-drop data, and in response to the comparison, it is determined whether the power distribution in the integrated circuit satisfies a predetermined power distribution condition.

Another aspect of the present invention is directed to an approach that assumes the existence of a linear, space-invariant, equivalent IC image. The voltage-drop gradient of this ideal IC image data is computed and then compared with the results of an actual ICs voltage-drop data image. Where the corresponding data points between the actual and ideal images are close in value, the voltage-drop data is acceptable. Where the corresponding data points deviate sufficiently in value from a predetermined threshold, the voltage drop is not acceptable.

The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.

The invention may be more completely understood in consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which: FIG 1 is a data-flow diagram illustrating the use of an actual voltage-drop circuit image and an ideal voltage-drop circuit image, according to an example embodiment of the present invention; and

FIG 2 is a flow chart illustrating one example of a manner for analyzing voltage drop using images such as those in FIG. 1 , according to an example embodiment of the present invention.

While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.

The present invention is believed to be useful for designing ICs with efficient and adequate power distribution. While the present invention is not necessarily limited to such applications, various aspects of the invention may be appreciated through a discussion of various examples using this context.

In connection with an example embodiment of the present invention, a method is used to automatically analyze voltage drop in the power distribution of an integrated circuit. The method includes using a circuit-representative image that corresponds to an actual implementation of the integrated circuit to represent actual voltage-drop data for power distributed across the integrated circuit. A circuit-ideal image, corresponding to an ideal implementation of the integrated circuit, is used to represent ideal voltage-drop data for power distributed across the integrated circuit. The circuit-ideal image can be developed in a variety of ways including, for example, using some of the actual or approximated voltage-drop data as a basis to generate other portions of and complete the circuit-ideal image. The actual voltage-drop data is compared with the ideal voltage-drop data, and in response to the comparison, it is determined whether the power distribution in the integrated circuit satisfies a predetermined power distribution condition.

Voltage-drop (a.k.a., IR-drop) mapping tools are used to ensure that sufficient power is routed through an IC. Such tools typically produce an image of the IC having a color gradient indicative of the IR-drop variance across the IC. Ideally, IR-drop is expected to be at a minimum near the IC edges and at a maximum near the IC center where the power distribution is most remote from the IC edges. Thus, in the hypothetical situation where the power distribution area for an IC corresponds to concentric circles, an ideal IR-drop variance image should look like the targeted pattern (or bull's eye) on a dart board. When images of actual IR- drop data deviate from this ideal pattern, such discrepancies make the interpretation of IR-drop images difficult. By comparing the actual voltage-drop data with the ideal voltage-drop data, the present invention mitigates the likelihood of error by an IC designer in attempting to visually assess the images and subjectively (using art- like skills) ascertain whether design improvement is possible and/or necessary. Automated (e.g., computer-based) interpretation of this data reduces the variance and errors in these human interpretations.

In many IC applications, accurately automating such analysis is difficult due to the data points in an IR-drop image being neither equally spaced nor uniformly distributed (because the electronic components are not equally spaced or uniformly distributed). In accordance with another aspect, the present invention is directed to automatically calculating the gradients from such irregularly spaced and dense IR- drop data points. In a more specific application, such automated calculations involve modern digital/discrete signal processing (hardware and/or software) tools that employ arithmetic logic for high-speed processing outside of linear, space- invariant constraints.

Fig. 1 shows an approach for mapping IR-drop data points to create an idealized IR-drop image for use in automatically analyzing actual IR-drop data according to one example embodiment of the present invention. The approach involves creating an IR-drop image of an actual circuit. The image uses color gradients to indicate regions of varying voltage drop; in Fig. 1 these color gradients are shown using different cross-hatch shading. For example, the largest voltage drop occurs in the shaded areas 112, the next largest voltage drop occurs in the area with diagonal lines 114, the next largest voltage drop occurs in the area having horizontal lines 116, and the area with the least amount of voltage drop across the die occurs in the area with vertical lines 118. The voltage drop near the center of the actual IR-drop image is typically the worst case voltage drop for the die. To compare the actual IR-drop image with idealized data, an idea IR-drop image 120 must be created. The ideal die image will correspond to the actual image's structure and circuit specifications, which must be provided to the mapping tool 122.

The idealized IR-drop image is created by mapping boundary-condition points which in a typical embodiment includes points at which supply voltages are provided to the IC, e.g., point A mapped to the ideal IR-drop image as point A'. In certain embodiments, these boundary-condition data points also include the points from the actual voltage-drop image experiencing the largest voltage drop in the IC. The mapping may incorporate grid coordinates since the structure of both the actual and ideal images is the same, and the mapping includes both the location of the data point and the value of the voltage-drop data at that point.

In accordance with one specific approach, a Laplacian of these boundary- condition data points is used to complete the ideal IR-drop image. With this approach, the image is formed such that the 2-D differential of the image with the above constraints has no discontinuities. The locations of corresponding data points in intervening regions are then mapped on the ideal IR-drop image, e.g., C mapped to C.

To analyze the actual IR-drop image, each point in the actual IR-drop image is compared to the value at that point of the ideal IR-drop image, and the resultant scalar values are used to form a histogram. Any values outside of a predetermined variance from the histogram's central lobe would be flagged by software for additional examination by the IC designers. This analysis can be further aided by weighting the data points so as to use a single predetermined variance. If none of the data points are flagged, the IC is determined to meet the power requirements of the IC specifications.

Referring to the flow chart of Fig. 2, idealized IR-drop image data is created for a comparison with actual IR-drop image data. At block 210 a mapping tool is used to create an IR-drop image of the actual die being tested. One commercially - available mapping tool is the above-discussed Cadence VoltageStorm®. At block 220 the actual ICs circuit specifications and boundary-condition IR-drop data points are used to create an initial ideal IR-drop image of a corresponding idealized die. These boundary-condition IR-drop data points generally will be data points along the edge of the die where power is supplied and data points located near the center of the die. At block 230, the initial ideal IR-drop image is revised using the Laplacian of the boundary condition IR-data points to identify data points in the regions between the edges and the center of the ideal die. At block 240, the mapping of the idealized IR-drop image data is completed by filling in the identified intervening data points. Optionally, at block 250, value assignments for the IR-drop data points can be adjusted to perform a weighted comparison. Thus, one variance threshold can be used for each of the analyzed IR-drop data points and those data points near the center of the images would be acknowledged as being more sensitive. The image data of the actual IR-drop image is then compared point-for- point with the idealized IR-drop image data at block 260. At block 270, if a data point on the actual ICs IR-drop image is not within a predetermined threshold of the corresponding idealized data point, the actual IR-drop data point is flagged. If no data points are flagged, the die is considered to be in compliance with the ICs power specifications and the analysis is complete at block 280. However, if data points are flagged on the actual IR-drop image, an IC designer will analyze the flagged data points and evaluate whether to redesign or reroute the IC power grid at block 290.

While certain aspects of the present invention have been described with reference to several particular example embodiments, those skilled in the art will recognize that many changes may be made thereto without departing from the spirit and scope of the present invention. Aspects of the invention are set forth in the following claims.

Claims

What is claimed is:

1. A method for automatically analyzing voltage drop in the power distribution of an integrated circuit, the method comprising: using a circuit-representative image corresponding to an actual implementation of the integrated circuit to represent actual voltage-drop data for power distributed across the integrated circuit; using a circuit-ideal image corresponding to an ideal implementation of the integrated circuit to represent ideal voltage-drop data for power distributed across the integrated circuit; comparing the actual voltage-drop data with the ideal voltage-drop data; and in response to the comparison, determining whether the power distribution in the integrated circuit satisfies a predetermined power distribution condition.

2. The method of claim 1 , further including using a voltage-drop mapping tool to provide the circuit-representative image.

3. The method of claim 1, wherein the circuit- ideal image of the integrated circuit is based on a comparable linear, space-invariant distribution of voltage-drop data.

4. The method of claim 3, further including creating the circuit- ideal image, wherein the step of creating the circuit-ideal image includes mapping boundary condition voltage-drop points, including points where the power supply voltages are applied and points at or near the center of the image of the actual implementation, to at least one boundary region and a center region of the circuit-ideal image.

5. The method of claim 3, further including creating the circuit- ideal image, wherein the step of creating the circuit-ideal image includes mapping boundary condition voltage-drop points from the actual implementation of the integrated circuit to provide data points for corresponding regions of the circuit-ideal image.

6. The method of claim 5, wherein the step of mapping further includes using an algorithm to map intervening ideal voltage-drop points for intervening regions of the circuit-ideal image.

7. The method of claim 6, wherein the algorithm is a function of a Laplacian algorithm.

8. The method of claim 1, further including assigned weighted values to the voltage-drop data points of at least one of the circuit-representative image and circuit- ideal image, and wherein the step of comparing includes using a subtraction of the weighted values.

9. The method of claim 8, wherein the assigned weighted values vary as a function of the voltage-drop data point's proximity to the center of said at least one of the circuit-representative image and the circuit-ideal image.

10. The method of claim 1, wherein the step of comparing includes analyzing voltage-drop data corresponding to the circuit-representative image.

11. The method of claim 10, wherein the step of analyzing voltage-drop data corresponding to the circuit-representative image includes comparing the points in the voltage-drop data to corresponding voltage-drop data for the circuit-ideal image.

12. The method of claim 11 , further including using results from the step of analyzing to form a histogram.

13. The method of claim 12, wherein the step of determining whether the power distribution in the integrated circuit satisfies a predetermined power distribution condition includes examining the histogram.

14. The method of claim 1, wherein the circuit- ideal image contains a color gradient indicative of a voltage drop for the integrated circuit.

15. The method of claim 14, wherein the voltage drop for the integrated circuit corresponds to the actual voltage drop across the integrated circuit.