JP2009516255A - Analysis method of voltage drop in power distribution in integrated circuit - Google Patents

Abstract

An automatic voltage drop analysis method for integrated circuit power distribution includes comparing the actual voltage drop image data with the predicted ideal voltage drop image data for the ideal version of the IC. The method includes representing actual voltage drop data for power distributed across the integrated circuit using a circuit representation image corresponding to the actual implementation of the integrated circuit. Next, ideal voltage drop data relating to power distributed over the entire area of the integrated circuit is represented using a circuit ideal image corresponding to an ideal implementation of the integrated circuit. The actual voltage drop data is compared with the ideal voltage drop data, and according to the comparison, it is determined whether the power distribution in the integrated circuit satisfies a predetermined power distribution condition.

Description

  The present invention is generally directed to a voltage drop in an integrated circuit and an analysis method for its improved circuit design.

  Integrated circuits (ICs) continue to become more complex to operate at higher data processing speeds with increasing density in smaller IC packages. In addition to such complexity, there is an ever increasing demand for reducing power consumption without affecting the power distribution in the circuit. To meet these performance requirements, modern IC designers have a variety of tools including, for example, computer aided design (CAD) tools that can help accelerate IC development time by automating most of the design process. To simplify the design process. This reduces the time and cost required to develop ICs and helps designers create more competitive products in the market.

  One design consideration for reducing the size of IC components is the voltage drop across the IC. In general, an external power supply source is connected to an internal die circuit via a power supply pad cell via a lead pin and a bond pad directly connected to the die. Typically, a thin metal wire power-bus grid is mainly used to transfer power from the power pad cell to the die circuit through the core.

  The power distributed to the die circuit via the power bus grid can present a significant problem to the IC designer. For example, if the circuit is intended to operate at a relatively low level voltage, a slight voltage drop can result in poor operation. Such a voltage drop in the region of the wire or die is proportional to the amount of current conducted by the wire or region as well as the corresponding internal resistance.

  Therefore, the internal resistance in the power distribution structure of an IC is the subject of many scrutiny and critical studies to ensure that no more than a sufficient amount of power routing is provided, or the designer can Must guess about the amount of power routing. To avoid these failures, IC designers attempt to manage the voltage (or “IR”) drop through the design process from the design stage to the commercially mounted die. If it is not feasible to test an actual die early in the design process, static analysis can provide useful information to the designer to make important design decisions.

  In order to support such static analysis, various types of CAD tools are commercially available. One commercially available tool in this regard is a power distribution / power grid inspection CAD tool such as the VoltageStorm ™ sold by Cadence, San Jose, California. This type of tool allows the IC designer to draw IC power consumption data statically and dynamically into an image for analysis by the IC designer. The image is color coded to indicate where the circuit consumes a relatively large amount of power distributed. Various applications of such tools are described, for example, in US Pat. No. 6,725,434 (method for verifying design circuits), US Pat. No. 5,872,952 (analysis of integrated circuit power networks via simulation), and US Pat. No. 6,675,139 (power bus analysis based on plan view and integrated circuit design tool).

  Like many CAD tools, the power verification tools described above do not provide detailed circuit analysis. For many design applications, such tools still require the IC designer to infer whether a power distribution design is appropriate for each circuit specification. Such speculations often expose ICs to a wide variety of problems that are difficult to identify and mitigate. To overcome such limitations, as well as time and other engineering costs, standard means have overdesigned IC power routing by using extremely conservative power estimates when designing power bus grids. It was. Designers typically avoid the voltage drop problem by multiplying the amount of current estimated to flow through the power bus grid by a buffer factor. These conservative estimates generally yield an integrated circuit that is significantly larger than what is actually needed to distribute power in the IC.

  One aspect of the present invention is directed to a method for analyzing voltage drop data in an integrated circuit using a signal processing imaging algorithm. These and other aspects of the invention are illustrated in a number of illustrated implementations and applications, some of which are illustrated in the drawings and set forth in the following claims section.

  Various aspects of the present invention are applicable to methods for automatically analyzing voltage drops in the power distribution of an integrated circuit. The method includes showing actual voltage drop data for power distributed across the integrated circuit using circuit representation images corresponding to the actual implementation of the integrated circuit. Next, ideal voltage drop data relating to power distributed over the entire area of the integrated circuit is represented using a circuit ideal image corresponding to an ideal implementation of the integrated circuit. The actual voltage drop data is compared with the ideal voltage drop data, and according to the comparison, it is determined whether the power distribution in the integrated circuit satisfies a predetermined power distribution condition.

  Another aspect of the invention is directed to means for assuming the presence of a linear, spatial invariant, equivalent IC image. The voltage drop slope of this ideal IC image data is calculated and then compared with the actual IC voltage drop data image results. Voltage drop data is acceptable if the values of the corresponding data points between the actual and ideal images are close. If the value of the corresponding data point deviates sufficiently from the predetermined threshold, the voltage drop is unacceptable.

  The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The following drawings and detailed description illustrate these embodiments in more detail.

  The invention will be more fully understood in view of the following detailed description of various embodiments of the invention in connection with the accompanying drawings.

  While the invention is amenable to various modifications and alternative forms, specific examples thereof have been shown in the drawings for purposes of illustration and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is intended to cover all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.

  The present invention is believed to be useful for IC designs that are effective and have an appropriate power distribution. The present invention need not be limited to such applications, and various aspects of the present invention will be appreciated through consideration of various embodiments using the text of this specification.

  For embodiments of the present invention, a method for automatically analyzing voltage drops in the power distribution of an integrated circuit is used. The method includes representing actual voltage drop data for power distributed across the integrated circuit using a circuit representation image corresponding to the actual implementation of the integrated circuit. The ideal voltage drop data relating to the power distributed over the entire area of the integrated circuit is represented using a circuit ideal image corresponding to the ideal implementation of the integrated circuit. The circuit ideal image can be developed by various means including, for example, creating and completing other parts of the circuit ideal image using some of the actual or approximate voltage drop data as a basis. The actual voltage drop data is compared with the ideal voltage drop data, and according to the comparison, it is determined whether the power distribution in the integrated circuit satisfies a predetermined power distribution condition.

  A voltage drop (also known as IR drop) mapping tool is used to ensure that sufficient power is delivered through the IC. Such tools typically create an image of an IC having a color gradient display with IR drop dispersion across the IC. Ideally, IR drop is expected to be minimal near the IC edge and power distribution is expected to be maximal near the IC center furthest from the IC edge. Therefore, in an assumed situation where the IC power distribution region corresponds to a concentric circle, an ideal IR drop dispersion image must look like a target pattern (or target) on the dart board. If the actual IR drop data image deviates from this ideal pattern, the discrepancy makes IR drop determination difficult. By comparing the actual voltage drop data with the ideal voltage drop data, the present invention visually evaluates the image and is capable of subjective (using art-like techniques) design improvements and Reduce the possibility of errors by IC designers attempting to determine if they are necessary. This automated (eg computer aided) determination of this data reduces the variance and error in their interpretation.

  In many IC applications, properly automating such analysis is because the data points in the IR drop image are neither equally spaced or evenly distributed (because electronic elements are not equally spaced or evenly distributed). So) difficult. According to another aspect, the present invention is directed to automatically calculating gradients from such irregularly spaced and dense IR drop data points. In more specific applications, such automated computations use modern digital / discrete signal processing (hardware and / or software) tools that use arithmetic logic operations for high speed processing in addition to linear, space invariant constraints. Including.

  FIG. 1 illustrates a method for mapping IR drop data points to create an ideal IR drop image for use in automatically analyzing actual IR drop data in accordance with one embodiment of the present invention. The method includes creating an IR drop image of the actual circuit. The image uses color gradients to show the regions that change the voltage drop, and in FIG. 1 these color gradients are shown using oblique parallel shadows. For example, the maximum voltage drop occurs in the shaded area 112, the next largest voltage drop occurs in the diagonal area 114, the next largest voltage drop occurs in the area 116 with the horizontal line, and the minimum amount of voltage drop across the die. A region having a vertical line 118 occurs. The voltage drop near the center of the actual IR drop image is generally the worst case voltage drop for the die. In order to compare the actual IR drop image with the ideal data, an ideal IR drop image 120 must be created. The ideal die image corresponds to the actual image structure and circuit specifications that must be provided to the mapping tool 122.

  An ideal IR drop image is created by mapping a boundary condition point that includes the point that supplies the supply voltage to the IC in a representative manner, eg, mapping point A to the ideal IR drop image as point A ′. . In certain aspects, these boundary condition data points also include points from actual voltage drop images experiencing the maximum voltage drop in the IC. The mapping can incorporate grid coordinates because the structure of both the actual image and the ideal image is identical, and the mapping is the data point location and the voltage drop data value at that location. Includes both.

  According to one specific method, an ideal IR drop image is completed using Laplacian of such boundary condition data points. In this method, the image is formed so that the 2-D derivative of the image having the above-described suppression does not have a break. Next, the position of the corresponding data point in the intervening region is mapped to an ideal IR drop image, for example C is mapped to C '.

  In order to analyze the actual IR drop image, each point in the actual IR drop image is compared with the value at that point of the ideal IR drop image, and the resulting scalar value is used to form a histogram. All values except the predetermined variance from the central maximum portion of the histogram are marked by software for additional inspection by the IC designer. This analysis can be further aided by weighting the data points to use a single predetermined variance. If none of the data points are marked, the IC is determined to meet the power requirements of the IC specification.

  Referring to the flowchart of FIG. 2, ideal IR drop image data is created for comparison with actual IR drop image data. At block 210, an IR drop image of the actual die to be tested is created using the mapping tool. One commercially available mapping tool is the Cadence Voltage Storm ™ described above. At block 220, an initial ideal IR drop image of the corresponding ideal die is created using the actual IC circuit specifications and boundary condition IR drop data points. These boundary condition IR drop data points are data points generally along the edge of the die to which power is supplied and data points located near the center of the die. At block 230, the initial ideal IR drop image is modified using the Laplacian of the boundary condition IR data points to identify the data points in the region between the ideal die edge and center. At block 240, the ideal IR drop image data mapping is completed by filling in the identified intervening data points. Optionally, at block 250, a numerical comparison for IR drop data points can be adjusted to perform a weighted comparison. Thus, a single dispersion threshold can be used for each analyzed IR drop data point, and the data points near the center of these images are recognized as more sensitive. Next, the actual IR drop image data is compared with the ideal IR drop image data in block 260 step by step. At block 270, the actual IR drop data point is marked if the data point on the actual IC IR drop image does not fall within the predetermined threshold of the corresponding ideal data point. If the data point is not marked, the die is considered to comply with the IC power specifications and the analysis is complete at block 280. However, if the data point was marked on the actual IR drop image, the IC designer analyzes the marked data point and redesigns or reroutes the IC power grid at block 290. Evaluate whether or not.

  While particular aspects of the present invention have been described with reference to several detailed embodiments, those skilled in the art will recognize that many modifications can be made without departing from the spirit and scope of the invention. Aspects of the invention are set out in the following claims.

FIG. 4 is a data flow diagram illustrating the use of an actual voltage drop circuit image and an ideal voltage drop circuit image according to an embodiment of the present invention. 2 is a flowchart illustrating an embodiment of a method for analyzing a voltage drop using an image as shown in FIG. 1 according to an embodiment of the present invention.

Claims (15)

In automatically analyzing the voltage drop in the power distribution of an integrated circuit,
Represents actual voltage drop data for power distributed across the integrated circuit using circuit representation images corresponding to the actual implementation of the integrated circuit,
Represents ideal voltage drop data for power distributed across the integrated circuit using circuit ideal images corresponding to the ideal implementation of the integrated circuit,
Comparing the actual voltage drop data with the ideal voltage drop data;
A method for analyzing a voltage drop, comprising: determining whether a power distribution in the integrated circuit satisfies a predetermined power distribution condition according to the comparison.   The method of claim 1, further comprising creating a circuit representation image using voltage drop mapping means.   The method of claim 1, wherein the circuit ideal image of the integrated circuit is based on a comparable linear spatial invariant distribution of voltage drop data. Further comprising creating the circuit ideal image,
The step of creating the circuit ideal image includes a boundary condition voltage drop point that includes a point at which a power supply voltage is applied and a point at or near the center of the image of the actual mounting. 4. The method of claim 3, comprising mapping to one boundary region and a central region. Further comprising creating the circuit ideal image,
4. The method of claim 3, wherein creating the circuit ideal image includes mapping boundary condition voltage drop points from an actual implementation of the integrated circuit to provide data points for corresponding regions of the circuit ideal image. .   The method of claim 5, wherein the mapping step further comprises mapping an intervening ideal voltage drop point with respect to an intervening region of the circuit ideal image using an algorithm.   The method of claim 6, wherein the algorithm is a function of a Laplace algorithm. A weight assigned to at least one of the voltage drop data points of the circuit representation image and the circuit ideal image,
The method of claim 1, wherein the comparing step includes using subtraction of the weight values.   9. The method of claim 8, wherein the assigned weight value varies as a function of a voltage drop data point proximity to at least one center of the circuit representation image and the circuit ideal image.   The method of claim 1, wherein the step of comparing includes analyzing voltage drop data corresponding to the circuit representation image.   The method of claim 10, wherein analyzing the voltage drop data corresponding to the circuit representation image comprises comparing a point in the voltage drop data with corresponding voltage drop data for the circuit ideal image.   The method of claim 11, further comprising forming a histogram using results from the analyzing step.   The method of claim 12, wherein determining whether a power distribution in the integrated circuit satisfies a predetermined power distribution condition comprises examining a histogram.   The method of claim 1, wherein the circuit ideal image includes a color gradient display of a voltage drop for the integrated circuit.   The method of claim 14, wherein the voltage drop for the integrated circuit corresponds to an actual voltage drop across the integrated circuit.

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