EP1911188B1 - Asynchronous data buffer - Google Patents

Asynchronous data buffer Download PDF

Info

Publication number
EP1911188B1
EP1911188B1 EP06780170A EP06780170A EP1911188B1 EP 1911188 B1 EP1911188 B1 EP 1911188B1 EP 06780170 A EP06780170 A EP 06780170A EP 06780170 A EP06780170 A EP 06780170A EP 1911188 B1 EP1911188 B1 EP 1911188B1
Authority
EP
European Patent Office
Prior art keywords
data
input
valid bit
output
burst
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Not-in-force
Application number
EP06780170A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP1911188A1 (en
Inventor
Robert Gruijl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of EP1911188A1 publication Critical patent/EP1911188A1/en
Application granted granted Critical
Publication of EP1911188B1 publication Critical patent/EP1911188B1/en
Not-in-force legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/005—Correction by an elastic buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Definitions

  • This invention relates generally to interfacing techniques between two systems, and in particular to an asynchronous data buffer for data transfer between two systems linked to asynchronous clock domains.
  • asynchronous interfaces also have disadvantages such as extra latency for data synchronization and increased probability of data corruption during data transfer.
  • Data corruption occurs because of metastability across an asynchronous interface.
  • State of the art concepts are two-stage synchronizers and two-phase handshake methods. However, these concepts have an undesirable trade-off between performance and reliability, or use complicated synchronization logic substantially increasing the complexity of the system.
  • Recent technologies utilize a data valid bit to reduce the risk of a metastable condition.
  • US Patent 6,516,420 Audityan et al teach valid bits used to synchronize individual data elements, which are reset after each transaction is done using a data sampler.
  • an object of the invention to provide an asynchronous data buffer that is more efficient and has a higher data throughput by substantially reducing latency.
  • an asynchronous data buffer for transferring m data elements of a burst-transfer between two asynchronous systems.
  • the asynchronous data buffer comprises a data input port for receiving the m data elements of a data burst from a sending system and a data memory in communication therewith for storing the m data elements, wherein each data element is stored at a predetermined address location.
  • a valid bit memory m input valid bits are stored, wherein each input valid bit is stored at a predetermined address location corresponding to the predetermined address location of a respective data element.
  • Input control logic circuitry in control communication with the data memory and the valid bit memory determines the address locations, creates the m input valid bits, and provides an input control signal for inverting the input valid bits of a following data burst.
  • Output control logic circuitry in communication with the data memory, the valid bit memory and a valid bit output port, the output control logic circuitry controls reading of the m data elements and provision of the same to a receiving system, creates m output valid bits based upon the m input valid bits and an output control signal, the m output valid bits for provision to the receiving system, and inverts control logic circuitry in control communication with the data memory and the valid bit memory.
  • asynchronous data buffer In order to provide a better understanding of the asynchronous data buffer according to the invention and its operation, communication between two systems using an example embodiment of the asynchronous data buffer will be described in the following with reference to Fig. 1 .
  • a handshake protocol is implemented. Before the sending system A starts sending data to the receiving system B, the receiving system B needs to be ready to receive the data, or at least a portion of the data if not all data are lost. As shown in Fig.
  • the sending system A requests a data transfer by sending a handshake signal hs_A and waits with the data transfer until the receiving system B has acknowledged that it is ready for receiving the data by sending handshake signal hs_B to the sending system A.
  • burst-transfers are used, i.e. multiple data elements are sent when a data transfer has been acknowledged by the receiving system B instead of performing a handshake for every individual data element.
  • the receiving system B acknowledges that it is ready to receive m n-bit data elements when it sends the handshake signal hs_B.
  • an asynchronous data buffer 100 is interposed between the sending system A and the receiving system B.
  • the sending system A transfers the m data elements to the data buffer 100 for storage in memory thereof by sending for each of the m data elements a write enable signal WE and the data element on dout[n].
  • the sending system A and the receiving system B need to access the data buffer 100 simultaneously, i.e. the receiving system B does not wait reading the data elements until the sending system A has completed writing the m data elements into the memory of the data buffer 100.
  • the receiving system B does not wait reading the data elements until the sending system A has completed writing the m data elements into the memory of the data buffer 100.
  • data-loss or data-corruption will likely occur due to metastability problems.
  • This problem is overcome by creating a valid bit each time a data element is stored in the memory of the data buffer indicating to the receiving system B that the stored data element belongs to the current burst-transfer of m data elements as acknowledged by the handshake signals hs_A and hs_B.
  • Fig. 2 illustrates in a block diagram an example embodiment of an asynchronous data buffer 100 according to the invention.
  • the data buffer 100 comprises data input port 102 and write enable input port 104 for being connected to the sending system A, and data output port 106, read enable input port 108 and valid bit output port 110 for being connected to the receiving system B.
  • the data buffer 100 comprises two portions: a data input portion - left hand side - for being connected to the sending system A and, therefore, for being linked to the clock domain clk_A; and a data output portion - right hand side - for being connected to the receiving system B and, therefore, for being linked to the clock domain clk_B.
  • the data input port 102 is connected to a data input port D of data memory 112 - preferably a RAM having storage space for m data elements of n bits each, i.e. a maximum possible size of a burst-transfer between the systems A and B.
  • the write enable input port 104 is connected to a write enable input port WE of the data memory 112, to a write enable input port WE of valid bit memory 114 - preferably an m-bit RAM, and to input control logic circuitry 116.
  • the input control logic circuitry 116 is connected to an address input port A of the data memory 112 and to an address input port A of the valid bit memory 114 for provision of logic signals thereto.
  • the input control logic circuitry 116 comprises an input counter 118 such as a binary address counter and an input valid bit generator, which is a combination of an input toggle flip-flop 120 with an input XOR gate 122.
  • the input counter 118 comprises an E input port connected to the write enable input port 104, a Q output port connected to the address input ports A of the memories 112 and 114, respectively, and a C output port connected to an E input port of the input toggle flip-flop 120.
  • the input XOR gate 122 comprises a first and a second input port connected to the write enable input port 104 and a Q output port of the toggle flip-flop 120, respectively, and an output port connected to a data input port D of the valid bit memory 114.
  • the counter 118 is incrementing a first input logic signal and a following empty location in the memory 112 is addressed by transmitting the first input logic signal to the address input port A of the memory 112.
  • an input valid bit - a binary 0 or 1 - is created in the input XOR gate 122 based on a second input logic signal received from the input toggle flip-flop 120 and the write enable signal WE, which is then stored in the valid bit memory 114 with the address location corresponding to the address location of the data element being controlled by the first input logic signal.
  • the write enable signal WE being always a same, preferably, binary signal 0 or 1 and the input toggle flip-flop 120 producing a same, preferably, binary signal 0 or 1.until a third input logic signal is received from the input counter 118 a same input valid bit is created.
  • the input counter 118 loops back and sends the third input logic signal to the input toggle flip-flop 120.
  • the input toggle flip-flop 120 Upon receipt of the third input logic signal the input toggle flip-flop 120 produces an inverted second input logic signal, which results in the input XOR gate 122 producing an inverted input valid bit - changing from a binary 0 to a binary 1 or vice versa. Therefore, after each burst-transfer of m data elements the input valid bit is inverted, automatically rendering all data elements of a previous burst-transfer invalid.
  • the data output portion of the data buffer 100 comprises valid bit synchronization circuitry 123, valid bit multiplexer 124, output data multiplexer 125, and output control logic circuitry 126.
  • the valid bit synchronization circuitry 123 is connected to a data output port Q of the valid bit memory 114 and data input ports of the valid bit multiplexer 124, and comprises in the example embodiment m parallel two stage synchronizers synch[1] to synch[m] - one synchronizer for each of the m input valid bits corresponding to the m data elements - with each two stage synchronizer comprising two flipflops 123A and 123B connected in series, and with the first flipflop 123A for being linked to the clock domain clk_A of the sending system A and the second flipflop 123B for being linked to the clock domain clk_B of the receiving system B.
  • the valid bit synchronization circuitry 123 synchronizes the input valid bits to the clock domain clk_B of the receiving system B.
  • Data input ports of the valid bit multiplexer 124 are connected to the valid bit synchronization circuitry 123, while a data output port and a control logic input port are connected to the output control logic circuitry 126.
  • the valid bit multiplexer 124 transfers an input valid bit from one of the m synchronizers synch[1] to synch[m].
  • Data input ports of the output data multiplexer 125 are connected to data output port Q of the data memory 112, a data output port of the output data multiplexer 125 is connected to the data output port 106, and a control logic input port is connected the output control logic circuitry 126.
  • the data multiplexer 125 transfers one of the m data elements from a corresponding address location in the data memory 112.
  • the output control logic circuitry 126 is of a similar structure as the input control logic circuitry 116, and comprises an output counter 128 such as a binary address counter and a combination of an output toggle flip-flop 130 with an output XOR gate 132.
  • the output counter 128 comprises an E input port connected to the read enable input port 108, a Q output port connected to the control logic input ports of the multiplexers 124 and 125, respectively, and a C output port connected to an E input port of the output toggle flip-flop 130.
  • the output XOR gate 132 comprises a first and a second input port connected to the data output port of the valid bit multiplexer 124 and a Q output port of the output toggle flip-flop 130, respectively, and an output port connected to the valid bit output port 110.
  • the output counter 128 is incrementing a first output logic signal and a following location in the memory 112 is addressed by transmitting the first output logic signal to the control logic input port of the data multiplexer 125.
  • an output valid bit - a binary 0 or 1 - is created in the XOR gate based on a second output logic signal received from the output toggle flip-flop 130 and the input valid bit received from the valid bit multiplexer 124, which is then transferred to the valid bit output port 110, with provision of the input valid bit being controlled by the first output logic signal provided to the valid bit multiplexer 124.
  • the output toggle flip-flop 130 With the input valid bit being a same for m data elements of a burst transfer and the output toggle flip-flop 130 producing a same, preferably, binary signal 0 or 1 until a third output logic signal is received from the output counter 128 a same output valid bit is created.
  • the output counter 128 After m read enable signals RE corresponding to m data elements have been received, the output counter 128 loops back and sends the third output logic signal to the output toggle flip-flop 130.
  • the output toggle flip-flop 130 Upon receipt of the third output logic signal the output toggle flip-flop 130 produces an inverted second output logic signal.
  • the output XOR 132 Receiving an inverted input valid bit and the inverted second output logic signal, the output XOR 132 produces in a following burst transfer a same output valid bit for provision to the receiving system B. Therefore, the data buffer 100 according to the invention inverts after each burst transfer of m data elements the input valid bit internally, automatically rendering all data elements of a previous bur
  • FIG. 3 a simplified flow diagram of a method for transferring m data elements of a burst-transfer using an asynchronous data buffer according to the invention is shown.
  • the method will be described in two portions related to the input and the output portion of the asynchronous data buffer.
  • the two portions will be performed simultaneously once the first valid bit - indicating that the first data element of the burst-transfer has been stored in the data memory - is detected.
  • a first write enable signal WE and a first of m data elements of a burst-transfer are received from the sending system A.
  • the first data element is then stored - box 12 - at a first address location in the data memory 112.
  • a first input valid bit is created and stored at a first address location in the valid bit memory 114 - box 14.
  • the write enable signal WE is further used for incrementing the address location - box 16.
  • the above steps indicated by boxes 10 to 16 are then repeated until the m th write enable signal WE and the m th data element have been received - box 18.
  • the m th data element is stored at the m th address location in the data memory 112 - box 20.
  • an m th input valid bit is created and stored at the m th address location in the valid bit memory 114 - box 22.
  • the m th write enable signal WE is used to loop back to the first address location and to invert the input control signal resulting in an inverted input valid bit for the following burst-transfer - box 24.
  • a first read enable signal RE is received from the receiving system B.
  • the first input valid bit is then retrieved from the first address location of the valid bit memory 114 - box 32.
  • This step is followed by the generation of a first output valid bit using the first input valid bit and an output control signal and provision of the same to the receiving system B - box 34.
  • the first data element is retrieved from the first address location in the data memory 112 and provided to the receiving system B - box 36.
  • the address location is incremented - box 38. The above steps indicated by boxes 30 to 38 are then repeated until the m th read enable signal RE has been received - box 40.
  • the m th input valid bit is then retrieved from the m th address location of the valid bit memory 114 - box 42. This step is followed by the generation of the m th output valid bit using the m th input valid bit and the output control signal and provision of the same to the receiving system B - box 44.
  • the m th data element is retrieved from the m th address location in the data memory 112 and provided to the receiving system B - box 46.
  • the mth read enable signal RE is used to loop back to the first address location and to invert the output control signal, resulting in a same output valid bit when processed together with the inverted input valid bit during the following burst-transfer - box 48.
  • the asynchronous data buffer 100 is highly advantageous by individually synchronizing data elements of a burst-transfer between two asynchronous systems with valid bits that are inverted after each burst-transfer. Therefore, the asynchronous data buffer 100 allows simultaneous access for the sending as well as the receiving system with reduced risk of metastability problems, while latency is substantially reduced by obviating the need for clearing or resetting of the valid bits. Furthermore, the asynchronous data buffer 100 is easily implemented due to a simple design having a low gate count and the substantially same design of the input control logic circuitry 116 and the output control logic circuitry 126, substantially decreasing design and manufacturing cost.
  • the asynchronous data buffer 100 is integrated together with one of the systems A and B on a single semiconductor chip.
  • the asynchronous data buffer 100 is highly beneficial in system bus implementations that allow burst-transfers between two asynchronous systems. Knowing system requirements for the burst-transfer, it is possible to design the asynchronous data buffer 100 on a computer by executing commands based on the above description stored on a storage medium.
  • the implementation of the asynchronous data buffer 100 according to the invention has been illustrated using an example embodiment, but as is evident, is not limited thereto. There are numerous possibilities for implementing inversion of the input valid bits and generating same output valid bits.
  • the logic circuits of the asynchronous data buffer 100 are easily adapted to produce other logic signals as input and output valid bits then the binary 0 and 1 disclosed in combination with the example embodiment.
  • the logic circuits of the asynchronous data buffer 100 are adapted to receive one write enable and/or read enable signal for successively writing and/or reading the m data elements controlled, for example, by the clock signals clk_A and elk_B.
  • the implementation shown in Fig. 2 comprises edge triggered logic components triggered by a rising clock pulse edge, but as is evident, it is also possible to use a falling clock pulse edge.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
EP06780170A 2005-07-22 2006-07-21 Asynchronous data buffer Not-in-force EP1911188B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US70205305P 2005-07-22 2005-07-22
US73545605P 2005-11-10 2005-11-10
PCT/IB2006/052514 WO2007010502A1 (en) 2005-07-22 2006-07-21 Asynchronous data buffer

Publications (2)

Publication Number Publication Date
EP1911188A1 EP1911188A1 (en) 2008-04-16
EP1911188B1 true EP1911188B1 (en) 2011-10-19

Family

ID=37451210

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06780170A Not-in-force EP1911188B1 (en) 2005-07-22 2006-07-21 Asynchronous data buffer

Country Status (6)

Country Link
US (1) US7899955B2 (ja)
EP (1) EP1911188B1 (ja)
JP (1) JP2009503640A (ja)
CN (1) CN101228733B (ja)
AT (1) ATE529966T1 (ja)
WO (1) WO2007010502A1 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8205110B2 (en) * 2008-11-03 2012-06-19 Oracle America, Inc. Synchronous operation of a system with asynchronous clock domains
CN102207919A (zh) * 2010-03-30 2011-10-05 国际商业机器公司 加速数据传输的处理单元、芯片、计算设备和方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5084837A (en) * 1988-01-22 1992-01-28 Sharp Kabushiki Kaisha Fifo buffer with folded data transmission path permitting selective bypass of storage
US5781802A (en) * 1995-02-03 1998-07-14 Vlsi Technology, Inc. First-in-first-out (FIFO) controller for buffering data between systems which are asynchronous and free of false flags and internal metastability
US5898893A (en) * 1995-10-10 1999-04-27 Xilinx, Inc. Fifo memory system and method for controlling
US5884099A (en) * 1996-05-31 1999-03-16 Sun Microsystems, Inc. Control circuit for a buffer memory to transfer data between systems operating at different speeds
US5956748A (en) * 1997-01-30 1999-09-21 Xilinx, Inc. Asynchronous, dual-port, RAM-based FIFO with bi-directional address synchronization
US6058439A (en) * 1997-03-31 2000-05-02 Arm Limited Asynchronous first-in-first-out buffer circuit burst mode control
JP3545908B2 (ja) * 1997-06-25 2004-07-21 株式会社リコー データ処理装置
US6055285A (en) * 1997-11-17 2000-04-25 Qlogic Corporation Synchronization circuit for transferring pointer between two asynchronous circuits
US6141691A (en) * 1998-04-03 2000-10-31 Avid Technology, Inc. Apparatus and method for controlling transfer of data between and processing of data by interconnected data processing elements
US6516420B1 (en) * 1999-10-25 2003-02-04 Motorola, Inc. Data synchronizer using a parallel handshaking pipeline wherein validity indicators generate and send acknowledgement signals to a different clock domain
US6519688B1 (en) * 2000-09-29 2003-02-11 S3 Incorporated Read data valid loop-back for high speed synchronized DRAM controller
US6880050B1 (en) * 2000-10-30 2005-04-12 Lsi Logic Corporation Storage device, system and method which can use tag bits to synchronize queuing between two clock domains, and detect valid entries within the storage device
US6931561B2 (en) * 2001-10-16 2005-08-16 International Business Machines Corporation Apparatus and method for asynchronously interfacing high-speed clock domain and low-speed clock domain using a plurality of storage and multiplexer components
JP4095317B2 (ja) * 2002-03-14 2008-06-04 富士通株式会社 非同期式半導体記憶装置、非同期式半導体記憶装置の内部制御方法及びシステム

Also Published As

Publication number Publication date
US7899955B2 (en) 2011-03-01
EP1911188A1 (en) 2008-04-16
ATE529966T1 (de) 2011-11-15
CN101228733A (zh) 2008-07-23
JP2009503640A (ja) 2009-01-29
CN101228733B (zh) 2011-10-12
WO2007010502A1 (en) 2007-01-25
US20080201499A1 (en) 2008-08-21

Similar Documents

Publication Publication Date Title
JP3856696B2 (ja) ２倍データ速度同期式動的ランダムアクセスメモリのための構成可能同期装置
US7555590B2 (en) Fast buffer pointer across clock domains
US6249875B1 (en) Interface circuit using plurality of synchronizers for synchronizing respective control signals over a multi-clock environment
JP4091941B2 (ja) クロック同期回路
US8520464B2 (en) Interface circuit and semiconductor device incorporating same
JP2000099193A (ja) 同期装置および同期方法ならびにインタフェ―ス回路
JP4634803B2 (ja) データ取得の方法と装置
US6424688B1 (en) Method to transfer data in a system with multiple clock domains using clock skipping techniques
US5539739A (en) Asynchronous interface between parallel processor nodes
JP3645584B2 (ja) データ転送同期装置
JPH09222988A (ja) コンピュータシステム及び第１の回路と第２の回路との間でデータを転送するインタフェース回路
EP2628157A1 (en) Memory subsystem for counter-based and other applications
US7224638B1 (en) Reliability clock domain crossing
CN104380273B (zh) 基于环形缓冲器的数据的自适应偏移同步
US8176353B2 (en) Method for the data transfer between at least two clock domains
US6546451B1 (en) Method and apparatus for decoupling processor speed from memory subsystem speed in a node controller
CN107066419B (zh) 可扩展的自适应n×n通道数据通信系统
EP1911188B1 (en) Asynchronous data buffer
US6640277B1 (en) Input staging logic for latching source synchronous data
US7392406B2 (en) Circuit and method for generating clock signals for clocking digital signal processor and memory
US6952791B2 (en) Method and circuit for initializing a de-skewing buffer in a clock forwarded system
US20040064660A1 (en) Multiplexed bus with multiple timing signals
US20080183948A1 (en) Flash memory system with higher data transmission rate and method thereof
US6760392B1 (en) Method and apparatus to provide fixed latency early response in a system with multiple clock domains with fixable clock ratios
US6557064B1 (en) Set up time adjust

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20080222

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR

17Q First examination report despatched

Effective date: 20100317

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR

DAX Request for extension of the european patent (deleted)
REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602006025273

Country of ref document: DE

Effective date: 20111222

REG Reference to a national code

Ref country code: NL

Ref legal event code: VDEP

Effective date: 20111019

LTIE Lt: invalidation of european patent or patent extension

Effective date: 20111019

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 529966

Country of ref document: AT

Kind code of ref document: T

Effective date: 20111019

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111019

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120219

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111019

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111019

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120220

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111019

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111019

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120120

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111019

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111019

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111019

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111019

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111019

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120119

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111019

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111019

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111019

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111019

26N No opposition filed

Effective date: 20120720

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602006025273

Country of ref document: DE

Effective date: 20120720

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111019

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120731

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120731

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20120130

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120731

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

REG Reference to a national code

Ref country code: DE

Ref legal event code: R081

Ref document number: 602006025273

Country of ref document: DE

Owner name: PARTNERS FOR CORPORATE RESEARCH CV, KY

Free format text: FORMER OWNER: NXP B.V., EINDHOVEN, NL

Effective date: 20130322

Ref country code: DE

Ref legal event code: R081

Ref document number: 602006025273

Country of ref document: DE

Owner name: PARTNERS FOR CORPORATE RESEARCH CV, GEORGE TOW, KY

Free format text: FORMER OWNER: NXP B.V., EINDHOVEN, NL

Effective date: 20130322

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111019

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120721

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20130717

Year of fee payment: 8

Ref country code: FR

Payment date: 20130724

Year of fee payment: 8

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111019

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120721

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20060721

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20140721

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20150331

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20140731

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20140721

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20170724

Year of fee payment: 12

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 602006025273

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190201