Classifications

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  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3648—Control of matrices with row and column drivers using an active matrix
  • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
• • G—PHYSICS
  • G02—OPTICS
  • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
  • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
  • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
  • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
  • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3648—Control of matrices with row and column drivers using an active matrix
  • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/04—Structural and physical details of display devices
  • G09G2300/0404—Matrix technologies
  • G09G2300/0408—Integration of the drivers onto the display substrate
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/04—Structural and physical details of display devices
  • G09G2300/0421—Structural details of the set of electrodes
  • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
  • G09G2300/0809—Several active elements per pixel in active matrix panels
  • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
  • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/06—Details of flat display driving waveforms
  • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/06—Details of flat display driving waveforms
  • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
  • G09G2310/062—Waveforms for resetting a plurality of scan lines at a time
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/06—Details of flat display driving waveforms
  • G09G2310/065—Waveforms comprising zero voltage phase or pause
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2320/00—Control of display operating conditions
  • G09G2320/02—Improving the quality of display appearance
  • G09G2320/0252—Improving the response speed
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/2007—Display of intermediate tones
  • G09G3/2011—Display of intermediate tones by amplitude modulation

Definitions

• the present invention relates to an active matrix for liquid crystal display devices.
• bistable nematic liquid crystal display devices usually called BiNem® devices.
• BiNem® devices bistable nematic liquid crystal display devices
• the bistable nematic displays are used in various applications, and more particularly in nomadic applications.
• mobile phones or handheld computers such as organizers, generally designated by the acronym PDA for Personal Digital Assistant, or the "electronic readers” French translation devoted to the Anglo-Saxon term e -book, more commonly used.
• bistable nematic displays have the particularly interesting property of not requiring image refresh, which is very favorable for all these nomadic applications, for which we seek to minimize consumption. They offer a high image quality independent of the number of lines.
• bistable nematic displays are mainly so-called passive matrix: each pixel is controlled directly by a line signal and a column signal.
• the disadvantage of passive matrices is that the pixel of a column "sees" all the signals applied to each of the pixels of the column during the display time of an image. This makes the use of this technology problematic for large screens. In addition, switching is slow, rendering this technology unusable for video applications.
• passive matrix displays are more particularly suitable for applications where the image changes little or slowly, and small sizes, typically for e-book type applications.
• active matrix is meant a matrix structure of pixel electrodes, in which the addressing goes through a switching device associated with each pixel electrode. When a pixel is not addressed, the associated switching device isolates the pixel electrode line and column signals (to coupling problems with near parasitic capacitances).
• the switching device may be a diode or a transistor.
• This is advantageously a standard transistor type TFT (Thin Film Transistor), which uses a thin layer of amorphous silicon (a-Si).
• a-Si amorphous silicon
• these transistors have the advantage over the polycrystalline silicon transistor of having a zero or very low leakage current, which is a very important feature for maintaining the information on the TN-type pixels.
• the active matrix comprising the pixel electrodes, the switching devices, the row and column conductors, is formed on a first substrate.
• the display comprises in addition to the active matrix, a second substrate which forms the other pixel electrode, common to all the pixels and still called counter-electrode.
• the second substrate is arranged so that a cavity is formed between the top of the active matrix and the second substrate.
• the cavity is filled with liquid crystal with a composition and orientation of the molecules depending on the technology envisaged.
• the pixel electrode and the counter-electrode then form the two frames of the pixel capacitance, and the bistable material which makes it possible to memorize the information is between the two plates.
• FIG. 1 An active matrix structure for a bistable nematic display as described in the above-mentioned application is schematically illustrated in FIG.
• the structure M of the active matrix conventionally comprises rn * p couples (pixel electrode 1, transistor 2) arranged in an array of m rows ri, ⁇ 2 , ... r m , and p columns coh, C0I 2 , ... p .
• the transistor 2 associated with each pixel electrode 1 makes it possible to individually address a corresponding pixel of the screen by a line conductor and a column conductor.
• the transistor 2 associated with each electrode 1 acts as a switching element. When it is controlled in the on state, it allows the application of a determined voltage level on the pixel electrode, allowing the display of a corresponding gray level on the pixel of the screen. When it is controlled in a non-on or off state, it isolates the pixel electrode from the rest of the array (at near parasitic capacitance couplings).
• the transistor comprises two conduction electrodes, called drain d and source s, and a gate electrode g, by which the "on" or "off” state of the transistor is controlled.
• the transistor is generally connected in the matrix structure as follows: a conduction electrode, for example the drain d, is connected to the pixel electrode.
• the gate g of the transistor is controlled by the line selection signal applied to the associated line.
• the other conduction electrode of the transistor, in the example the source s, is connected to the associated column.
• the gates of all the transistors of the same line are all connected to this line, while the sources of all the transistors of the same column are all connected to this column.
• a transistor When a transistor is set "on”, it switches the voltage applied by the column associated with its source s, on the drain d: thus the pixel electrode 1 is charged to a voltage level corresponding to a video data (gray level ) to display.
• the pixel electrodes 1 are each controlled, via their associated transistor 2, by peripheral addressing circuits.
• These addressing circuits typically comprise a line control circuit 3, more simply called line driver in the following, and a column control circuit 4 more simply called column driver in the following.
• the line control circuit 3 applies voltage levels successively to the lines, in order to select them sequentially over a frame time.
• circuit 4 of Column control applies appropriate voltage levels to the columns, in order to display a given gray level on each pixel of the selected line.
• the control of the pixels of a bistable nematic screen assumes the use of high voltages if it is desired that the switching between the two stable states of the pixel is rapid.
• These two stable states correspond to two different textures, a uniform texture and a twisted texture. They result from a judicious composition of the liquid crystal associated with orientation layers of different molecules on each side of the substrates (or plates) forming the cavity filled with liquid crystal.
• the uniform texture is defined by a low angle of twist, close to 0 °, in the thickness of the pixel.
• the twisted texture is defined by a strong twist angle close to 180 ° in the thickness of the pixel.
• the shape of the electric field applied to the terminals of the pixel makes it possible to choose one or other of the two textures after a step of breaking the anchoring at a high electric field value, equivalent to a "reset" phase.
• texture This reset phase is characterized by a determined breaking voltage level, and a duration of application.
• one or the other texture is obtained according to the shape of the electric pulse applied.
• the switching in one or the other stable state can be obtained by the shape of the falling edge of the electric pulse.
• the uniform texture U can be obtained by slow-falling edge switching, for example by a step-like shape or by an analog downward voltage ramp from the breaking voltage level, which favors an elastic relaxation behavior. This elastic relaxation process causes the molecules to be all parallel without any twist angle, leading to the uniform texture U.
• the pixel appears black on the display.
• the twisted texture T can be obtained by a steep falling edge switching, from the breaking voltage level, which favors a dynamic process for modifying the orientation of the molecules, known by the Anglo-Saxon term "backflow".
• the strong hydrodynamic flow of the liquid crystal molecules of the pixel results in a weak breakage of the molecules and an organization of the molecules with a twist angle of around 180 °. The pixel appears white on the display.
• a display signal SD display (PI, P2) of a gray level on a bistable nematic display is illustrated in Figure 2.
• PI a gray level on a bistable nematic display
• P1 and P2 applied to the columns of the matrix during each line time.
• the first level P1 corresponds to the breaking phase of the anchor. It is characterized by a duration ⁇ 1 and a determined voltage level VP1. This voltage level is in practice chosen greater than or equal to a break voltage defined for the technology, as a function of the application time ⁇ 1.
• the second stage P2 corresponds to the phase of display (or writing) of the new texture. It is characterized by a duration ⁇ 2 and a voltage level VP2 lower than the voltage VP1 of anchor breaking.
• the shape of the signal Sc is a function of the data to be displayed.
• the sum ⁇ 1 plus ⁇ 2 gives the line time of the display, ie the time required to display the new display data on the pixels of a selected line of the matrix.
• the difference (or height) of operation between the first bearing P1 and the second bearing P2 is a function of the texture that is to be obtained.
• the slow falling edge necessary to obtain the uniform texture U is thus obtained by choosing a second bearing P2 lower, but not too distant from the first bearing.
• the steep descending front needed to obtain the twisted texture T is obtained by choosing a second step P2 further away, therefore lower than in the previous case.
• VP1 the voltage level of the first stage P1 and VP2, the variable voltage level of the second stage P2 of duration ⁇ 2, depending on the texture to be obtained.
• VP2 is equal to VU ⁇ VP1, to control a uniform texture U (black display);
• VP2 is equal to VT ⁇ VU ⁇ VP1, to control a twisted texture T (white display); and
• VP2 is equal to an intermediate value VM, between VT and Vu (VT ⁇ VMj ⁇ Vu ⁇ VP1) for controlling a mixed texture M (U 1 TX in which the two textures U and T coexist (display of a level of Grey).
• the voltage VP2 can thus take any value between the values Vu and VT, which are characteristics of the technology.
• Vu and VT are characteristics of the technology.
• VP2 VM- I
• there appears a portion of twisted texture T in the uniform texture U: there is a mixed texture M (U, T) - ⁇ , corresponding to a determined gray level.
• M (U, T) - ⁇ there is a mixed texture M (U, T) - ⁇ , corresponding to a determined gray level.
• the intermediate gray levels are obtained by varying the voltage level VP2 of the second level between the extreme values Vu and VT.
• Vu -VT ⁇ 3 volts the order of 3 volts between Vu and VT.
• the double arrow going from the left to the right in FIG. 2 illustrates the increasing direction of this effect as a function of the voltage of the second stage.
• the level of the anchoring breaking voltage VP1 is of the order of 15 to 18 volts for fairly long line times.
• the display control signal SD (PI, P2) which has just been described in relation to FIG. 2 is applied to the columns, whereas a line selection signal is applied successively to each row of the matrix. , during the line time.
• the display control signal has two distinct, successive signal components: a reset signal and a video signal.
• the reset signal corresponds to the initial phase, anchoring break.
• the video signal corresponds to a writing phase, or programming a new texture. These two signals have different voltage levels.
• the addressing of a row of the matrix for displaying new data is as follows: the line is selected by applying a selection signal in the form of a voltage pulse, during the line time. This pulse is in fact applied to the gate g of each of the transistors of the line ( Figure 1). This pulse has a voltage level sufficient to put each of the transistors 2 of the line in the "on" state.
• a display control signal is applied to each of the columns of the matrix, and thus to the source s of the transistors.
• the gate voltage applied to the transistors of the selected line must be at least equal to the voltage applied to the columns increased by the threshold voltage Vth of the transistors (ie the minimum voltage applied between gate and drain, or gate and source, for that the transistor is conductive), to obtain that each transistor of the selected line switches almost without loss the display signal Sc on the associated pixel electrode.
• Active matrices according to the state of the art have been developed more particularly for TN type liquid crystal displays, for “Twisted Nematics", or of the IPS type, for “In Play Switching", with line drivers and standard columns designed to support control voltage levels.
• These row or column drivers are preferably integrated into the active matrix. They can be made on an external circuit. They receive the analog power supplies necessary to ensure the display of the video data they receive.
• the line driver ensures the scanning of the lines, sequentially and the column driver ensures for each line, the application on the columns of the voltage levels to be applied to the pixel electrode to ensure the display of a corresponding data (gray level ) on each pixel of the line.
• the high voltage column drivers are designed to deliver 13 volts, making it possible to obtain about 6 volts rms on the liquid crystal (alternating positive and negative).
• the maximum voltage is 16.5 volts.
• Standard line drivers are capable of outputting voltage levels from -10 volts to 30 volts, for example.
• the range of voltages needed to control bistable nematic displays is compatible with the drivers of standard active matrices of the state of the art, TN or IPS.
• bistable nematic displays with active matrix for video applications in particular.
• the line time must be shorter, requiring to reduce the switching time of the pixels. This is to make the reset phase as short as possible.
• the shorter the anchoring break phase the higher the breaking tension required. This is explained in particular in the aforementioned publication (see ⁇ 3.4 and FIG. 5 in particular) and in a more recent publication by Ivan Dozov et al. Recent Symposium Digest 32, 224 (2001).
• the breaking voltage is then greater than 20 volts with the bistable nematic displays current.
• a problem which then arises in the use of a standard active matrix, in combination with bistable nematic displays is that there is no compatibility of the range of voltages necessary to control these displays with the standard technology of the devices. column drivers active matrices.
• the level of the breaking voltage is applied to the columns of the matrix, by the column driver 4 ( Figure 1). It has also been seen that the state-of-the-art line drivers are designed to apply amplitude gate voltage levels of up to 40 volts. On the other hand, the column drivers can not apply voltages of more than 16, 5 volts in the best case (standard IPS) on the drains (or sources) of the transistors of the matrix. It is therefore not possible to control voltages higher than 13 volts (TN drivers) or 16.5 volts (IPS drivers) on the columns of the matrix. These levels are insufficient to allow the anchor break on a sufficiently low line time, compatible with video applications.
• the TFT transistors associated with the pixel electrodes are capable of supporting and switching a voltage greater than 20 volts, it is not possible to apply such voltages using standard state-of-the-art drivers. .
• the voltages to be applied to the gates of the transistors, and the range [Vu, VT] of the voltage levels of the video signal to be applied be between 10 and 13 volts in practice, respectively corresponding to the twisted texture T and the uniform texture U , they do not fit in the standard specifications of the drivers of these matrices, it is not the same for the initialization component (bearing P1) of the display control signal SD (PI, P2) applied to the columns: it is indeed not possible to apply a breaking voltage of 20 volts and more by means of standard column drivers of the state of the art.
• An object of the invention is to solve this technical problem.
• An object of the invention is to provide an active matrix bistable nematic display structure that can be used with standard drivers (integrated or external) to apply high voltage levels to the pixel electrodes.
• An object of the invention is to propose such an active matrix at a lower cost.
• An object of the invention is to obtain an active matrix for a bistable nematic display device, essentially by modifying the drawings of the masks used for the manufacture of a standard active matrix for TN or IPS displays.
• An idea underlying the invention is to start from a standard active matrix, and to modify the structure so that standard drivers can be used, and to apply the necessary control voltage levels to the pixel electrodes. , without degrading neither the reliability of the matrix nor that of the drivers.
• the switching device associated with each pixel electrode comprises another switching element, for example another transistor, whose function is to ensure the breaking of the anchor point of the pixel.
• This other switching element can be controlled by the line driver, which supports high voltages of the order of 40 volts, and connected to a specific power bus, to switch a breaking voltage of the order of 20 volts or more.
• This breaking voltage is applied by the specific power bus and no longer by the column driver, which then exclusively serves to control the voltage levels corresponding to the video to be displayed, as for standard matrices TN or IPS.
• the specific supply bus can be made by conductors which are added in the matrix structure, on the levels of conductive layers, or by functional conductive layers already provided in the matrix, but whose function can be deflected. , for the purposes of applying the level of breakage voltage.
• These are typically the conductive functional layers provided in the active matrix structures as storage capacity. These layers can be diverted from their original function because the pixels of the bistable nematic displays do not require storage capacity to maintain the voltage level on the pixel electrode. Indeed, once the new texture is "written" in the pixel, it remains there indefinitely, as long as one does not break an anchor point.
• it is possible to divert functional layers provided in the TN or IPS active matrices of the state of the art to achieve a specific power bus, for the breaking voltage, and at lower development cost.
• the invention therefore relates to an active matrix for a liquid crystal display device, comprising pixel electrodes arranged in a crossed network of rows and columns, and associated with each pixel electrode, an electronic control device comprising a first switching element. connected between said pixel electrode and an associated column, a control electrode of said first switching element being connected to an associated line, characterized in that said control device comprises an initialization circuit of said pixel electrode comprising an initialization bus and a second switching element, connected between said pixel electrode and said initialization bus, and having a control electrode connected to a previous line of the network.
• the invention applies to liquid crystal displays comprising such an active matrix, and in particular to a bistable nematic display.
• FIG. 1 already described represents an active matrix structure for bistable nematic displays, according to the state of the art
• FIG. 2 already described illustrates the display control of a pixel of a bistable nematic display
• FIG. 3a illustrates a first embodiment of an active matrix according to the invention, with an initialization phase for each row of the matrix, corresponding to the breaking of the anchoring, performed on the addressing time of the previous line
• FIG. 3b illustrates forms of electrical signals on the various conductors of the matrix of FIG. 3a
• FIGS. 1 already described represents an active matrix structure for bistable nematic displays, according to the state of the art
• FIG. 2 already described illustrates the display control of a pixel of a bistable nematic display
• FIG. 3a illustrates a first embodiment of an active matrix according to the invention, with an initialization phase for each row of the matrix, corresponding to the breaking of the anchoring, performed on the addressing time of the previous line
• FIG. 3b illustrates forms of electrical signals on
• FIG. 3c and 3d each represent an alternative embodiment of an active matrix according to the invention
• FIG. 4a illustrates another embodiment of an active matrix according to the invention
• FIG. 4b represents corresponding electrical signals on the rows or columns of the matrix
• FIG. 5 illustrates an active matrix of the state of the art, comprising a storage capacity bus under each row of pixel electrodes, and which can be used in the invention
• FIG. 6a illustrates a first embodiment of an improvement of an active matrix according to the invention
• Figure 6b shows corresponding electrical signals on the rows and columns of the matrix
• Figures 6c and 6d each illustrate an alternative embodiment of the improvement
• FIG. 7 illustrates another embodiment of the improvement of an active matrix according to the invention
• FIG. 8 illustrates a variant of the control mode of a matrix structure according to FIG. 3a.
• FIG. 3a illustrates a first example of an active matrix structure with standard transistors according to the invention, able to allow the application of very high voltage levels on the pixel electrodes without risk of breakdown of the transistors used.
• Such a matrix structure used in a bistable nematic display then allows the use of the display in video applications, with line times less than 40 microseconds, which offers interesting prospects of opening the market of these displays.
• a pixel electrode EPg associated in the matrix at line r, and column CoI j comprises an associated control device.
• This device comprises, in the usual way, a switching element T connected between the column CoI j and the pixel electrode EP, j .
• the control electrode g of this switching element T is connected to the line ⁇ .
• the switching element is typically a transistor, of which a conduction electrode, the source s for example, is connected to the column, and whose other conduction electrode, the drain d for example, is connected to the pixel electrode .
• the control device of each pixel electrode further comprises an initialization circuit of the pixel electrode on the previous line time.
• this initialization circuit is a transistor-type switching element, T '.
• This initialization transistor T ' is connected between a conductor connected to a specific Reset power bus, and the pixel electrode.
• the source s' of the transistor T ' is connected to the pixel electrode EPg and the drain d 1 of the transistor T' is connected to the reset bus.
• the gate g 1 of this initialization transistor is connected to a previous line, ⁇ . 1 in the example.
• a corresponding pixel is formed between the pixel electrode EP g and a counter-electrode CE.
• the selection of a line results in the application by the line driver 3 of a voltage level Vg 0n applied to this line.
• the transistors, whose gate is connected to this line are then in the "on” state, equivalent to a short circuit.
• the deselection of this line results in a Vg Off voltage level applied on this line.
• the transistors of a deselected line are then in the off state "off", equivalent to an open circuit.
• the transistors T 'associated with the pixel electrodes EPi j of the line ⁇ , and whose gates are connected to the previous line r h1 , are set to "on" on the previous line time tl h1 , c is when the line ⁇ .i is selected. They are in the "off” state otherwise, in particular, they are in the "off” state on the line time.
• the transistors T are the ones in the "on” on the line time tl ,, and "off 1 on the other line time.
• the Reset bus is raised to a Vreset DC voltage level greater than or equal to the anchor breaking voltage of the liquid crystal molecules.
• the transistor T goes to the "on" state, it transfers the level of voltage Vreset on the pixel electrode EP, tJ on the line time N 1- - I 1 at Vg on -Vth which must be greater than the breaking voltage.
• line time is meant the addressing time of a line, during which the line driver applies a selection signal on this line, which has the effect of making all the switching elements T this line. All other lines are deselected during this line time.
• the line driver applies on the line time t1, of the line ⁇ , a voltage level Vg 0n which passes all the transistors T of this line.
• the line driver applies a voltage level Vg Off , so that all transistors are off or off.
• the transistor T then switches the voltage VD, applied to its source, by the associated column CoI j . is without losses because VD is at most equal to the voltage level for a uniform texture, or 13 volts in the state of the art, while the gate voltage Vg 0n is much higher, of the order of 20 volts and more.
• the pixel electrode EP g connected to a transistor T of the selected line r therefore charges substantially at the voltage level VD, which is applied to the corresponding column CoI j on the line time t1.
• This voltage level typically corresponds to the data to be displayed.
• the Vreset initialization voltage was of the order of 20 volts or greater than 20 volts, for line times compatible with video applications.
• this voltage is applied by a specific bus, directly on the drain of the transistor T of the matrix, while the gate g 1 controlled by the line driver receives a higher voltage Vg 0n at the voltage Vreset of at least the threshold voltage Vth of the transistor T '.
• the threshold voltage Vg 0n remains below 30 volts: it is therefore compatible with the gate control voltage range of the standard line drivers.
• the video voltage levels applied by the column driver to the sources or drains of the transistors T vary between 13 volts, to control a uniform texture U, and 10 volts, to control a twisted texture T. These voltage levels are included in FIG. the range of control voltages provided by standard column drivers.
• An active matrix as illustrated in FIG. 3a used with standard row and column drivers, integrated into the matrix or not, in a bistable nematic display, is thus able to allow the anchoring break and the display of the new video data for each of the pixels of a line r ,, on two separate line times: the anchoring break on the previous line time, tl, .i and the display of the new video data on the line time tl ,.
• the control device of each pixel electrode comprising a transistor T and an initialisation circuit T "according to the invention thus makes it possible to simply obtain a two-stage signal form on the pixel electrode, as illustrated in FIG. the pixel electrodes EP U and EP, + i j .
• This signal is compatible with the control of the pixels of a bistable nematic display. This is achieved by using a standard active matrix, with standard row and column drivers, for TN or IPS displays, by simply adding a transistor to the array. This is achieved simply by modifying the designs of the masks, without having to modify the steps of the standard manufacturing process. For a bistable nematic display, the addition of a transistor per pixel is not detrimental in terms of OAR, because ultra-portable devices that use such displays usually operate in reflective mode.
• transistors T and T ' are each used in usual ranges of voltage.
• the separation of anchoring break functions, and video display by different switching means, activated on different line times allows to apply voltage levels compatible with the technology, and with video applications.
• the specific supply reset bus which brings the initialization voltage Vreset, to the drains or sources of the matrix initialization transistors, comprises a plurality of conductors arranged parallel to the columns. . In practice these conductors are made on the same level as the columns of the matrix, or on a separate level.
• the conductors of the Reset supply bus are arranged parallel to the lines of the matrix. This is the variant shown in Figure 3c. It should be noted in this respect that there exist in the state of the art matrices which comprise for each pixel, a column, an address line and a storage capacity line. It is then easy to use these matrices of the state of the art by modifying the function of these storage lines, into a function of supplying a Vreset initialization voltage to the drains (or sources) of the transistors initialization T ', providing suitable connections between these lines and these drains (or sources).
• the Reset supply bus is formed by a conductive functional layer F of a standard matrix, such as the buried ground plane 'Ground plane') usually used to form a storage capacity with each pixel electrode, in standard TN matrices in particular.
• a functional layer is formed on a separate level of the pixel electrodes by at least one insulator layer, to form a parallel storage capacitance on the Cpixel pixel capacitance.
• This functional layer may also be a layer of the "Light Shield” type, ie a screen which is commonly used in standard TN matrices in particular, to mask the light leaks due to the structure-induced field lines. .
• It is generally a conductive and opaque layer, made of titanium in the form of a grid, and which can be either disposed under the active matrix (that is to say under the transistors) or between the level of the lines / columns (forming the drains / sources of the transistors) and the pixel electrodes.
• This conductive layer is usually formed on a separate level of the pixel electrodes by at least one insulator layer and thus serves in these storage capacity structures for each pixel electrode. For the same reasons as above, this layer can therefore be advantageously used as a supply bus for supplying the initialization voltage Vreset to the drain (or the source) of each initialization transistor T '.
• FIG. 4a Another embodiment of an initialization circuit according to the invention is shown in FIG. 4a.
• the initialization circuit of the control device of a pixel electrode of a line r then comprises a diode D connected between the pixel electrode EP, j and the preceding line r, _i.
• the diode D can be obtained typically by a transistor whose drain of (or source) and the gate g 1 are connected together, to the previous line r h1 .
• the other conduction electrode of the transistor, the source s' in the example, is connected to the pixel electrode EP ,, j .
• FIG. 4b shows the shape of the signal that can be obtained on the pixel electrode EP 1J , according to the signals applied to the rows and columns of the matrix during the different line times U 1 - I, t 1, t 1, + 1 , ... It is substantially identical to that illustrated in Figure 3b.
• FIG. 5 illustrates an example of an active matrix described in the French patent application entitled "Active matrix structure for a display screen and screen comprising such a matrix” and recorded under the number 02 15484.
• a matrix describes parallel buses. to the lines, and arranged under each row of pixel electrodes, and used as storage capacity.
• Such a matrix can still be used to produce a matrix according to the invention.
• Such a matrix is illustrated in FIG. 5. It includes storage capacity buses provided under each pixel electrode row.
• Each pixel electrode EP 1 covers a large part of the surface framed by two lines and two successive columns. In the figure, the row R of pixel electrodes is flanked by the associated selection line, r h, and by the selection line r i of the immediately preceding row.
• a bus of associated storage capacity B is provided below the row, of substantially the same width.
• This bus B 1 is arranged in parallel, between the two selection lines r, and ⁇ .-i. It is connected to the selection line r, .i of the previous row. In the example shown, it is connected to this line, outside the active zone of the matrix, ZA, by its two ends.
• This bus B forms a storage capacitor Cst with each pixel electrode EPi J of the row R 1.
• this storage capacitance formed by the bus B 1 which is large, and which is connected to the preceding selection line r, i, is advantageously used to charge the pixel electrodes EPg of the line ⁇ , to the desired initialization voltage, typically at the Vreset initialization voltage. This is obtained by sizing the storage capacity (facing surface between the storage capacitor plane and the pixel electrode, the dielectric used and the dielectric thickness) so that the coupling offset is greater than the initialization voltage. sought.
• the switching element T 'connected to the pixel electrode EP U of FIG. 3a is here replaced in an equivalent manner by the bus B 1 .
• this bus forms a storage capacitor with this electrode EP 1J , a terminal of this capacitance being connected to the pixel electrode, the other terminal of the capacitor being formed by the conductive bus itself and connected to the preceding line ⁇ .i.
• Switching the voltage Vg O ff to the voltage Vg 0n on the line rg causes the switching on the other terminal of the storage capacitor of a voltage equal to the coupling offset, of the order of the Vreset tension.
• the previous line r, .i is at a level Vg 0n chosen greater than the initialization voltage Vreset.
• the initialization circuit associated with each pixel electrode thus comprises the bus forming storage capacity with said electrode.
• the matrix comprises for each line ⁇ , a conductive bus B 1 buried under the row of pixel electrodes of said line, and connected to the previous line r, .i .
• This bus forms a storage capacity with each of the pixel electrodes of said line of rank i.
• This storage capacity is sized to exceed a coupling offset higher than the Vreset initialization voltage.
• the initialization circuit associated with each pixel electrode then comprises the bus forming storage capacity with said electrode.
• each pixel electrode a form of two-level electrical signal: an initialization stage, allowing the break, a write stage of the new video data.
• the pixel electrode remains at the second level until the next line time of the new video frame.
• An improvement of the invention comprises a circuit for grounding the pixel electrodes of each line at the end of the line.
• FIG. 6a A first embodiment of a matrix according to the invention comprising such a grounding circuit is shown in FIG. 6a.
• the grounding circuit is another switching element, typically a transistor T ", connected between the pixel electrode EP U and a ground plane GP ground of the matrix, and activated on the time line following tl + i. to this end, the gate g "of the last transistor to ground T" is connected to the next line r, + i.
• the voltage level of the pixel electrode EPi j is drawn on the line time t1, + i, from the video level VD, charged on the line time t1, towards the electrical ground (0 volts ).
• the line time tl corresponds to a display cycle ⁇ v of the new video on these pixel electrodes.
• the line time tl, + i corresponds to a grounding cycle ⁇ m of these pixel electrodes. From line to line, the three cycles ⁇ c , ⁇ v, ⁇ m succeed each other over three successive line times: the line time of the preceding line, the line time of the current line, the line time of the following line.
• time lines are in the example immediately successive, choice that facilitates the design, but it is quite possible that these times lines are separated by several times lines.
• FIG. 6a there is a control device with three transistors: the transistor T for charging the video, the initialization transistor T 'and the grounding transistor T.
• the switching transistor to earth is connected to a ground plane GP
• the initialization transistor T ' is connected to a bus or a different conductive plane, which is brought to the voltage Vreset.
• Vreset is thus brought by a supply reset bus, comprising conductors parallel to the columns (which corresponds to the embodiment of FIG. 3a).
• the Vreset voltage is brought by a screen-type conductive plane ( "Light Shield") LS (which corresponds to the embodiment explained in relation to FIG. 3d).
• the grounding transistor T is connected to a conductive functional layer F of the matrix, which is grounded. by the parasitic capacitance line / pixel C p ⁇ xe ⁇ / ⁇ r, illustrated in Figure 4a. in order to ensure the discharge of the pixel electrode, the value of the capacitance is adapted to ensure at least the passage under the torsional threshold voltage from the pixel to the deselection of the line.
• the grounding can be obtained by the natural clearance of the leakage currents of the first switching element (T) and / or the second switching element of the control device of each pixel electrode, when these transistors are polycrystalline, monocrystalline, polymorphic or organic.
• FIG. 7 illustrates another embodiment of a circuit for grounding in a matrix according to the invention, according to which a current of leakage of the spacers e is used which is usually used in the cavity comprising the liquid crystals of a display .
• one or more spacers are arranged on each electrode. These spacers are in contact with the pixel electrode and the counter electrode CE. Then there is a leakage current in each spacer that will draw the pixel electrode to the potential of the counter-electrode (typically the mass).
• These spacers are in a chosen material with a conductivity determined sufficiently high not to disturb the charge of the pixel but low enough to obtain the discharge after a few times line.
• FIG. 8 illustrates yet another embodiment of the circuit for grounding in a matrix according to the invention, with a matrix according to any of the embodiments illustrated in FIGS. 3a, 3b, 3c, 3d, 4a, or 5 , or a variant that follows, in combination with an appropriate command of the power supplies on the column driver 4 at the end of each line time, that is to say just before the end of the line time, because it is necessary here that the line is still selected.
• the grounding of the pixel electrodes of a line is thus obtained by controlling on the columns, a return to zero at the end of each line time.
• a return to zero at the end of each line time For example on the line time tl h on each column, for example on the col column, first the video voltage level to be displayed VD 1 , then the level 0. This is good.
• This is obtained by providing at the level of the control circuit of the columns (column driver), or via an independent circuit controlled appropriately, a grounding of the analog voltages just before the end of each line time. (the line must still be selected).
• the transistors of the matrix T and T '(or D), or T, T' and T "according to the variant embodiments, may be TFT transistors, whose channel is made of silicon amorphous, and which have the advantage of not being the seat of leakage currents. This is an important parameter for TN or IPS displays.
• a bistable nematic display comprising an active matrix according to the invention with row or column drivers, integrated or not, standard, can thus be controlled with line times less than 40 microseconds, which makes it usable for many applications, with all the advantages offered by bistable nematic technology at a lower cost.
• the pixel electrode and the counterelectrode form the two frames of the pixel capacitance, and the bistable material which stores the information is between the two frames.
• the invention that has just been described applies by equivalence to matrix memory devices, to at least two stable states, such as memories of ROM, RAM, CCD .... type, in which the bistable material is included. between the two frames of information storage capacity.
• the pixel electrode is to be understood as an armature of this capacitance.

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  • 2005-08-02 FR FR0508259A patent/FR2889615B1/fr not_active Expired - Fee Related
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