Classifications

• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
  • H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
  • H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
  • H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
  • H02J9/061—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems for DC powered loads
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B60—VEHICLES IN GENERAL
  • B60R—VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
  • B60R21/00—Arrangements or fittings on vehicles for protecting or preventing injuries to occupants or pedestrians in case of accidents or other traffic risks
  • B60R21/01—Electrical circuits for triggering passive safety arrangements, e.g. airbags, safety belt tighteners, in case of vehicle accidents or impending vehicle accidents
  • B60R21/017—Electrical circuits for triggering passive safety arrangements, e.g. airbags, safety belt tighteners, in case of vehicle accidents or impending vehicle accidents including arrangements for providing electric power to safety arrangements or their actuating means, e.g. to pyrotechnic fuses or electro-mechanic valves
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
  • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
  • H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
  • H02J7/345—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering using capacitors as storage or buffering devices

Definitions

• the invention relates to a control device for personal protection according to the preamble of the independent claim.
• the erf ⁇ ndungssiee control unit for personal protection with the features of the independent claim has the advantage that the control unit at least one measured value observed at a turn-off and depending on a signal generated, based on this signal an assessment is made by the control unit, as it is to behave in a carcass fall. This error can be detected early and overall safe operation of the controller in one Autarkiefall be guaranteed.
• a signal for example, control signals or counters or accumulations or comparison results or the measured value itself come into question.
• the control unit ensures the monitoring of the integrity of the supply system including the connected external sensors that the system of the control unit, the connected sensors and the personal protection means remain fully functional for a desired time without disturbances such as a system reset in a real autarky event becomes.
• a feature is a polarity reversal protection between the external battery voltage UB and an internal voltage VZP, which is normally generated by the battery voltage UB, but can also be provided in the autarkiefalle from the energy reserve, for example by a DC / DC down converter.
• this control unit protects against the outflow of energy into the electrical system, in particular if it has a short circuit to ground.
• the check for integrity of the system supply in Autarkiefall is therefore preferably at each switching off the controller by a first measurement of the battery voltage UB and the internal
• Voltage VZP is initiated when the battery voltage UB falls below a minimum threshold U-Boff (e.g., 5V). Prerequisite for carrying out the measurement is a charged energy reserve of an operational system. This measurement confirms the blocking capability of the polarity reversal protection diode, since the internal voltage VZP must be higher than the battery voltage UB.
• U-Boff e.g. 5V
• a second feature is a bidirectional DC / DC switching converter which, independently of a microcontroller .mu.C, supplies energy from the energy reserve to the supply voltage VZP in the case of an excessively low internal voltage VZP when the threshold VZP falls below rn.
• This independence makes it possible to differentiate between a dynamically occurring reset in the system and an autarchic state, eg caused by normal switch-off.
• depending on the mode of operation of the switching converter is also called down converter when the switching converter from the energy reserve voltage to the internal voltage converts, the switching converter in normal operation the Battery voltage or internal voltage for charging the energy reserve upwards.
• a system If a system has reached its operational readiness and signals this by deleting the warning information, for example by switching off the warning lamp, this is characterized by a charged energy reserve.
• This analogue variable is supplied to the microcontroller ⁇ C for monitoring via a voltage divider. This converts this size first with an analog-to-digital converter in a digital size.
• the monitoring of the energy reserve voltage begins after a period of time, which is either known as a fixed parameter of the software of the microcontroller ⁇ C, or additionally determined as a function of the battery voltage.
• a first measurement of the energy reserve voltage at the start of the system immediately after a RESET enable and initialization of the microcontroller ⁇ C is performed.
• the microcontroller ⁇ C recognizes, on the basis of a first measurement of the energy reserve voltage VER, that it already has a value much lower than VERoff and thus the reasons for the restart ("warm start") was not an autarkic fall or a regular shutdown, but an inadmissible RESET, eg caused by a fault.
• Another feature that decides on self-sufficiency is the knowledge that in case of one case the fully usable energy is available. This is not only a question of capacity and power consumption, but also a global property of the system, which expresses that the energy reserve voltage VER can be used from a value VERreg max to a value VERoff.
• an autarchy test marker is placed in a memory, for example - A -
• control unit components which belong to this feature are the already known energy reserve voltage-VER and battery voltage-UB detection as well as additionally the internal voltage VZP by the microcontroller ⁇ C via a voltage divider.
• the repetition rate of the measurement is system dependent between 1 - 10ms usually lms.
• a capacitor CyZP can be used for this purpose. If the autarkic fall marks out
• the DC / DC switching converter will be activated independently of the microcontroller and a drop below VZP ⁇ VZPth
• Voltage VZP VZPreg e.g. 6.3V to CtyzP generates the, which takes over further system supply from the energy reserve ER. With increasing discharge of the energy reserve, the maintenance of the control voltage VZPreg approaches the end.
• VZP VZPreg_min (e.g., 6.0V)
• VZPregoff 5.8V detected.
• the voltage VER VERoff measured at time VZPregoff, which is also measured in this measuring grid, is now written to the EEPROM as the last, still safely storable measured value.
• the writing process for EEPROMs takes about 1-lOms.
• a VERoff FZ fault counter for defective VZP autarky control
• the counter reading reaches the value n,
• the system warning lamp is preferably permanently activated.
• the VERoff FZ Fault Counter may be incremented by 1 for each detected error and decremented by 1 for each undetected error.
• the incrementing and decrementing steps could also be chosen differently.
• the specified autarchy time is additionally checked in the case of the integrity check of the system (control unit with connected components) described here in the case of autarchy, for example.
• an autarky test marker is written to the EEPROM ("AUTARKIE TESTABLE") to verify the validity of autarky tests prepare.
• AUTARKIE TESTABLE an autarky test marker is written to the EEPROM ("AUTARKIE TESTABLE") to verify the validity of autarky tests prepare.
• the elapsed autarky time AUTARKY time counter is stored in an EEPROM.
• test markers are also read out of the EEPROM and evaluated immediately after the RESET release and initialization of the autarchy. If it is set to "AUTARKIE TESTABLE", the stored autarchy time is evaluated .. If AUTARKYtime ⁇ AUTARKYtime min, an AUTARKYtime_ error counter in a non-volatile memory (EEPROM) is incremented by 1. If the counter reading reaches the value n, for example 3, the system warning lamp is activated Accordingly, the signal in the sense of claim 1 is here the activation of the system warning lamp.
• the AUTARKIEZEIT_error counter may be incremented by 1 for each detected error and decremented by 1 for each undetected error. Furthermore, the incrementing and decrementing steps could also be selected the same or different.
• the error counter is the signal in the sense of claim 1.
• a communication error occurs, it is stored in a non-volatile memory (EEPROM).
• EEPROM non-volatile memory
• a communication error counter (COMM FZ)
• test markers are also read out of the EEPROM and evaluated immediately after the RESET enable and initialization of the autarky. If it stands up, AUTARKIE PRÜFBAR "then the stored KOMM FZ is evaluated.
• the system warning lamp is permanently activated; if not, it can also be decremented.
• each connected external sensor has its own
• Communication error counters are introduced. To distinguish whether communication errors occur in the normal state of the system or in autarky, different communication error counter can be stored. This makes it possible in particular for errors or the function of sensors connected to the control unit, that is to say so-called satellites or assistants, to be detected. Because even these sensors are to be supplied with energy in the absence of battery voltage from the energy reserve, without becoming unusable in this critical phase by communication errors.
• the erf ⁇ ndungsdorfe control unit is thus safer, since it is still fully functional in the case of demolition or break-in of the battery voltage for a certain time. Furthermore, this makes the controller smarter, as it is able to differentiate various errors, such as battery break-in or reset.
• the real case without battery supply is simulated during the monitoring of the energy reserve.
• the controller recognizes a fault of the controller if and only if the internal voltage is too low and the battery voltage is normal.
• an error signal is generated by the control unit, as a function of which, for example, an optical or acoustic warning is issued that the control unit has a defect.
• control unit in addition to the measurement of capacitance and / or ESR of the energy reserve, the control unit also assesses this based on emitted energy to an internal voltage (VZP).
• VZP internal voltage
• control unit after the autarky time has elapsed, monitors further parameters, up to the limit of the storability of the results, in order to determine whether the control unit continues to show any autarchy weaknesses that have to be detected in order to remedy the situation. by changing defective components.
• control unit on reaching a predetermined state, for example, a steady state after switching on a
• MARKER sets in a non-volatile memory and thus sets the standard requirements for the observed parameters of a regular Autarkiefall or usually a normal shutdown.
• control unit writes data in memory as a function of the energy reserve. This provides data on the voltage, the capacitance and the internal resistance of the energy reserve as well as the energy reserve voltage after the end of the specified autarky time and the smallest usable energy reserve voltage for a subsequent analysis. This facilitates the proof of the functionality of the control unit.
• FIG. 1 is a block diagram of the control unit
• Figure 2 is a flow chart airbag ready
• Figure 3 is a flow chart airbag in the initialization
• FIG. 4a is a block diagram of the switching converter
• FIG. 4b is a circuit diagram of an autarkic detection circuit.
• Previous safety-relevant systems in particular control devices for personal protection, monitor the capacity of an energy reserve, in particular an electrolytic capacitor, this capacitor being used for the provision of energy for supplying the control device in the event of autarky and / or for the ignition of restraint means.
• Real is the state in which the supply of the controller and the satellites powered by these not only the battery voltage source via polarity reversal diode, but from the personal protection system itself, by the self-sufficiency.
• Crash case can match, also ensures the availability of the personal protection system.
• the control device has a number of advantages: The monitoring of the reverse polarity protected voltage required in the control unit must activate a switching converter in good time at a defined, lowest possible limit, which converts the voltage of the energy reserve down to a required value. It must be avoided that the control unit, despite full power reserve and a successful Abundwandlertest, ie the implementation of the voltage of the energy reserve capacitor to the voltage that is required in the control unit, comes to a halt by reset in the digital supply or by communication abatement of the satellites.
• VZP is carried out. Furthermore, it is ensured that the switching converter has been activated in good time and that the current required by the control unit can be provided.
• the advantage here is that in this approach, the regulation of the voltage VZP by the down converter VER-> VZP, by the microcontroller ⁇ C on the independent detection of the internal voltage VZP and additionally by the band monitoring of the output voltages, which are derived from VZP such the 5V analog / digital voltage is possible.
• the system can demonstrably ensure the evaluation of the satellite sensors even in the event of a crash with supply interruption.
• the voltage of the energy reserve after the end of the guaranteed autarchic time without ignition of restraints, it is ensured that the efficiency of the power supply and the power consumption is within the permissible tolerances.
• This also an unacceptably high current at the controller or the satellite, as it may be present in case of defects, is detected.
• the control unit according to the invention makes it possible to detect any type of reset operations, the cause of which is not a break in or an interruption of the supply voltage, as may occur due to electrical interference, electromagnetic radiation, humidity, etc. This is therefore possible because a so-called warm reset without degradation of the energy storage of self-sufficient device.
• VERoff max Max. Value of the energy reserve voltage which leads to the breakdown of the control voltage VZR reg when falling below
• VZPreg min Minimum control voltage of VZP in autarkic fall
• VZPreg max Maximum control voltage of VZP in autarkic fall
• VZPreg off Minimum voltage on VZP after leaving the control band which still allows a safe error handling.
• COMM FZ communication error counter to external sensors etc.
• MW measured value
• FIG. 1 shows a first block diagram of the control device according to the invention.
• the control unit 10 has in its housing a microprocessor or microcontroller ⁇ C, which is connected via a data interface, such as an SPI line SPIl, with an interface module PAS IF.
• the interface module PAS IF serves as a connection for external sensors 11.
• external sensors 11 are for example outsourced acceleration sensors, for example in the area of the front hood, or else
• Side impact sensors which may be acceleration sensors and / or pressure sensors, and also weight sensors and occupant position detection sensors.
• the microprocessor ⁇ C Via a second data interface, for example an SPI line SPI2, the microprocessor ⁇ C is connected to an ignition output stage FLIC.
• the ignition output stage FLIC is used to ignite ignition circuit for RHS.
• the retaining means RHS are located outside the control unit 10. These are airbags, belt tensioners and / or roll bars.
• the switching converter 12 consists of an independent comparator 12a, which compares the internal voltage VZP to the threshold VZPth (eg 5.2V) and in case of stepping down the switching converter 12b VZP ⁇ -> VER in the Ab lakeitmode switches (self-sufficiency).
• the supply of the control unit 10 is made from VZP. This can be used directly as with the PAS IF or via other voltage transformers 14, which generate the digital and analogue supply 5V, 3.3V, 1.8V of all modules.
• the microprocessor ⁇ C monitored via a level adjustment circuit 16 (in the simplest case independent voltage divider in special cases, voltage divider with level limiting and Störfilterung) the voltages UB, VZP and VER via a multi-channel analog-to-digital converter for the task discussed here.
• a level adjustment circuit 16 in the simplest case independent voltage divider in special cases, voltage divider with level limiting and Störfilterung
• the battery voltage UB is normally used to supply the controller 10.
• the energy reserve CgR is also normally used to provide the ignition current for the FLIC.
• the anode of a polarity reversal protection diode 17 is connected to CgR and this in turn to the switching converter output 12.
• the cathode of the diode 17 is connected to the FLIC.
• the microprocessor ⁇ C can detect the presence of the polarity reversal protection diode in the flow direction in normal operation.
• the microprocessor ⁇ C has now recognized that a autarkiefall from UB supply view is present and the system only remains functional, even if the hardware given by the comparator 12a detects this, the switching converter VZP ⁇ - -> VER switches in time in the Aboniaingmode and energy of Energy reserve CJTR can be taken to form a sufficiently high control voltage at VZP.
• the evaluation takes place only if previously the system could reach its normal operating state, characterized from an energy point of view in that the energy reserve voltage VER in a well-defined monitoring band e.g. 21 -28V or 31-38V etc. was. This circumstance is indicated by an autarchy test marker.
• the microprocessor ⁇ C starts an autarchy counter based on the condition UB ⁇ UBoff. This condition must be valid throughout the test.
• the measurement of the voltage UB takes place with a repetition rate of, for example, 1-10 ms.
• the energy reserve voltage VER ignition is measured. This reading must be above a limit of ignition min (e.g., 15V) which is chosen so that ignition of the restraint is possible under the required current conditions.
• the Ignition value is written to a non-volatile memory 15 (EEPROM), which is connected to the ⁇ C via a data interface, such as a serial SPI line (SPI2), for later evaluation in the initialization phase.
• EEPROM non-volatile memory 15
• SPI2 serial SPI line
• the system warning lamp is permanently activated, or error information is output as the signal to a standardized vehicle bus such as CAN via a transceiver 19.
• the Ignition_ FZ can be incremented by 1 for each detected error and decremented by 1 for each undetected error. Furthermore, the incrementing and decrementing steps could also be chosen to be the same or different.
• the system is ready to perform the test described above for the next autarchy to be observed.
• the condition UB ⁇ UBoff if not complied with throughout the autarky time measurement, may be used to abort the measurement, since the requirement for autarky was not consistent.
• a communication error occurs, it is written to a nonvolatile memory 15 (EEPROM).
• EEPROM a nonvolatile memory 15
• a communication error counter may be formed in the nonvolatile memory 15, which is incremented by 1 each time a communication error occurs.
• a separate communication error counter can be introduced for each connected external sensor.
• different communication error counter can be stored (stored). This makes it possible in particular for errors or the function of sensors connected to the control unit, that is to say so-called satellites or assistants, to be detected. Because even these sensors are to be supplied with energy in the absence of battery voltage from the energy reserve, without becoming unusable in this critical phase by communication errors.
• test markers are then read out of the EEPROM and evaluated by the microprocessor .mu.C immediately after the RESET release and initialization of the autarchy time.
• AUTARKIE PRÜFBAR "then the stored communication error (in self-sufficiency) is evaluated. If KOMM FZ> eg 3 the system warning light is permanently driven, or an error information to a standardized vehicle bus such as CAN via a Tranceiver 19 delivered.
• the communication error counter can be decremented again after a judgment without warning.
• VZP VZPreg eg. 6.3V to CA / ZP generated, which takes over the further system supply from ER.
• VZPreg VZPreg eg. 6.3V to CA / ZP generated
• VZP VZPreg_off eg. 5.8V detected by the microprocessor ⁇ C.
• the voltage VER VERoff also measured in this measuring grid at the time VZPreg off, is now written to the non-volatile memory 15 (EEPROM) as the last safe storable measured value.
• the writing process for EEPROMs takes about 1-lOms.
• test markers are then read out of the nonvolatile memory 15 (EEPROM) and evaluated by the microprocessor .mu.C immediately after the RESET release and initialization of the autarchy. If it rises, AUTARKIE CAN NOT BE TESTED ", then the memory cell VERoff is not checked and no error handling is performed.
• EEPROM nonvolatile memory 15
• the microprocessor ⁇ C continues its further program sequence for achieving operational readiness. If it is "AUTARKY TESTABLE", the content of the memory cell VERoff is read out of 15 and compared with the lower usable energy reserve voltage VERoff soll, which is known as a parameter to the system, and assumed as the prerequisite for the energy reserve calculation.
• the VERoff FZ can be incremented by 1 for each detected error and decremented by 1 for each undetected error. Furthermore, the incrementing and decrementing steps could also be chosen differently.
• this feature is a complex feature that goes far beyond simple knowledge of individual quantities such as energy reserve capacity. For example, this test can be successfully passed if
• the detection of reset disturbances is considered in the transition to the autarky state or other processes that could cause dynamic disturbances in the RESET structure of a system (humidity, EMC, etc.).
• Figure 2 illustrates in a flowchart the basic sequence in a control unit, starting from the ready state.
• method step 201 the current variables UB, VZP, VER are measured.
• the battery voltage is set to a certain
• the warning lamp is activated in method step 2002 (the indication mZ, with time control indicates that a permanent or different type of lamp control takes place according to the wishes) and the method continues in B (205).
• step 203 If the supply voltage in the regular supply band (202 is true), the process continues in step 203. If VZP ⁇ UB is true, the battery reverse polarity protection diode 13 is given in the forward direction in Figure 1, and it follows step 204, in which the error counter (Battdiode FZ) is decremented for freedom from error, if it is greater than 1.
• step 2003 follows.
• the associated error counter Battdiode FZ is incremented. It follows process step 2013. Is the Battdiode FZ> 10 d. h., there is a filtered safe error of the polarity reversal protection diode 13 in Figure 1, so follows process step 2014 with warning lamp on and continuation of the procedure in B (205).
• step 206 the energy reserve voltage is checked for compliance with a specific band. If there are inadmissible energy reserve voltages, the reasons are given in 2006 and the procedure will be continued in 2007. If 206 is true, it is confirmed that the controller is ready for operation. It follows method step 207, in which the contents of the memory cell autarky test - markers, for example. Cell 2 (15 in Figure 1) is checked. If the content is NOT AUTHENTICALLY TRUE, the process continues in step 208.
• the specified cells are preempted with default cell contents, which is thus ready for testing for an upcoming autarkic case for integrity, typically a normal shutdown of the system by turning the key switch in position o.
• Step 209 is followed by the entry point 209. If 207 is not true, the method continues in C (209), since the memory cells have already been pre-assigned.
• process step 210 contains the further process steps in the lms Humne, but which have nothing to do with the invention dealt with here.
• the process is re-run in A (200) exactly in the lms (e.g., lms-10ms) cycle.
• process step 2007 The continuation of the process in process step 2007, after the power reserve voltage is not in the target range, tests the controller supply voltage. If process step 2007 is true, i. UB is too small or not available, follows process step 2017, here it is checked whether the amount of energy reserve voltage for ignition via diode 17 and the ignition circuit FLIC (FLICS) in Figure 1 is insufficient or not. If method step 2017 is true, method step 2117 follows.
• the current state of the volatile ⁇ C RAM self-suffix counter is stored in the nonvolatile EEPROM memory (15 in FIG. 1), for example. written in cell 4, if not already done.
• method step 2118 contains the further method steps in the lms plane, but which have nothing to do with the invention dealt with here.
• the process is re-run from A (200) exactly in the lms (e.g., lms - 10ms) cycle.
• step 2119 follows, in which it is checked whether VZP is less than a lower limit which characterizes the breakdown of the VZP control. If this step is true, step 2120 follows, in which the current VER measured value, which now corresponds to the limit VERoff, is converted to a nonvolatile state EEPROM memory (15, Figure 1) by the microprocessor ⁇ C eg. is written in cell 5, if not already done.
• step 2121 which contains the further process steps in the lms level, but have nothing to do with the invention treated here.
• the process is re-run from A (200) exactly in the lms (e.g., lms - 10ms) cycle.
• step 2119 is false, i. H. If the VZP voltage is too high during autarky, this may also be supplied to error handling in step 2219.
• step 2018 follows.
• step 2028 the currently present measured value of the energy reserve voltage is called ignition in the EEPROM by the microprocessor ⁇ C in cell, for example. Cell 3 written. This energy reserve voltage is held after evaluation of the required autarky time without evaluation.
• step 2128 which contains the further process steps in the lms level, but have nothing to do with the invention treated here.
• the process is re-run from A (200) exactly in the lms (e.g., lms - 10ms) cycle.
• process step 2019 follows.
• the ⁇ C RAM counter is, for example. in RAM cell 1 for autarky time incremented by 1 ms. This is followed by process step 2020.
• a communication error counter in a non-volatile memory (15, FIG. 1), for example. incremented in cell 6.
• step 2121 which contains the further process steps in the lms level, but have nothing to do with the invention treated here.
• the process is re-run from A (200) exactly in the lms (e.g., lms - 10ms) cycle.
• step 2020 If, in step 2020, the condition is not met, i. H. There are no communication errors, followed by step 2021, which contains the further process steps in the lms level, but have nothing to do with the invention dealt with here.
• step 2021 After processing, the process is re-run from A (200) exactly in the lms (e.g., lms - 10ms) cycle.
• process step 2007 If process step 2007 is not fulfilled, the shutdown can not be detected with UB, and it follows in 2008. Further program parts for monitoring the energy reserve voltage and, if necessary, their error handling are carried out here. This is followed by process step 2009, which contains the further process steps in the lms level, but which have nothing to do with the invention dealt with here. After processing, the process is re-run from A (200) exactly in the lms (e.g., lms - 10ms) cycle.
• FIG. 3 explains in a flow chart the basic sequence in a control unit starting from the initialization state.
• the autarky test marker becomes the EEPROM
• step 301 Cell eg 2 read by the microprocessor ⁇ C. If the content "AUTARKIE PRÜFBAR" is present, then method step 301 is carried out If this content is not present, further tasks are carried out in method step 3000 in the initialization phase, which have nothing to do with the invention dealt with here.
• method step 301 it is checked whether the current VER voltage is smaller than the value VERoff max known to the system for the "GOOD case" parameter as a parameter, thereby ascertaining whether a regular autarky has preceded There was no erroneous dynamic WARM reset, followed by step 302.
• an error counter that counts WARMreset errors is decremented if it is greater than one.
• method step 3001 follows.
• the occurred WARMreset error is counted in a nonvolatile memory, e.g. in cell 10.
• step 303 the nonvolatile memory becomes the contents of the cells
• step 304 an evaluation of ignition follows. Ignition is less than a parameter known to the system Ignition min, d. H. if faulty, then method step 305 follows.
• step 306 the check of this error counter follows an allowable limit, e.g. 3. If this is exceeded, then follows in step 3006, the control of the warning lamp because of too low VER voltage after required Autarkiezeit.
• an allowable limit e.g. 3. If this is exceeded, then follows in step 3006, the control of the warning lamp because of too low VER voltage after required Autarkiezeit.
• process step 3106 Continued in A. If process step 304 is not met, d. H. there is no faulty ignition voltage after a minimum autarky time, method step 3004 follows.
• EEPROM eg ZE7 decrements to increase the robustness and the procedure in A continues.
• process step 308 an evaluation of the possible autarchy time follows. If the AUTARKIE time is less than a parameter AUTARKIE time min known to the system, ie faulty, method step 309 follows.
• step 308 If method step 308 is not fulfilled, i. H. there is no autarkic error, in step 3008 a decrementing of the autarchy time hitherto accumulated follows
• process step 310 the check of this error counter follows an allowable filter limit, e.g. 3. If this is exceeded, then in method step 3010, the warning lamp is actuated because the autarky time is too short and the minimum energy reserve voltage required is min. It follows process step 3110 Continued in B.
• an allowable filter limit e.g. 3.
• step 311 follows.
• method step 312 This is followed in method step 312 by an evaluation of the VERoff voltage. If the VERoff voltage is greater than a parameter known to the system VERoff max, d. H. faulty, then method step 313 follows. Here an already established error counter becomes too high
• method step 312 If method step 312 is not fulfilled, ie the ER voltage can be used up to sufficiently low values, without control problems at VZP, then in method step 3012 the error counter VERoff FZ is decremented if> 1 and the continuation in C. If method step 314 is not fulfilled, ie there is no filtered autarky time error, method step 315 follows.
• method step 316 the check of this error counter follows an allowed filter limit, for example 3. If this is exceeded, in method step 317 the warning lamp is triggered because of excessive VERoff voltage in the case of VZP instability.
• method step 3016 follows in which the error counter is decremented to increase the robustness. This is followed by method step 3116, in which further tasks are carried out in the initialization phase, which have nothing to do with the invention dealt with here.
• FIG. 4a shows an embodiment of the blocks 12a and 12b and 14 from FIG. 1 in an integrated module.
• the bidirectional switching converter VZP ⁇ -> VER the external coil Ll and a control capacity Cer are required for the up-converting operation VZP-> VER, and a control capacity Cvzp for the down-converting operation VER-> VZP in the autarkic case.
• VZP is generated by a down-converter VZP-> VST1 VSTl.
• the coil L2 and the control capacity Cvstl necessary.
• From VSTl is generated by a linear regulator VST2 (3.3V). For this the control capacity Cvst2 is necessary. From VST2 is generated by a linear regulator VST3 (1.8V). For this the control capacity Cvst3 is necessary.
• the control of the downward and upward conversion direction of the bi-directional switching converter VZP ⁇ -> VER is performed by an auto-detection circuit. In the simplest case, it is a circuit according to Figure 4b.
• the voltage VZP is connected to the resistor 400 on one side. This is connected to the resistor 402, the resistor 401 and the positive input of a comparator 404.
• the resistor 401 is connected to ground on the other side.
• the resistor 402 is on the other side with the collector of an NPN transistor 403 connected.
• the emitter of 403 is connected to ground.
• the base of transistor 403 is connected to the collector of transistor 405 and to one side of resistor 406.
• the emitter of transistor 405 is connected to ground.
• the base is connected to one side of the resistor 408.
• the other side of the resistor 408 is connected to the output of the comparator 404.
• the 406 is connected to the IC internal voltage VINT.
• the negative input of the comparator 404 is connected to a reference voltage 40.
• the positive supply of the comparator 404 is connected to VINT, the negative supply of the comparator 404 is connected to ground.
• the output of the comparator 404 is additionally connected on one side to the resistor 407. The other side of resistor 407 is connected to VINT.
• VZP is greater than a threshold voltage VZPth, for example, 5.2V
• VZPth for example, 5.2V
• Comparator 404 is grounded. This also turns off transistor 405 through resistor 408, i. he locks.
• Transistor T2 conducts and switches resistor 403 in parallel with resistor 401 of the input voltage divider.
• the input voltage at the positive input of the comparator 404 the center of the input voltage divider continues to drop. That is, the hysteresis formed stabilizes the new switching state of the comparator 404. Its output voltage remains at approximately 0V. The system is in self-sufficient condition.
• the low level at the output of the comparator 404 signals the switching converter the

Landscapes

• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Mechanical Engineering (AREA)
• Business, Economics & Management (AREA)
• Emergency Management (AREA)
• Secondary Cells (AREA)
• Air Bags (AREA)
• Dc-Dc Converters (AREA)
• Charge And Discharge Circuits For Batteries Or The Like (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=37563307

Family Applications (1)

Country Status (6)

Families Citing this family (9)

Family Cites Families (8)

• 2005
  • 2005-07-04 DE DE102005031085A patent/DE102005031085A1/de not_active Withdrawn
• 2006
  • 2006-05-22 CN CN200680024489XA patent/CN101218128B/zh not_active Expired - Fee Related
  • 2006-05-22 WO PCT/EP2006/062485 patent/WO2007003469A2/de active Application Filing
  • 2006-05-22 JP JP2008519883A patent/JP5015924B2/ja active Active
  • 2006-05-22 US US11/988,261 patent/US7831361B2/en not_active Expired - Fee Related
  • 2006-05-22 EP EP06763211A patent/EP1901940A2/de not_active Withdrawn

Non-Patent Citations (2)

Also Published As

Similar Documents

Legal Events