Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
  • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2200/00—Indexing scheme relating to amplifiers
  • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45534—Indexing scheme relating to differential amplifiers the FBC comprising multiple switches and being coupled between the LC and the IC
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
  • H03F2203/7215—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by a switch at the input of the amplifier

Definitions

• the present invention relates to audio amplifier circuits for use in wireless telephone and handheld devices .
• An external plug-in earphone/microphone is commonly used with a portable cellular telephone .
• the wireless cellular telephone to support both the handset speaker and the plug-in earphone , will typically include two independent amplifiers . Two amplifiers are typically required because the handset speaker and plug-in earphone must work independently and present different loads .
• a handset speaker load may be 8 ohms and the earphone load may be 32 ohms .
• the handset microphone and speaker are turned off when the external plug-in earphone/microphone is in use .
• Fig . 1 illustrates a typical prior art configuration of a switch selection circuit and amplifiers to support both a handset speaker and an external plug-in earphone .
• An selection switch 10 routes an audio input signal 20 to either a speaker amplifier circuit 30 or an earphone amplifier circuit 40.
• An amplifier circuit 30 , 40 will typically include an output amplifier stage 32 , 42 to drive the speaker or load and a preamplifier stage 33 , 43.
• An amplifier circuit 30 , 40 will typically include feedback loops 31 , 41 to decrease distortion and improve the audio quality .
• Kim suffers from one or more of the following disadvantages : the use of two separate independent amplifiers , including a preamplifier and output amplifier for a handset speaker, and for a plug-in earphone which introduces redundancy in the wireless cellular telephone circuitry, additional cost , increased size and weight of the cellular telephone , and increased power consumption .
• An exemplary embodiment of the present invention provides independently selectable audio amplifier output stages using only a single preamplifier stage (a single core amplifier or a single driver stage) .
• the preamplifier output may be selectively coupled to one of multiple audio amplifier output stages without degrading the performance of the output signal .
• a switching circuit or switching method selectively couples the preamplifier output to a selected amplifier output stage and also couples a feedback signal between the selected amplifier output stage and the preamplifier stage .
• the coupling circuit or coupling method may couple the preamplifier stage to a selected output stage simultaneously with a feedback loop or employ a delay in the coupling method.
• a dedicated integrated circuit an approximate reduction in the silicon die size of approximately 30 percent may be realized .
• the invention may be used in many types of communication devices and audio devices .
• Fig . 1 is a block diagram of a prior art phone circuit having dual amplifiers .
• Fig . 2 is a block diagram of an exemplary circuit having a single core preamplifier or drive circuit .
• Fig . 3 is a circuit diagram of exemplary amplifier output stages and selection devices of Fig . 2
• Fig . 4 is an exemplary control and timing diagram for controlling the circuit in Fig . 3.
• Fig . 5 is an exemplary digital control and timing circuit for controlling the circuit in Fig . 3.
• Fig . 6 is an alternate exemplary control and timing diagram for controlling the circuit in Fig . 3. - A -
• the present invention uses a single preamplifier (amplifier core or driver circuit) selectively coupled to one of multiple amplifier output stages .
• a first output stage may drive an 8 ohm load and a second output stage may drive a 32 ohm load.
• a selection or switching circuit also couples or switches a feedback loop that corresponds to a selected output stage such that the overall performance of the amplifier is not degraded.
• a typical application of the present invention is in a wireless device or a cellular telephone to amplify an audio signal and drive an audio transducer such as a speaker or earphone .
• an audio transducer such as a speaker or earphone .
• the invention may be applied to other product areas to amplify audio signals , other analog signals , or non-analog signals including carrier signals .
• an exemplary audio amplifier circuit 100 includes a preamplifier 110 stage (amplifier core or driver circuit) having audio inputs 112 , which may be differential inputs .
• the preamplifier 110 stage provides a voltage gain .
• the preamplifier 110 may include single or multiple amplification stages to, for example , amplify current and/or voltage .
• the audio inputs 112 are coupled to preamplifier inputs 132 , 133 via input resistors 130 , 131.
• Feedback loops 122 , 123 are coupled to the preamplifier inputs 132 , 133 via feedback resistors 120 , 121.
• the input resistors 130 , 131 or the feedback resistors 120 , 121 may be replaced by alternative circuitry depending upon the application .
• the feedback loop may be used to provide a DC source or bias voltage to stabilize the circuitry, control drift or saturation, control an input or output impedance, reduce signal distortion, or control frequency and gain characteristics .
• Other circuits such as biasing circuits (for constant current sources) and common mode feedback (for a differential architecture) may be used .
• the exemplary audio amplifier circuit 100 also includes multiple amplifier output stages : output stagel 150 , and output stage2 151 to drive loads such as a built-in speaker or an earphone .
• Each amplifier output stage 150 , 151 may include single or multiple amplification stages to, for example , amplify current and/or voltage .
• each output stage 150 , 151 may be implemented as a balanced CMOS multiple stage class-AB amplifier .
• preamplifier 110 stage is at least equal to or greater than the better performing output stage 150 , 151. Also, for optimal operation of the audio amplifier as a whole , it is desirable that the preamplifier 110 stage is biased similar to the selected output stage 150 , 151.
• a similar biasing scheme for the preamplifier 110 stage and output stages 150 , 151 promotes a fast start-up for a selected amplifier output stage 150 , 151.
• the output from the preamplifier 110 and the feedback loops 122 , 123 are selectively coupled (or switched) to or from each output stage 150 , 151.
• An exemplary switching method to connect the amplifier output stages 150 , 151 is performed by speaker select switches 140 and by earphone select switches 141.
• the speaker and earphone select switches 140 , 141 which may be implemented as a standard electro-mechanical switches or as a solid state switching devices such as CMOS transistors .
• the switching method may operate as quickly as the solid state device allows , or may operate or couple the amplifier stages at a slower rate (ramp) to control the coupling speed .
• the switching method may connect the preamplifier 110 output to an output stage 150 , 151 and disconnect the other output stage 150 , 151 , or the switching method may de-couple the preamplifier 110 output from all of the output stages 150 , 151.
• a switching method or procedure must be carefully implemented to reduce a possibility of oscillation or startup failure of the amplifier circuit
• Switching the feedback loop 122 , 123 may float the inputs to the preamplifier 110.
• Two switching devices 160 , 161 may be used to bias the feedback sense point to a common mode voltage, V CM to simulate a connected output stage .
• the output stage 150 , 151 When one or both of the output stages 150 , 151 are disconnected from the preamplifier 110 output , the output stage 150 , 151 is typically muted to reduce the amplifier ' s overall power consumption. The unused output stage 150 , 151 is then placed in a high impedance state . Most of the current consumption of the amplifier is related to the amplifier output stages 150 , 151. Therefore , when no output stages 150 , 151 are coupled to the preamplifier 110 output and the output stages 150 , 151 are operating in mute mode , power and current consumption of the amplifier may be reduced up to 80 percent .
• exemplary H-Bridge circuit configurations 200 are illustrated, using MOS transistors 241-244 for a first output stage 250 to drive a handset speaker 260 , and using MOS transistors 245-248 for a second output stage 251 to drive an earphone speaker 261.
• the handset speaker 260 and the earphone speaker 261 may have different impedances , for example an 8 ohm handset speaker and a 32 ohm earphone speaker .
• the first 250 and second 251 output stages include two PMOS transistors each 241 , 243 , 245 , 247 and two NMOS transistors each 242 , 244 , 246 , 248 connected in a rail-to-rail push-pull topology. Both output stages are biased in class-AB to minimize distortion and reduce power consumption
• the MOS transistor 241-244 gates are coupled to drive signals by selection devices (or switches) 210-213.
• the MOS transistor 245- 248 gates are coupled to drive signals by selection devices (or switches) 220-223.
• the selection devices 210-213 , 220-223 couple or decouple (connect , disconnect , or switch) the first output stage 250 or the second output stage 251 to or from the preamplifier stage 110 (as shown in Fig . 2 ) .
• the selection devices 210-213 , 220-223 may also be used to place the MOS transistors 241-244 , 245-248 in a high impedance state , for example to reduce power consumption, by coupling the MOS transistor 241-244 , 245-248 gates to a pre-selected voltage or bias source (such as connecting to V dd or to ground) .
• An output stage 150 , 151 is connected to a preamplifier stage via drive lines DRVp_ PMO s/ DRVp_ NMO s/ DRV N PMOS / DRV N _ NMOS -
• the selection devices 210-213 , 220-223 are shown such that neither the first output stage 250 nor the second output stage 251 are connected to the preamplifier stage 110.
• the selection devices 210 -213 , 220-223 are shown so that the first and second output stages 250 , 251 are operating in a high impedance state with the gates of PMOS transistors 241 , 243 , 245 , 247 are coupled to V dd , and NMOS transistor 242 , 244 , 246 , 248 coupled to ground. Operating all of the output stages in a high impedance state may be used to reduce the overall power consumption .
• selection devices 230 -235 selectively couple feedback signals to the preamplifier 110 stage via the feedback lines 270 , 271.
• a Mute function is implemented by selection devices 230 -231 to couple a common mode voltage (V CM + and V CM - ) to the preamplifier 110.
• Selection devices 232 -235 are used to selectively couple a selected output stage signal , as a feedback signal , to the preamplifier 110 stage .
• the selection devices 232 -235 are shown open since neither the first nor the second output stages 250 , 251 are coupled to the preamplifier stage 110 and a feedback loop from an output stage 250 , 251 is not necessary.
• the Mute function selection devices 230 -231 are normally closed when neither output stage is selected, presenting a common mode voltage to the preamplifier 110.
• the selection devices are controlled by a selection circuit (described below) and may be implemented as mechanical-electrical switches or as other devices such as transistors .
• a CMOS pass gate device may be used to implement each switch, or a transistor device operating in a linear or ramp mode may be used .
• MOS pass gate devices operate in a highly non-linear manner .
• Selection devices 230 , 231 are not critical since they do not couple an audio signal
• selection devices 210-213 and 220 -223 are not critical since they couple the high impedance MOS transistor 241-244 , 245-248 gates .
• selection devices 232 -235 may feed an audio signal back to the preamplifier stage input and the selection devices 232 - 235 should be chosen so that their on-resistance is smaller than a feedback resistor or the impedance of other feedback circuitry, so the non-linearity of the selection devices 232 -235 does not impact the overall performance of the amplifier .
• Selection devices 210-213 , 220 -223 , and 230 -235 may be controlled to select and deselect an output stage to or from the preamplifier 110 (as shown in Fig . 2 ) .
• a chronological or timed control sequence may be applied to the selection devices 210-213 , 220 -223 , and 230 -235 to reduce audible noise at the speaker, or to reduce a possibility of undesirable amplifier behavior such as oscillations or a failed start-up .
• An amplifier output stage is selected by coupling either the gates of the first output stage transistor 241-244 or the gates of the second output stage transistor 245-248 to the preamplifier output 110 by switching the output stage selection devices 210-213 , 220 -223.
• the mute selection devices 230-231 and feedback selection devices 232 -235 are then switched after a timed delay from the selection of the output amplifier 250 , 251.
• an exemplary timing sequence 400 illustrating the selection 401 of an amplifier output stage 250 (in Fig . 3 ) for the handset speaker 260 at time Sl by switching the select devices 210-213.
• the corresponding feedback loop for the selected amplifier output stage is then selected 402 from the selected output amplifier to the preamplifier after a time delay 404 has elapsed at S2.
• the time delay 404 may be approximately 5 nanoseconds .
• the mute select device 230 is switched off (opened) 403 at the same time that the feedback loop is selected 402 at S2 , facilitating a continuous bias signal to the preamplifier to reduce the start up time for the preamplifier 110 and selected output stage .
• the select devices 210 -213 first deselect the currently coupled output stage from the preamplifier stage 110 by placing the MOS transistors 241-244 in a high impedance state so that no audible "pops " can be transmitted to the handset speaker 260 at time S3.
• the corresponding feedback loop is then deselected 402 after a time delay 405 has elapsed at time S4.
• the exemplary timing sequence may also be used to correspondingly select or deselect the output stage 251 for the earphone speaker .
• an exemplary digital selection circuit 300 includes input select lines 140 , 141 to select a particular output stage, output stage select lines 320 , 321 to select an output stage , feedback select lines 322 , 323 to control feedback loops , and mute select lines 324. Operating modes of the digital selection circuit 300 depending upon the state of the input lines are shown in the table below .
• the outputs for controlling feedback loops 322 , 323 and a mute circuit output 324 contain feedback delay circuits 309 , 310 , 304.
• the delay timing parameters for the mute delay 304 and feedback delays 309 , 310 are generally matched, however, the delay times may be individually varied depending upon the application, for example , if the characteristics of a first output amplifier greatly differ from a second output amplifier .
• the select lines 140 , 141 are coupled to a NOR gate 303 , setting the NOR gate 303 output to ON (high state) .
• the NOR gate 303 output is coupled to the mute delay 304 , and after a pre-determined delay period, the mute output 324 is set to ON.
• the NOR gate output is also coupled to an inverter 301 , setting the inverter output to OFF .
• the inverter output is coupled to a pair of AND gates 305 , 306 setting the outputs of both AND gates to OFF .
• the outputs of both AND gates are coupled to the output stage select lines 320 , 321 and feedback delays 309 , 310.
• the output stage select lines 320 , 321 are set to OFF, and after a pre-determined delay period, the feedback select lines 322 , 323 are set to OFF, deselecting all output stages .
• the NOR gate 303 output is set to OFF and after a delay 304 , the mute output 324 is set to OFF .
• the NOR gate 303 output is also coupled to a latch circuit 330 comprised of an OR gate 302 , and two NAND gates 307 , 308.
• the latch circuit 330 stores the last state when either of the input lines Select 1 (140 ) or Select 2 (141) is set to ON.
• the output of inverter 301 is set to ON, enabling the pair of AND gates 305 , 306 to correspondingly select one of the output stage select lines 320 , 321 and, after a delay, one of the corresponding feedback select lines 322 , 323.
• a first select line of the two select lines (140 or 141) is set to ON, setting the second input line (141 or 140 ) to ON has no effect on the stored memory state of the latch circuit 330.
• This logic configuration has an advantage of preventing the simultaneous connection of both output stages and both feedback loops to the preamplifier stage .
• an exemplary selection sequence 600 is illustrated .
• the digital selection circuit 300 (Fig . 5) is in a mute mode 610 having no output stage selected, and the Select_l select line (141 in Fig . 5 ) is set to ON at tl , the Select_l output stage (and feedback loop) is selected .
• the Select_2 select line (140 in Fig . 5) is set to ON at t2 , only the Select_l output stage (and feedback loop) will be selected for a first period 611.
• the selection circuit 300 When the Select_l select line 141 is then set to OFF at t3 , and the Select_2 select line 140 is still set to ON, the selection circuit 300 will immediately select the Select_2 output stage (and feedback loop) during a second period 612. When the Select_2 select line 140 is then set to OFF at t4 , and the Select_l select line 141 is still set to OFF, the selection circuit 300 will operate in a mute mode during a third period 613.
• Presented in this invention is a circuit and method of switching the output of a single preamplifier to or from multiple amplifier output stages .

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• 2005
  • 2005-12-15 EP EP05854097A patent/EP1839378A4/de not_active Withdrawn
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