Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/004—Error avoidance
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/46—Multiprogramming arrangements
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
  • G06F1/08—Clock generators with changeable or programmable clock frequency
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
  • G06F1/32—Means for saving power
  • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
  • G06F1/3234—Power saving characterised by the action undertaken
  • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/16—Error detection or correction of the data by redundancy in hardware
  • G06F11/1629—Error detection by comparing the output of redundant processing systems
  • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30181—Instruction operation extension or modification
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30181—Instruction operation extension or modification
  • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
  • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
  • G06F2201/845—Systems in which the redundancy can be transformed in increased performance
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

• Transient errors caused by alpha particles or cosmic rays, are increasingly becoming a problem for semiconductor integrated circuits.
• a microcontroller essentially consists of memory modules (eg RAM, ROM, cache), a processor (CPU, Core) and input / output interfaces, so-called peripherals (eg A / D converter, CAN interface). Because memory elements can be effectively monitored with check codes (parity or ECC), and peripherals often application-specific monitored as part of a sensor or actuator signal path, there is a further redundancy approach in the sole doubling of the cores of a microcontroller.
• memory modules eg RAM, ROM, cache
• processor CPU, Core
• peripherals eg A / D converter, CAN interface
• microcontrollers with at least two integrated cores are also called dual-core
• Both cores execute the same program segment redundantly and in isochronous mode (lockstep mode), the results of the two cores are compared, and an error is then detected in the comparison for correspondence.
• This configuration of a dual-core system can be called a comparison mode.
• Dual-core architectures are also used in other applications to increase performance. Both cores execute different programs, program segments, and commands, which can increase system performance, so this configuration of a dual-core system can be called a performance mode. This system is also referred to as a symmetric multiprocessor system (SMP).
• SMP symmetric multiprocessor system
• comparison mode the output signals of the cores are compared with each other.
• performance mode the two cores work as a symmetric multiprocessor (SMP) system and execute different programs, program segments, or commands.
• SMP symmetric multiprocessor
• the clock frequency of a ⁇ C can also be changed during operation. For example, you can save power by lowering the clock frequency and thus reduce the power loss.
• a ⁇ C that allows switching between two modes there is a requirement, depending on the application, that the reliability characteristics for a mode must be boosted. For this purpose, no solution is known in the prior art.
• a method or a device for controlling a computer system having at least two execution units, wherein it is possible to switch over between at least two different operating modes of the computer system, has the advantage over known approaches that switching between the operating modes also involves switching the clock frequency of the computer system ,
• the clock frequency in the comparison mode it is advantageous for the clock frequency in the comparison mode to be higher than the clock frequency in the performance mode. In further applications, it may be particularly advantageous that the clock frequency in the performance mode is higher than the clock frequency in the comparison mode. It may also be advantageous for the ratio between the clock frequencies to be chosen such that an effective performance in the at least two operating modes is the same.
• At least one second clock frequency is generated in that a unit for clock change and / or adaptation is influenced by a signal of switching means, in particular a switching and comparison unit.
• a controllable PLL is used for generating at least a second clock frequency.
• at least one second clock frequency is generated in that at least two independent devices for frequency matching are present and can be switched over in a controlled manner between the at least two output signals of these devices.
• FIG. 1 shows a multiprocessor system with two execution units H100A and H1000b as well as a switching and comparison unit H101.
• FIG. 2 shows a multiprocessor system with two execution units H100A and H100B and with two clock change units H210 and H220.
• FIG. 4 shows a general switching and comparison component which generates a general mode signal.
• the present invention describes a method in which the switching of the clock frequency in a multiprocessor system is coupled with the switching between the at least two operating modes of such a processor system.
• the invention relates to a multiprocessor system with at least two Aus requirementshungsakuen and a switching and comparison unit, which can be switched between the at least two operating modes "performance mode” and “comparison mode".
• the overall performance of the processor system differs depending on the set operating mode.
• An execution unit can in the following designate both a processor / core / CPU, as well as an FPU (Floating Point Unit), DSP (Digital Signal Processor), coprocessor or ALU (Arithmetic Logical Unit).
• FPU Floating Point Unit
• DSP Digital Signal Processor
• ALU Arimetic Logical Unit
• This figure shows how the various conceivable modes can arise.
• the logical component of a switching logic Nl 10 is included in this figure. This first determines how many output signals there are. Furthermore, the switching logic NI lO determines which of the input signals contribute to which of the output signals. It can be an input signal to exactly one
• the circuit logic defines a function that assigns an element of the set ⁇ N160, ..., N16n ⁇ to each element of the set ⁇ N140, ..., N14n ⁇ .
• the processing logic N 120 then sets to each of the outputs N16i in which
• a first possibility is to compare all signals and to detect an error in the presence of at least two different values, which can be optionally signaled.
• a second possibility is to make a k out of m selection (k> m / 2). This can be realized by using comparators.
• an error signal can be generated if one of the signals is detected as deviating.
• a possibly different error signal can be generated if all three signals are different.
• a third option is to apply these values to an algorithm. This may be, for example, the formation of an average, a median, or the use of a Fault Tolerant Algorithm (FTA).
• FTA Fault Tolerant Algorithm
• This averaging can be done over the entire set of residual values, or preferably over a subset that is easy to form in HW. In this case, it is not always necessary to actually compare the values. For example, averaging only adds and divides, FTM, FTA, or median require partial sorting.
• an error signal can optionally also be output at sufficiently large extreme values
• the task of the processing logic is thus to determine the exact shape of the comparison operation for each output signal, and thus also for the associated input signals.
• the combination of the information of the switching logic Nl 10 (i.e., the above-mentioned function) and the processing logic (i.e., the determination of the comparison operation per output signal, i.e. per function value) is the mode information and this sets the mode information.
• Mode fixed In the general case this information is multivalued, ie not representable only via a logical bit. Not all the theoretically conceivable modes are useful in a given implementation, it is preferable to restrict the number of modes allowed. It should be emphasized that in the case of only two execution units, where there is only one compare mode, all the information can be condensed to only one logical bit. Switching from a performance mode to a comparison mode is characterized in the general case by the fact that execution units, which are displayed in the performance mode on different outputs, mapped in the comparison mode to the same output become.
• this is realized in that there is a subsystem of execution units in which in the performance mode all input signals N14i to be considered in the subsystem are switched directly to corresponding output signals N16i, while in the comparison mode they are all mapped to an output.
• switching can also be realized by changing pairings. It is represented by the fact that in the general case one can not speak of the performance mode and the comparison mode, although in a given form of the invention one can restrict the set of allowed modes such that this is the case. However, one can always speak of switching from the performance to the comparison mode (and vice versa).
• the switching is triggered either by the execution of special switching instructions, special instruction sequences, explicitly marked instructions or by the access to specific addresses by at least one of the execution units of the multiprocessor system.
• the fault circuit logic N 130 collects the error signals and can optionally passively switch outputs N16i off, for example, by interrupting them via a switch.
• the clock frequency of the processor system is switched such that the effective performance available to the user remains the same (or comparable within certain limits) independently of the operating mode. This must - starting from a
• the key advantage of this application is that the effective, user-usable performance is the same, i. regardless of the mode remains.
• a performance mode does not lead to a higher effective performance of the processor system in such a configuration, but to a lower power consumption and noise emission at the same performance compared to the operation in a comparison mode.
• overclocking may be conceivable in comparison mode within certain limits. This potentially leads to a higher one
• comparison mode If the comparison mode is operated at a reduced clock frequency, the execution of the program parts in this mode of operation is less error-prone, i. more robust compared to a version with a higher clock frequency.
• the program parts which are calculated in lockstep mode have a higher requirement for error detection as specified. In the present exemplary embodiment, however, not only the error detection is increased (security aspect), but potentially the probability of occurrence of errors reduced (reliability and safety increase).
• FIG. 1 shows a multiprocessor system with two execution units H10A and
• the switching and comparing unit Hl 10 generates a mode signal Hl 50 which is used by a clock changing unit H 120 to change the clock H 160 of the clock generating unit H130 such that when switching to the Comparison mode, the clock frequency is increased by exactly the factor by which the performance would increase in the performance mode compared to the comparison mode without switching the clock frequency. When switching from a performance to a comparison mode, the clock frequency is reduced by exactly the same factor.
• the adjusted clock H 140a, H 140b is then the other units in particular the
• the clock generation unit H130 can be a PLL (Phase Locked Loop) or a clock divider that can change it in a known manner from a basic clock of a H130 clock generation unit (e.g., RC resonator or quartz).
• PLL Phase Locked Loop
• a clock divider that can change it in a known manner from a basic clock of a H130 clock generation unit (e.g., RC resonator or quartz).
• the clock change unit H 120 decreases the clock when switching from the performance to the compare mode. This then causes a reduced sensitivity to transient errors in the comparison mode. Accordingly, the clock is increased again when switching from the comparison mode to the performance mode.
• the mode signal Hl 50 is shown in a general form in FIG.
• the signals and components N10, N120, N130, N140, N141, N142, N143, N14n, N160, N161, N162, N163, N16n of the switching and comparison component N200 have the same meaning as those of the switching and comparison component N100 in FIG FIG. 3.
• the mode signal Nl 50 and the error signal N170 are shown in this figure.
• the mode signal Nl 50 corresponds to the signal Hl 50 of Figure 1 and Figure 2.
• the optional error signal N170 is generated by the error circuit logic N130 which collects the error signals and is either a direct forwarding of the single error signals or a bundling of the error information contained therein.
• Mode signal NL 50 is optional, but its use outside of this component can be used to advantage in many places.
• the combination of the information of the switching logic Nl 10 (i.e., the above-mentioned function) and the processing logic (i.e., the determination of the comparison operation per output signal, i.e. per function value) is the mode information and sets the mode. This information is in general
• the mode signal brings the relevant mode information to the outside.
• a HW implementation is preferred shown so that the externally visible mode signal can be configured.
• the processing logic and circuitry are also configured to be configurable. Preferably, these configurations are coordinated. Alternatively, one can give only or additionally changes of the mode signal to the outside. This has advantages especially in a two-configuration.
• FIG. 2 shows an alternative using two clock change units H210 and H220.
• the two execution units H100A and H100B receive their clock H270a, H270b from the clock switch H200. This switches depending on a core mode signal Hl 50, generated by a switching and comparison unit
• the clock switch H200 has two clock inputs driven by the H240 and H250 clocks.
• the clock H240 is set by the clock change unit H210
• the clock H250 is set by the clock change unit H220.
• the clock change units H210 and H220 optionally receive a basic clock H260 from the clock generation unit
• This arrangement can be used to lower the clock for the execution units in the performance mode, so that the performance remains approximately the same in both modes. Likewise, this arrangement can be used to lower the clock in the comparison mode to reduce the sensitivity in the comparison mode against transient errors.

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• 2005
  • 2005-10-25 EP EP05801505A patent/EP1810150A2/de not_active Ceased
  • 2005-10-25 CN CNA2005800364878A patent/CN101048748A/zh active Pending
  • 2005-10-25 KR KR1020077009363A patent/KR20070067169A/ko not_active Application Discontinuation
  • 2005-10-25 CN CNB2005800364971A patent/CN100520730C/zh not_active Expired - Fee Related
  • 2005-10-25 WO PCT/EP2005/055548 patent/WO2006045806A2/de active Application Filing
  • 2005-10-25 US US11/666,412 patent/US20090125749A1/en not_active Abandoned

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