EP1763015A1 - Systèmes et procédés pour générer des tensions de référence - Google Patents

Systèmes et procédés pour générer des tensions de référence Download PDF

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Publication number
EP1763015A1
EP1763015A1 EP05019572A EP05019572A EP1763015A1 EP 1763015 A1 EP1763015 A1 EP 1763015A1 EP 05019572 A EP05019572 A EP 05019572A EP 05019572 A EP05019572 A EP 05019572A EP 1763015 A1 EP1763015 A1 EP 1763015A1
Authority
EP
European Patent Office
Prior art keywords
coupled
resistor
circuit
switch
resistor circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05019572A
Other languages
German (de)
English (en)
Inventor
Ching-Wei Lin
Chueh-Kuei Jan
Meng-Hsun Hsieh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TPO Displays Corp
Original Assignee
Toppoly Optoelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppoly Optoelectronics Corp filed Critical Toppoly Optoelectronics Corp
Priority to EP05019572A priority Critical patent/EP1763015A1/fr
Publication of EP1763015A1 publication Critical patent/EP1763015A1/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0428—Gradation resolution change
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general

Definitions

  • the present invention relates to electrical circuitry and, in particular, to systems and methods for generating reference voltages.
  • AMLCDs Active matrix liquid crystal displays
  • An AMLCD comprises a grid (or matrix) of picture elements (pixels) Thousands or millions of these pixels are used together to create an image on such a display.
  • TFT thin film transistor
  • TFTs act as switches to individually turn each pixel "on” (light) or "off' (dark).
  • a display usually has several power-saving modes.
  • a display can have an n-gradation mode (where n is an integer smaller than the number of levels in full gradation) in which an image is represented with fewer gradations, a partial display mode in which only a portion of the display is used to represent an image, and/or a standby mode in which the display is turned off temporarily until being activated again.
  • n-gradation mode where n is an integer smaller than the number of levels in full gradation
  • Integrating driving (reference voltage generating) circuits into display panels using TFT technology can largely reduce display module cost.
  • a conventional resistor string (R-string) approach is adopted for providing different voltages.
  • Fig.1 shows a prior art reference voltage generating circuit 10 disclosed in U.S. Patent No. 6,839,043 to Nakajima , which is incorporated herein by reference.
  • the reference voltage generating circuit 10 includes switch circuits 41 and 42, dividing resistors R1-R7, and switches SW15 and SW16.
  • the switch circuits 41 and 42 include switches SW11, SW12 and switches SW13, SW14, respectively.
  • the switches SW11-SW14 couple output terminals A and B of the R-string to a positive power supply Vcc and a power supply Vss, which has a lower voltage level with respect to the positive power supply Vcc.
  • the power supplies Vcc and Vss operate at fixed periods in opposite phases for row inversion driving methodology.
  • the dividing resistors R1 to R7 are connected in series between output terminals A and B of the R-string, with switches SW15 and SW16 interposed therebetween, respectively. Voltages V0, V7, and V1-V6 obtained by voltage division by the R-string are outputted to a digital-analog-converter (DAC).
  • DAC digital-analog-converter
  • Fig. 2 for a timing chart illustrating the operation of the reference voltage generating circuit 10.
  • the reference voltages V0 and V7 are both produced by connecting node A to the positive power supply Vcc and node B to the power supply Vss in a first driving period, and by connecting node B to the positive power supply Vcc and node A to the power supply Vss in a second driving period. Each such driving period alternates in a fixed interval based on control pulses ⁇ 1 and ⁇ 2, as shown in the timing chart of Fig. 2.
  • the reference voltages V1-V6 for intermediate gradations are produced by voltage division through the dividing resistors R1 to R7.
  • the switches SW15 and SW16 are opened (switched off) to stop the supply of current to the dividing resistors R1-R7 based on control pulse ⁇ 3.
  • the switches SW15 and SW16 are opened (switched off) to stop the supply of current to the dividing resistors R1-R7 based on control pulse ⁇ 3.
  • the voltage levels of V1 and V6 are represented with flat lines of zero voltage in Fig. 2 during power saving modes, the prior art reference voltage generating circuit 10 actually produces floating voltages when the R-string is disconnected from power supplies Vcc and Vss.
  • the prior art reference voltage generating circuit 10 has two perceived major drawbacks.
  • the switches SW15 and SW16 are used to disconnect the R-string from the power sources Vcc and Vss during power-saving modes.
  • MOSFETs metal-oxide semiconductor field-effect transistors
  • a TFT is a transistor the active, current-carrying layer of which is a thin film (usually a film of polysilicon).
  • the resistance of a TFT is usually much larger than that of a MOSFET.
  • the switches SW15 and SW16 typically are large enough to exhibit low turn-on resistance.
  • the reference voltage generating circuit 10 occupies a large amount of space.
  • the release voltage generating circuit 10 since the R-string is disconnected from the power sources Vcc and Vss, the release voltage generating circuit 10 exhibits floating voltage levels that are outputted to the DAC during power-saving modes This tends to result in the DAC operation being non-stable and can result in more power consumption.
  • An embodiment of such a system comprises an integrated reference voltage generating circuit comprising a resistor circuit comprising a plurality of resistors coupled in series, a first switch coupled between a first end of the resistor circuit and a first power source, a second switch coupled between the first end of the resistor circuit and a second power source, a third switch coupled to a second end of the resistor circuit, a fourth switch coupled to the second end of the resistor circuit, a first resistor coupled between the first end of the resistor circuit and the first switch, a second resistor coupled between the first end of the resistor circuit and the second switch, a third resistor coupled between the second end of the resistor circuit and the third switch, a fourth resistor coupled between the second end of the resistor circuit and the fourth switch, and a control circuit for controlling the first, second, third, and fourth switches.
  • Another embodiment of a system comprises an integrated reference voltage generating circuit, a multiplexer for selecting from input data obtained in different operating modes as output data of the system, a digital-to-analog controller coupled to the multiplexer and the integrated reference voltage generating circuit for processing input data of an image displayed with full gradation, and a control circuit for sending signals to the integrated reference voltage generating circuit and the multiplexer based on an operating mode of the system.
  • An embodiment of a method for generating reference voltages comprises providing a resistor circuit comprising a plurality of resistors coupled in series, coupling first and second ends of the resistor circuit to a same power source when displaying an image with reduced power, and coupling the first end of the resistor circuit to a first power source and the second end of the resistor circuit to a second power source when displaying an image with full gradation.
  • Some embodiments can potentially reduce power consumption and/or compensate for charge injection effect. As such, some embodiments may be well suited for use in display systems, such as panel displays.
  • FIG. 3 depicts an embodiment of an integrated reference voltage generating circuit 30.
  • the integrated reference voltage generating circuit 30 includes a resistor circuit 32, switches SW1-SW4, resistors R1-R4, voltage sources Vcc and Vss, and a control circuit 34.
  • the power sources Vcc provide higher voltages then the power sources Vss.
  • the resistor circuit 32 includes a plurality of dividing resistors Rd1-Rd63 coupled in series.
  • the switch SW1 is coupled between node C of the resistor circuit 32 and the power source Vss
  • the switch SW2 is coupled between node C of the resistor circuit 32 and the power source Vcc
  • the switch SW3 is coupled between node D of the resistor circuit 32 and the power source Vss
  • the switch SW4 is coupled between node D of the resistor circuit 32 and the power source Vcc.
  • the resistor R1 is coupled between node C of the resistor circuit 32 and the switch SW1
  • the resistor R2 is coupled between node C of the resistor circuit 32 and the switch SW2
  • the resistor R3 is coupled between node D of the resistor circuit 32 and the switch SW3
  • the resistor R4 is coupled between node D of the resistor circuit 32 and the switch SW4.
  • the integrated reference voltage generating circuit 30 provides reference voltages by voltage division of the resistor circuit 32.
  • the integrated reference voltage generating circuit 30 provides reference voltages V0-V63 between two adjacent dividing resistors of the resistor circuit 32
  • the switches SW1-SW4 are turned on or off based on signals generated by the control circuit 34.
  • the switches SW1-SW4 can be made of transistors of different doping types.
  • the switches SW1 and SW3 can be N-type transistors, and the switches SW2 and SW4 can be P-type transistors, or vice versa.
  • switches SW1 and SW3 are N-type transistors and the switches SW2 and SW4 are P-type transistors, the switches SW1 and SW3 are turned on (closed circuit) and the switches SW2 and SW4 are turned off (open circuit) when receiving a control signal of "1"(high voltage level), and the switches SW1 and SW3 are turned off and the switches SW2 and SW4 are turned on when receiving a control signal of "0" (low voltage level).
  • ⁇ 1 - ⁇ 4 represent control pulses, each with two states: high and low.
  • V0, V1, V62 and V63 are shown for illustrating the operation of the integrated reference voltage generating circuit 30 during the normal mode and the power saving modes.
  • the polarity of the LC cell voltage is reversed on alternative intervals.
  • the reference voltage V0 and V63 are both produced by coupling node C of the resistor circuit 32 to the power supply Vcc and node D of the resistor circuit 32 to the power supply Vss in a first driving period, and by coupling node C of the resistor circuit 32 to the power supply Vss and node D of the resistor circuit 32 to the power supply Vcc in a second driving period.
  • Each such driving period alternates in a fixed interval based on control pulses ⁇ 1 and ⁇ 2, as shown in a timing chart of Fig. 4.
  • the control circuit 34 provides a control pulse ⁇ 4 of alternating high and low levels at the fixed interval and a control pulse ⁇ 3 of high level, and therefore generates control pulses ⁇ 1 and ⁇ 2 for the switches SW1-SW4, as shown in Fig. 4.
  • the resistor circuit 32 is coupled to power sources Vcc and Vss through the switches SW4 and SW1, respectively.
  • the resistor circuit 32 is coupled to power sources Vcc and Vss through the switches SW2 and SW3, respectively.
  • Intermediate reference voltages V1-V62 are generated by voltage division by the dividing resistors Rd1-Rd63 of the resistor circuit 32.
  • the control pulse ⁇ 3 switches to low level and the control pulse ⁇ 4 remains unchanged as in the normal mode, thereby generating the control signals ⁇ 1 and ⁇ 2each having a high level. Consequently, the switches SW2 and SW4 are turned off, disconnecting the resistor circuit 32 from the power source Vcc. At the same time, the switches SW1 and SW3 are turned on, coupling the resistor circuit 32 to the power source Vss. Therefore, during the power-saving mode, no current flows through the resistor circuit 32 and the power consumption from the diving resistors can be reduced. Although no current flows through the resistor circuit 32, both ends of the resistor circuit 32 are still coupled to Vss during the power-saving mode.
  • the integrated reference voltage generating circuit 30 can reduce power consumption without occupying large circuit space and without influencing the stability of the DAC during power-saving mode.
  • Fig. 5 is a diagram showing an equivalent circuit of a pixel 50.
  • the pixel 50 includes a TFT for turning on and off the pixel 50, a storage capacitor Cst for data storage, and a liquid crystal capacitor Clc representing the capacitance of the liquid crystal material. Data sent to the pixel 50 is stored in the capacitors Cst and Clc.
  • the parasitic capacitance of the pixel 50 is represented by a parasitic capacitor Cgd.
  • a signal from a gate line turns on the TFT, allowing data sent from a data line to be stored in the capacitors Cst and Clc.
  • reference voltages generated by an integrated reference voltage generating circuit are sent to a DAC, which in turn selects a voltage from the reference voltages and sends the selected voltage to the data line.
  • the charge-injection effect is a phenomenon of level change caused by stray capacitance represented by the parasitic capacitor Cgd.
  • Fig. 6 is a diagram illustrating the charge-injection effect.
  • Vgate represents the voltage sent to the gate line
  • Vpixel (dashed line) represents the ideal voltage obtained across the capacitors Cst and Clc if a voltage of Vp is sent to the data line
  • Vpixel' represents the actual voltage obtained across the capacitors Cst and Clc if a voltage of Vp is sent to the data line. Due to charge-injection effect, Vpixel' differs from Vpixel in that it suffers a voltage drop ⁇ Vp, potentaillycausing loss of data stored in the capacitors Cst and Clc.
  • Embodiments of an integrated reference voltage generating circuit can potentially compensate for the charge-injection effect using the resistors R1- R4. Based on capacitance of the capacitors Cst, Clc and Cgd, the voltage drop ⁇ Vp can be calculated. Through the resistors R1-R4, different voltages can therefore be provided at both ends of the resistor circuit 32 for compensating for the voltage drop ⁇ Vp.
  • the resistance of the resistors R1-R4 depends on the value of ⁇ Vp.
  • the resistors R1 and R4 have the same resistance, and the resistors R2 and R3 have the same resistance.
  • Fig. 7 is another embodiment of an integrated reference voltage generating circuit 70.
  • the integrated reference voltage generating circuit 70 includes a resistor circuit 32, switches SW1-SW4, resistors R1-R4, voltage sources Vcc and Vss, and a control circuit 34.
  • the power sources Vcc provide higher voltages then the power sources Vss.
  • the resistor circuit 32 includes a plurality of dividing resistors Rd1-Rd63 coupled in series.
  • the integrated reference voltage generating circuit 70 differs from the prior art voltage generating circuit 10, at least in one respect, in that it includes resistors R1-R4 for compensating for the charge-injection effect.
  • Fig. 8 is a schematic diagram of an embodiment of a display system 80 incorporating embodiments of integrated reference voltage generating circuit.
  • the display system 80 of Fig. 8 includes MUX devices 81 and 82, a buffer 83, a control circuit 84, a timing controller 85, a DAC 87 and a reference generating circuit 89.
  • the reference generating circuit 89 could be configured as the integrated reference generating circuits 30 and 70 shown in Fig. 3 and 7, for example, for providing reference voltages to the DAC 87.
  • the MUX device 81 selects from partial display mode input data, 8-color mode input data or normal mode input data as output data.
  • the reference generating circuit 89 When operating in normal mode, the reference generating circuit 89 performs voltage division and provides the DAC 87 a plurality of reference voltages. The MUX device 81 then selects the normal mode input data having been processed by the DAC 87 and the buffer 83 as the output data.
  • the resistor circuit adopted in the reference generating circuit 89 When operating in power-saving modes, such as partial display mode and 8-color mode, the resistor circuit adopted in the reference generating circuit 89 either has both ends coupled to a power source (such as when using the integrated reference generating circuits 30) or disconnected from a power source (such as when using the integrated reference generating circuits 70). The MUX device 81 then selects the partial display mode input data or the 8-color mode input data as the output data.
  • Integrated reference voltage generating circuits can potentially occupy less circuit space than prior art structures.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
EP05019572A 2005-09-08 2005-09-08 Systèmes et procédés pour générer des tensions de référence Withdrawn EP1763015A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP05019572A EP1763015A1 (fr) 2005-09-08 2005-09-08 Systèmes et procédés pour générer des tensions de référence

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Application Number Priority Date Filing Date Title
EP05019572A EP1763015A1 (fr) 2005-09-08 2005-09-08 Systèmes et procédés pour générer des tensions de référence

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008124051A1 (fr) * 2007-04-04 2008-10-16 Atmel Corporation Dispositif de commande pour un panneau d'affichage de dispositif d'affichage à cristaux liquides (lcd)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020097208A1 (en) * 2001-01-19 2002-07-25 Nec Corporation Method of driving a color liquid crystal display and driver circuit for driving the display as well as potable electronic device with the driver circuit
EP1335344A2 (fr) * 2002-02-08 2003-08-13 Seiko Epson Corporation Méthode et circuit de génération de tension de référence, circuit de commande d'affichage et dispositif d'affichage avec correction de gamma et consommation d'énergie réduite
WO2004059603A2 (fr) * 2002-12-26 2004-07-15 Casio Computer Co., Ltd. Dispositif d'entrainement d'affichage et procede de commande d'entrainement
JP2004348122A (ja) * 2003-04-28 2004-12-09 Matsushita Electric Ind Co Ltd 液晶表示パネル駆動装置及び液晶表示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020097208A1 (en) * 2001-01-19 2002-07-25 Nec Corporation Method of driving a color liquid crystal display and driver circuit for driving the display as well as potable electronic device with the driver circuit
EP1335344A2 (fr) * 2002-02-08 2003-08-13 Seiko Epson Corporation Méthode et circuit de génération de tension de référence, circuit de commande d'affichage et dispositif d'affichage avec correction de gamma et consommation d'énergie réduite
WO2004059603A2 (fr) * 2002-12-26 2004-07-15 Casio Computer Co., Ltd. Dispositif d'entrainement d'affichage et procede de commande d'entrainement
JP2004348122A (ja) * 2003-04-28 2004-12-09 Matsushita Electric Ind Co Ltd 液晶表示パネル駆動装置及び液晶表示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 2003, no. 12 5 December 2003 (2003-12-05) *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008124051A1 (fr) * 2007-04-04 2008-10-16 Atmel Corporation Dispositif de commande pour un panneau d'affichage de dispositif d'affichage à cristaux liquides (lcd)
US7907110B2 (en) 2007-04-04 2011-03-15 Atmel Corporation Display controller blinking mode circuitry for LCD panel of twisted nematic type

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