EP1697829A1 - Appareil et procede de commande de circuit logique programmable et programme associe - Google Patents

Appareil et procede de commande de circuit logique programmable et programme associe

Info

Publication number
EP1697829A1
EP1697829A1 EP04808169A EP04808169A EP1697829A1 EP 1697829 A1 EP1697829 A1 EP 1697829A1 EP 04808169 A EP04808169 A EP 04808169A EP 04808169 A EP04808169 A EP 04808169A EP 1697829 A1 EP1697829 A1 EP 1697829A1
Authority
EP
European Patent Office
Prior art keywords
module
memory
logic circuit
address
programmable logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04808169A
Other languages
German (de)
English (en)
Other versions
EP1697829A4 (fr
Inventor
Kazuaki Murakami
Syuichi Tokyo Electron Device Limited KIKUCHI
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of EP1697829A1 publication Critical patent/EP1697829A1/fr
Publication of EP1697829A4 publication Critical patent/EP1697829A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/13—Plc programming
    • G05B2219/13083—Jumps
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/13—Plc programming
    • G05B2219/13109—Pld programmable logic device software for plc

Definitions

  • PROGRAMMABLE LOGIC CIRCUIT CONTROL APPARATUS PROGRAMMABLE LOGIC CIRCUIT CONTROL METHOD AND PROGRAM
  • the present invention relates to a programmable logic circuit control apparatus, a programmable logic circuit control method and a program.
  • ASICs Application Specific Integrated Circuits
  • programmable logic circuits such as a field programmable gate array (FPGA) (e.g., XC series by XILBSfX in U.S.A.) and a programmable logic device (PLD) are widely used.
  • FPGA field programmable gate array
  • PLD programmable logic device
  • a programmable logic circuit can freely change the logic configuration of an internal logic circuit according to circuit information loaded.
  • the schemes can make the scale of an ASIC smaller by reconfiguring a programmable logic circuit.
  • complex ASICs do not just execute processes one after another.
  • ASICs are generally expected to execute a process in complicated procedures including conditional branching, returning from a branched step and loops.
  • the aforementioned schemes of reconfiguring a programmable logic circuit face a difficulty in smoothly executing multiple processes in such comphcated procedures and suffer a long overhead. Disclosure of Invention Accordingly, it is an object of the present invention to provide a programmable logic circuit control apparatus, a programmable logic circuit control method and a program, which facilitate smooth execution of multiple processes in comphcated procedures.
  • a programmable logic circuit control apparatus comprises: a controller (4) which supplies a control signal to an external programmable logic circuit (1) having a function of changing a logic configuration in accordance with a supplied control signal; a module storage memory (2) which stores a plurality of modules each comprised of data defining a logic configuration of the programmable logic circuit (1); and a module usage order designation memory (3) which has a plurality of ordered memory positions, each of the memory positions storing data for designating an address of a memory position of the module storage memory (2) in which a module to be executed is stored or storing data for designating an address of another memory position of this module usage order designation memory (3), wherein the controller (4) acquires data stored at a memory position in the module usage order designation memory (3), determines which of an address of the memory position storing the module and an address of the another memory position is designated by the acquired data, when having determined that the acquired data designates an address of the module, acquires the module stored in a memory position indicated by the controller
  • the programmable logic circuit control apparatus easily and smoothly executes a process of changing the logic configuration of a programmable logic circuit even when the process involves comphcated procedures including branch processes.
  • the data may include condition definition data designating a condition to start a process of acquiring data stored at the another memory position.
  • the controller (4) may determine whether a condition designated by the condition definition data included in the acquired data is fulfilled or not when having determined that the acquired data designates another memory position, may acquire data stored at the another memory position of the module usage order designation memory (3) when having determined that the condition is fulfilled, and may abort acquisition of data at the another memory position when having determined that the condition is not fulfilled.
  • the logic circuit control apparatus with the structure easily and smoothly executes a process of changing the logic configuration of a programmable logic circuit even when the process involves comphcated procedures including conditional branching.
  • the condition designated by the condition definition data may relate to a value given by a signal which is generated at a predetermined node of the programmable logic circuit (1).
  • the controller (4) may acquire the signal from the node of the programmable logic circuit (1). Based on the value given by the acquired signal, the controller (4) may determine whether that condition which is designated by the condition definition data included in the data acquired from the module usage order designation memory (3) is filled or not.
  • Data stored at a memory position in the module usage order designation memory (3) may include identification data for identifying which one of an address of the memory position storing a module and an address of another memory position is designated by the stored data.
  • the controller (4) may determine which of an address of the memory position storing the module and an address of the another memory position is designated.
  • a programmable logic circuit control apparatus acquires a module comprised of data defining a logic configuration of an external programmable logic circuit (1) having a function of changing a logic configuration in accordance with a supplied control signal from a module storage memory (2) which stores a plurality of modules, generates a control signal which controls the programmable logic circuit (1) to take a logic configuration defined by the acquired module and supplies generated control signal to the programmable logic circuit (1), and comprises: means which acquires data stored at a memory position in an external module usage order designation memory (3) which has a plurality of ordered memory positions, each of the memory position storing data for designating an address of a memory position of the module storage memory (2) in which a module to be executed is stored or storing data for designating an address of another memory position of this module usage order designation memory (3), from the module usage order designation memory (3); means which determines which of an address of the memory position storing the module and an address of the another memory position is designated by acquired data; means which, when it is determined that the acquired data
  • a programmable logic circuit control apparatus also easily and smoothly executes a process of changing the logic configuration of a programmable logic circuit even when the process involves comphcated procedures including branch processes.
  • a programmable logic circuit control method supplies a control signal to an external programmable logic circuit (1) having a function of changing a logic configuration in accordance with the supplied control signal, and comprises the steps of: storing a plurality of modules each comprised of data defining a logic configuration of the programmable logic circuit (1); storing data for designating an address of a memory position storing a module or an address of another memory position at each of a plurality of ordered memory positions; acquiring data stored at each of the memory positions; determining which of an address of the memory position storing the module and an address of the another memory position is designated by the acquired data; when it is determined that the acquired data designates an address of a memory position storing a module, acquiring the module stored in the memory position indicated by the address, generating a control signal which controls the programmable logic circuit
  • a programmable logic circuit control method easily and smoothly executes a process of changing the logic configuration of a programmable logic circuit even when the process involves comphcated procedures including branch processes.
  • a programmable logic circuit control method acquires a module comprised of data defining a logic configuration of an external programmable logic circuit (1) having a function of changing a logic configuration in accordance with a supphed control signal from a module storage memory (2) which stores a plurahty of modules, generates a control signal which controls the programmable logic circuit (1) to take a logic configuration defined by the acquired module and supplies the control signal to the programmable logic circuit (1), and comprises the steps of: acquiring data stored at a memory position in an external module usage order designation memory (3) which has a plurahty of ordered memory positions, each of the memory positions storing data for designating an address of a memory position of the module storage memory (2) in which a module to be executed is stored or storing data for designating an address of another memory position of this module usage
  • a program according to the fifth aspect of the invention allows a computer to function as: a controller (4) which supplies a control signal to an external programmable logic circuit (1) having a function of changing a logic configuration in accordance with the supphed control signal; a module storage memory (2) which stores a plurahty of modules each comprised of data defining a logic configuration of the programmable logic circuit (1); and a module usage order designation memory (3) which has a plurahty of ordered memory positions, each of the memory positions storing data for designating an address of a memory position of the module storage memory (2) in which a module to be executed is stored or storing data for designating an address of another memory position of the module usage order designation memory (3), , wherein the controller (4) acquires data stored at a memory position in the module usage order designation memory (3), determines which of an address of
  • a computer which executes the program easily and smoothly executes a process of changing the logic configuration of a programmable logic circuit even when the process involves comphcated procedures including branch processes.
  • a program according to the sixth aspect of the invention allows a computer to function as a programmable logic circuit control apparatus that acquires a module comprised of data defining a logic configuration of an external programmable logic circuit (1) having a function of changing a logic configuration in accordance with a supplied control signal from a module storage memory (2) which stores a plurahty of modules, generates a control signal which controls the programmable logic circuit (1) to take a logic configuration defined by the acquired module and supphes generated control signal to the programmable logic circuit (1), and further allows the computer to perform the functions of: acquiring data stored at a memory position in an external module usage order designation memory (3) which has a plurahty of ordered memory positions, each of the memory positions storing data for designating an address of a memory position of the module storage memory (2) in which a module to be executed is
  • a computer which executes the program also easily and smoothly executes a process of changing the logic configuration of a programmable logic circuit even when the process involves comphcated procedures including branch processes.
  • the present invention realizes a programmable logic circuit control apparatus and method, and a program, which facihtate smooth execution of multiple processes in comphcated procedures.
  • FIG 1 is a diagram iUustrating the structure of a programmable logic circuit control apparatus according to one embodiment of the present invention
  • FIG 2 is an exemplary diagram showing the configuration of a programmable logic circuit
  • FIG 3 is a diagram showing the configuration of an input logic circuit BIBC
  • FIG 4 is a diagram showing the configuration of a logic circuit BFBC
  • FIG 5 is a diagram showing the configuration of a logic circuit BQBC
  • FIG 6 is a diagram showing the configuration of an output logic circuit BOBC
  • FIG 7A is a diagram showing the structure of a matrix switch
  • FIG 7B is a diagram showing the structure of switches which constitutes the matrix switch
  • FIG 8 is an exemplary diagram showing the data structure of data stored in a module address memory section
  • FIG 9 is a flowchart uTustrating the flow of a process which is executed by a circuit control section.
  • FIG 1 illustrates the structure of the programmable logic circuit control apparatus.
  • the programmable logic circuit control apparatus includes a programmable logic circuit 1, a module memory section 2, a module address memory section 3, and a circuit control section 4.
  • the programmable logic circuit 1, the module memory section 2 and the module address memory section 3 are connected to the circuit control section 4.
  • the programmable logic circuit 1 is comprised of a configurable logic block (CLB), which is used to construct, for example, a field programmable gate array (FPGA) produced by XILINX in U.S.A., a matrix switch, a wiring material and so forth.
  • CLB configurable logic block
  • FPGA field programmable gate array
  • the programmable logic circuit 1 changes (reconfigures) its logic configuration (i.e., the correlation between signals to be input to the programmable logic circuit 1 and signals to be output therefrom) under the control of the circuit control section 4.
  • the programmable logic circuit 1 includes input logic circuits BIBC, logic circuits BFBC, logic circuits BQBC, output logic circuits BOBC, a matrix switche BLSW, wires LVLO to LVL4 and wires LHLO to LHL2.
  • Each of the wires LVLO to LVL4 and the wires LHLO to LHL2 consists of 63 signal lines.
  • the input logic circuits BIBC, the logic circuits BFBC, the logic circuits BQBC and the output logic circuits BOBC are connected to the wires LVLO to LVL4 via buses.
  • the wires LVLO to LVL4 and the wires LHLO to LHL2 are connected to one another or disconnected from one another by the matrix switch BLSW.
  • the matrix switch BLSW realizes variable interconnection.
  • Each of the input logic circuit BIBC, the logic circuit BFBC, the logic circuit BQBC and the output logic circuit BOBC is constituted by, for example, a TTL (Transistor- Transistor Logic) circuit or a CMOS (Complementary Metal-Oxide Semiconductor) logic circuit or so.
  • Each input logic circuit BIBC supplies a signal input to the programmable logic circuit 1 to the wire LVLO in a mode according to the control of the circuit control section 4.
  • Each input logic circuit BIBC is comprised of, for example, an output select circuit OSELl as shown in FIG 3.
  • the output select circuit OSELl is connected to the wire LVLO via buses IoA(l) to IoA(63) of 63 bits.
  • the output select circuit OSELl supphes a 4-bit signal input to the programmable logic circuit 1 to the signal lines constituting the wire LVLO. Based on the value of a 24-bit control signal Configl supphed from the circuit control section 4 or so, the output select circuit OSELl decides to which signal line in the wire LVLO the signal is to be supphed. The output select circuit OSELl then sends the signal to the decided signal line.
  • the output select circuit OSELl can decide not to send the signal to any of the signal lines of the wire LVLO.
  • Each logic circuit BFBC performs a logical operation on a signal supphed from the wire LVLO or LVL1 under the control of the circuit control section 4.
  • the logic circuit BFBC sends the acquired signal to the wire LVL1 or LVL2.
  • Each logic circuit BFBC includes, for example, an input select circuit ISEL1, a basic function cell FBC and an output select circuit OSEL2 as shown in FIG 4.
  • the input select circuit ISEL1 is connected to the wire LVLO or LVL1 via buses
  • the input select circuit ISEL1 acquires a 6-bit signal among signals supphed from the wire LVLO or LVL1 to which the input select circuit ISEL1 is connected.
  • the input select circuit ISEL1 sends the acquired signal to the basic function cell FBC.
  • the input select circuit ISEL1 decides from which six signal lines in the 63 signal lines of the wire LVLO or LVL1 the signal is to be acquired.
  • the input select circuit ISEL1 acquires the signal from the decided signal lines.
  • the input select circuit ISEL1 then sends the acquired signal to the basic function cell FBC.
  • the input select circuit ISEL1 can decide not to acquire a signal from any of the signal lines of the wire LVLO or LVL1. In this case, the input select circuit ISEL1 sends a signal representing a logic value "0" to the basic function cell FBC.
  • the basic function cell FBC includes, for example, a select circuit SEL and a latch circuit L as shown in FIG 4.
  • the basic function cell FBC selects a total of two bits, one bit from the first to 64-th bits of a 130-bit control signal ConfigFf supphed from the circuit control section 4 or so, and one bit from the 65-th to 128-th bits of the control signal ConfigFf.
  • the basic function cell FBC sends the 2-bit signal (signal XY) to the output select circuit OSEL2.
  • the basic function ceh FBC decides whether or not to latch the signal XY.
  • the basic function cell FBC then sends a signal EN indicating the result of the decision to the latch circuit L.
  • the latch circuit discriminates whether or not it is decided to latch the signal XY.
  • the latch circuit L holds the value of the signal XY.
  • the latch circuit L sends a 2-bit signal having the held value to the output select circuit OSEL2 as a signal QY.
  • the latch circuit L sends a 2-bit signal having a value currently held (i.e., the old value of the signal XY) to the output select circuit OSEL2 as the signal QY.
  • the individual sections of the programmable logic circuit 1 perform latching in synchronism with a clock signal.
  • the programmable logic circuit 1 may acquire the clock signal externally.
  • the programmable logic circuit 1 may have a circuit to generate the clock signal.
  • the output select circuit OSEL2 is connected to the wire LVLl or LVL2 via buses IoB(l) to IoB(63) of 63 bits.
  • the output select circuit OSEL2 supphes the signal XY and the signal QY, a total of four bits, supphed from the basic function cell FBC to the signal lines constituting the wire LVLl or LVL2.
  • the output select circuit OSEL2 decides to which signal line in the wire LVLl or LVL2 the 4-bit signal is to be supphed, based on the value of a 24-bit control signal ConfigFo supphed from the circuit control section 4 or so.
  • the output select circuit OSEL2 then sends the 4-bit signal to the decided signal line.
  • the output select circuit OSEL2 can decide not to send the signal to any of the signal lines of the wire LVLl or LVL2.
  • Each logic circuit BQBC holds a signal supphed from the wire LVL2 or LVL3 in a mode according to the control of the circuit control section 4.
  • the logic circuit BQBC gives the signal to the logic circuit BFBC in the programmable logic circuit 1 after reconfigure to a next logic configuration via the wire LVLO or LVLl.
  • Each logic circuit BQBC includes, for example, an input select circuit ISEL2, a function ceh QBC and an output select circuit OSEL3 as shown in FIG 5.
  • the input select circuit ISEL2 is connected to the wire LVL2 or LVL3 via buses IiB(l) to EB(63) of 63 bits.
  • the input select circuit ISEL2 acquires a 4-bit signal among signals supphed from the wire LVL2 or LVL3 to which the input select circuit ISEL2 is connected.
  • the input select circuit ISEL2 sends the acquired signal to the function ceh QBC.
  • the input select circuit ISEL2 decides from which four signal lines in the 63 signal lines of the wire LVL2 or LVL3 the signal is to be acquired.
  • the input select circuit ISEL2 acquires signals of a total of four bits from the decided signal lines, and sends the acquired signal to the function ceh QBC.
  • the input select circuit ISEL2 can decide not to acquire a signal from any of the signal lines of the wire LVL2 or LVL3. In this case, the input select circuit ISEL2 sends a signal representing a logic value "0" to the function cell QBC.
  • the function ceh QBC is comprised of a latch circuit or so.
  • the function ceh QBC holds the value of a 4-bit signal supphed from the input select circuit ISEL2.
  • the function ceh QBC sends a signal having the held value to the output select circuit OSEL3 as a signal QY2.
  • the output select circuit OSEL3 is connected to the wire LVL3 or LVL4 via buses IoC(l) to IoC(63) of 63 bits.
  • the output select circuit OSEL3 supphes the 4-bit signal QY2 supphed from the function ceh QBC to the signal lines constituting the wire LVL3 or LVL4.
  • the output select circuit OSEL3 decides to which signal line in the wire LVL3 or LVL4 the signal QY2 is to be supphed, based on the value of a 24-bit control signal ConfigQo supphed from the circuit control section 4 or so. The output select circuit OSEL3 then sends the signal to the decided signal line. The output select circuit OSEL3 can decide not to send the signal to any of the signal lines of the wire LVL3 or LVL4.
  • Each output logic circuit BOBC outputs a signal supphed from the wire LVL4 in a mode according to the control of the circuit control section 4.
  • Each output logic circuit BOBC includes, for example, an input select circuit ISEL3 and a function ceh OBC as shown in FIG 6.
  • the input select circuit ISEL3 is connected to the wire LVL4 via buses HC(l) to HC(63) of 63 bits.
  • the input select circuit ISEL3 acquires a 4-bit signal among signals supphed from the wire LVL4 to which the input select circuit ISEL3 is connected.
  • the input select circuit ISEL3 sends the acquired signal to the function ceh OBC.
  • the input select circuit ISEL3 decides from which four signal lines in the 63 signal lines of the wire LVL4 the signal is to be acquired.
  • the input select circuit ISEL3 acquires signals of a total of four bits from the decided signal lines, and sends the acquired signal to the function ceh OBC.
  • the input select circuit ISEL3 can decide not to acquire a signal from any of the signal lines of the wire LVL4. In this case, the input select circuit ISEL3 sends a signal representing a logic value "0" to the function ceh OBC.
  • the function ceh OBC is comprised of a latch circuit or so.
  • the function ceh OBC holds the value of a 4-bit signal supphed from the input select circuit ISEL3 or passes this signal. Whether to hold or pass the signal is decided based on the 25-th to 28-th bits in the control signal ConfigO.
  • the function ceh OBC sends out a signal having the held value or the signal that has passed as an output signal (signal Y) of the programmable logic circuit 1.
  • the matrix switch BLSW has a capability of electrically connecting or disconnecting the wires LVLO to LVL4 and the wires LHLO to LHL2 to one another or from one another.
  • the matrix switch BLSW electrically connects or disconnects the wires LVLO to LVL4 from one another, electrically connects or disconnects the wires LHLO to LHL2 from one another, or electrically connects or disconnects the wires LVLO to LVL4 to or from the wires LHLO to LHL2 in accordance with a value of a control signal (hereinafter the control signal wih be referred to as control signal ConfigL) supphed from the circuit control section 4, etc.
  • a control signal hereinafter the control signal wih be referred to as control signal ConfigL
  • the matrix switch BLSW which connects or disconnects wires LVLm (m being an integer from 0 to 4) to or from wires LHLn (n being an integer from 0 to 2), is comprised of 3969 switches Q which connect or disconnect wires LVLm-j (j being an integer from 1 to 63) to or from wires LHLn-k (k being an integer from 1 to 63).
  • Each switch Q is comprised of a switching element, such as field effect transistor (FET), for example, as shown in FIG 7B.
  • FET field effect transistor
  • a FET Ql connects or disconnects two signal lines LVLm-jA and LVLm-jB constituting the wire LVLm-j to or from each other.
  • a FET Q2 connects or disconnects two signal lines LHLn- kA and LHLn-kB constituting wires LHLn-k to or from each other.
  • a FET Q3 connects or disconnects the signal line LVLm-j A and the signal line LHLn-kA to or from each other.
  • a FET Q4 connects or disconnects the signal line LVLm-j A and the signal line LHLn-kB to or from each other.
  • a FET Q5 connects or disconnects the signal line LVLm-jB and the signal line LHLn-kA to or from each other.
  • a FET Q6 connects or disconnects the signal line LVLm-jB and the signal line LHLn-kB to or from each other.
  • a control signal ConfigL should be apphed to, for example, the gate of each of the FETs constituting the switches Q.
  • the wires LVLO to LVL4 are connected to the input logic circuits BIBC, the logic circuits BFBC, the logic circuits BQBC and the output logic circuits BOBC.
  • the wires LHLO to LHL2 are connected to the matrix switch BLSW.
  • the wires LHLO to LHL2 are not directly connected to the input logic circuits BIBC, the logic circuits BFBC, and the logic circuits BQBC (though the wires LHLO to LHL2 may be connected to those circuits via the matrix switch BLSW).
  • the wiring in the programmable logic circuit 1 changes based on the control signal ConfigL supphed to the matrix switch BLSW from the circuit control section 4 or so.
  • the input logic circuits BIBC, the logic circuits BFBC, and the logic circuits BQBC are connected to one another via the wires LVLO to LVL4 and the wires LHLO to LHL2 under the control of the circuit control section 4 or so.
  • the programmable logic circuit 1 as a whole becomes a logic circuit which has a capability of executing predetermined processes that are determined by the contents of modules to be discussed later.
  • Each of the module memory section 2 and the module address memory section 3 is comprised of a memory, such as a RAM (Random Access Memory).
  • Each of the module memory section 2 and the module address memory section 3 reads out data (to be discussed) stored therein in response to an access made by the circuit control section 4.
  • the module memory section 2 and the module address memory section 3 sends the read data to the circuit control section 4.
  • the module memory section 2 stores data (hereinafter called "module") which defines the logic configuration of the programmable logic circuit 1 as exemplified in FIG 1.
  • a single module indicates the whole of or a part of the logic configuration that one programmable logic circuit 1 can express at a time.
  • a module may indicate a the logic configurations of the input logic circuits BIBC, the logic circuits BFBC, the logic circuits BQBC and the output logic circuits BOBC as shown in FIG 2.
  • a module may be for reconfiguration of a part of the logic circuit BFBC or a part of the logic circuit BQBC, without changing the logic configurations of the other logic circuits, as per the apparatus as disclosed in, for example, Unexamined Japanese Patent Application KOKAI Publication No. 2003- 198362 or Unexamined Japanese Patent Application KOKAI Publication No. 2003-029969.
  • a 10-bit address is assigned to each of memory positions indicating memory areas in the module memory section 2.
  • the module memory section 2 specifies a module by specifying the address of the module, i.e., the address of the top memory position (or a given part in the module, such as the end) at which the module is stored. As shown in FIG 8, every 16 bits of the memory area of the module address memory section 3 constitutes one page. A page address (page position) is assigned to that page. The individual pages of the module address memory section 3 are ordered from a higher page to a lower page. The 16 bits that constitutes each page are likewise ordered from a higher significant bit to a lower one.
  • Each page in the module address memory section 3 whose data structure is exemplified in FIG 8 stores the address of each module stored in the module memory section 2 or a value indicating a jump distance (offset value) in case of performing branching, and six bits of a control bit.
  • the address of a module or an offset value occupies the lower ten bits of each page.
  • the control bit occupies the upper six bits.
  • the control bit consists of two bits indicating, for example, whether or not to allow the circuit control section 4 to perform a branch process (hereinafter called "branch control bit") and four bits indicating a branch condition in case of performing a branch process (hereinafter called "branch condition definition control bit").
  • branch control bit takes a predetermined value (e.g., a binary value of
  • the branch control bit instructs the circuit control section 4 to jump by the offset value stored in the page with the page address of the page as a start point. That is, in that case, the circuit control section 4 reads data stored on a page having the page address that is equivalent to the sum of the page address of the start page and the offset value stored on that page (i.e., data stored on the page to be jumped).
  • the branch control bit When the branch control bit takes a value other than the predetermined value (e.g., a binary value of "00" or "01 "), on the other hand, the branch control bit instructs the circuit control section 4 to read a module specified by the address included in the same page as the branch control bit, from the module memory section 2. The branch control bit also instructs the circuit control section 4 to reconfigure the programmable logic circuit 1 as indicated by the read module. Further, the branch control bit instructs the circuit control section 4 to read data stored on a next page to that page (specifically, a page with a page address which is the page address of the page incremented by "1 ").
  • the branch control bit instructs the circuit control section 4 to read data stored on a next page to that page (specifically, a page with a page address which is the page address of the page incremented by "1 ").
  • the branch condition definition control bit When the branch condition definition control bit takes a binary value of "0000”, for example, the branch condition definition control bit indicates “signal Cond(0) having a value of "0"” as a condition for executing a jump (conditional jump). When the branch condition definition control bit takes a binary value of "0001 ", for example, the branch condition definition control bit indicates “signal Cond(l) having a value of "0”” as a condition for executing a conditional jump. When the branch condition definition control bit takes a binary value of "0010”, for example, the branch condition definition control bit indicates "signal Cond(2) having a value of "0”” as a condition for executing a conditional jump.
  • the branch condition definition control bit When the branch condition definition control bit takes a binary value of "0011”, for example, the branch condition definition control bit indicates “signal Cond(3) having a value of "0" " as a condition for executing a conditional jump. When the branch condition definition control bit takes a binary value of "0100”, for example, the branch condition definition control bit indicates “signal Cond(4) having a value of "0”” as a condition for executing a conditional jump. When the branch condition definition control bit takes a binary value of "1000”, for example, the branch condition definition control bit indicates "signal Cond(0) having a value of "1”” as a condition for executing a conditional jump.
  • the branch condition definition control bit When the branch condition definition control bit takes a binary value of "1001 ", for example, the branch condition definition control bit indicates "signal Cond(l) having a value of "1”” as a condition for executing a conditional jump.
  • the branch condition definition control bit takes a binary value of "1010”, for example, the branch condition definition control bit indicates “signal Cond(2) having a value of "1”” as a condition for executing a conditional jump.
  • the branch condition definition control bit takes a binary value of "1011”, for example, the branch condition definition control bit indicates "signal Cond(3) having a value of " 1 " " as a condition for executing a conditional jump.
  • the branch condition definition control bit When the branch condition definition control bit takes a binary value of "1100", for example, the branch condition definition control bit indicates "signal Cond(4) having a value of "1"” as a condition for executing a conditional jump.
  • the branch condition definition control bit takes a binary value of "0111” or "1111”, for example, the branch condition definition control bit indicates a condition such that "a jump is made (a jump is made unconditionahy) as long as the branch control bit included on the same page as the branch condition definition control bit has the aforementioned predete ⁇ nined value".
  • the signals Cond(0) to Cond(4) are signals of a total of five bits to be supphed to the circuit control section 4 from the logic circuit BFBC which is executing a process of monitoring whether or not a condition is fulfilled, the logic circuit BQBC which is executing a process of holding the result of another process, or the output logic circuit BOBC which is executing a process of outputting the monitoring result.
  • the signals Cond(0) to Cond(4) are supphed from the logic circuit BFBC, the logic circuit BQBC or the output logic circuit BOBC is described in a module beforehand.
  • the circuit control section 4 is constituted by a controller including a processor, such as a CPU (Central Processing Unit), and a non-volatile memory, such as ROM (Read Only Memory) where a program to be executed by the processor is stored.
  • the controller constituting the circuit control section 4 may be comprised of an exclusive electronic circuit.
  • the circuit control section 4 executes, for example, a process as illustrated in FIG 9,
  • the process shown in FIG 9 is carried out as the processor loads the program stored in, for example, the non- volatile memory and runs the program.
  • the circuit control section 4 reads data stored on a page having the topmost page address in the module address memory section 3 (i.e., the control bit and the address of a module or the offset value) first (step SI in FIG. 9).
  • the circuit control section 4 discriminates whether a page from which the latest data is read from the module address memory section 3 at step S5, step S7 or step S9 to be discussed later is the last page or not, i.e., whether or not the page is a page given the lowest page address (step S2).
  • the circuit control section 4 terminates the process.
  • the circuit control section 4 discriminates which process, (a) reading of a module or (b) branching (conditional jump or unconditional jump), the control bit included in the latest data read from the module address memory section 3 indicates (step S3).
  • the circuit control section 4 When deciding that the control bit indicates the process (a), the circuit control section 4 reads a module, specified by an address included in the latest data read from the module address memory section 3, from the module memory section 2. Then, the circuit control section 4 reconfigures the programmable logic circuit 1 in such a way as to take the logic configuration indicated by the module (step S4). At step S4, specifically, the circuit control section 4 generates, for example, the aforementioned control signals ConfigL ConfigFi, ConfigFf, ConfigFo, ConfigQi, ConfigQo, ConfigO and ConfigL and sends the control signals to the programmable logic circuit 1 in order to reconfigure the programmable logic circuit 1.
  • the circuit control section 4 When the process at step S4 is finished, the circuit control section 4 reads data stored on a next page to the page from which the latest data has been read, from the module address memory section 3 (step S5). Then, the circuit control section 4 returns the process to step S2.
  • the circuit control section 4 discriminates which process, (c) unconditional jump or (d) conditional jump, the branch condition definition control bit included in the control bit indicates (step S6).
  • the circuit control section 4 discriminates whether the value of the branch condition definition control bit is "0111 " or " 1111 ". When the value of the branch condition definition control bit takes either value, the circuit control section 4 decides that an unconditional jump is instructed.
  • the circuit control section 4 decides that a conditional jump is instructed.
  • the circuit control section 4 jumps by the offset value included in the same page as the control bit (i.e., reads data stored at the page to be jumped) (step S7). Then, the circuit control section 4 returns the process to step S2.
  • the circuit control section 4 acquires, for example, the signals Cond(0) to Cond(4) supplied from the programmable logic circuit 1 (step S8).
  • the circuit control section 4 discriminates whether the branch condition indicated by the branch condition definition control bit is fulfilled or not, based on the values indicated by the acquired signals Cond(0) to Cond(4) (step S9).
  • the circuit control section 4 reads data stored on a next page to the page from which the latest data has been read, from the module address memory section 3 (step S10). Then, the circuit control section 4 returns the process to step S2.
  • the circuit control section 4 returns the process to step S7.
  • the programmable logic circuit 1 performs arithmetic operations according to its own logic configuration of the time when a signal supphed to the input logic circuit BIBC from outside, by using that signal or the old operation result held in the logic circuit BQBC. Then, the programmable logic circuit 1 holds a signal indicating the operation result in the logic circuit BQBC or outputs the signal from the output logic circuit BOBC. Through the operation, the programmable logic circuit control apparatus can execute logic configuration of the programmable logic circuit 1 in a predetermined order one after another. In addition, the programmable logic circuit control apparatus smoothly executes logic configuration in comphcated procedures involving conditional branching and unconditional branching.
  • the structure of the programmable logic circuit control apparatus is not limited to the one described above.
  • a single memory device may execute the functions of the module memory section 2 and the module address memory section 3.
  • Data which is stored in the module address memory section 3 should not necessarily take the above-described data structure.
  • the number of bits constituting one page is arbitrary.
  • the number of bits of the address of a module, the page address, the offset value, the branch control bit or the branch condition definition control bit, and the positions in each page in the module address memory section 3 are also arbitrary.
  • the conditions for the circuit control section 4 to make a jump are not limited to those discussed above.
  • the condition of executing a jump should not necessarily be associated with the values of the signals Cond(0) to Cond(4).
  • the condition may be associated with arbitrary information that is acquirable by the circuit control section 4.
  • the signal Cond may represent a value obtained as a result of performing a predetermined process, such as a logic operation, on the value of a signal which is generated a single node or at each of plural nodes of the programmable logic circuit 1 when at one timing or plural timings.
  • the programmable logic circuit 1 should have a logic circuit which executes the logic operation or so.
  • the circuit control section 4 may execute not only a jump in the aforementioned mode (i.e., a relative jump), but also an absolute jump.
  • the branch control bit stored in the module address memory section 3 should express three kinds of instructions, for example, a relative jump, an absolute jump and no jump.
  • the circuit control section 4 should interpret that the address of a page to be jumped is stored on the page that includes the branch control bit, instead of an offset value.
  • the page address of the page to be jumped is stored on the page that includes the branch control bit, instead of an offset value.
  • the programmable logic circuit control apparatus may further have a memory having a memory area which serves as last-in-first-out (LIFO) stack. Then, the programmable logic circuit control apparatus may use the stack to manage page addresses of pages in the module address memory section 3 in the stack, and achieve call and return functions.
  • the call and return functions can be accomphshed by, for example, the following scheme.
  • the control bit is so designed as to be able to include data instructing a calling process or data instructing a return process.
  • a page to be jumped in a branch process stores the address of a module which is repeatedly used.
  • the control bit of a page to be jumped includes data which instructs returning.
  • the circuit control section 4 stores the page address of a next page to the page which is currently executed. Then, the circuit control section 4 loads data stored at a page to be jumped and reconfigures the programmable logic circuit 1. Next, the circuit control section 4 reads out a page address stored in the stack (the address of a next page to the page which has been executed before jumping), and jumps to a page indicated by the page address.
  • a module may define the logic configuration of the programmable logic circuit 1 in such a way as to cause the logic circuit BFBC to monitor the end of the processing by the programmable logic circuit 1, the logic circuit BQBC to hold the monitoring result, and the output logic circuit BOBC to supply data indicating the end of the process to the circuit control section 4.
  • the module may define the logic configuration in such a way as to allow the programmable logic circuit 1 to further function as a counter to count the number of clocks of the clock signal and a logic circuit which discriminates whether the number of clocks counted by the counter has reached a predetermined number or not and supphes data indicating the end of the process to the circuit control section 4 when deciding that the number of clocks has reached the predetermined number.
  • the circuit control section 4, the module address memory section 3 and/or the module memory section 2 may be constructed by the programmable logic circuit 1.
  • the programmable logic circuit control apparatus further includes a non-volatile memory device (e.g., ROM or so) which stores a module defining the logic configuration for allowing the programmable logic circuit 1 to function as, for example, the circuit control section 4, the module address memory section 3 and/or the module memory section 2.
  • the programmable logic circuit 1 should have a control circuit or so which reads a module stored in the non- volatile memory device at a timing immediately after activation of the programmable logic circuit control apparatus and changes the logic configuration of the programmable logic circuit 1 as defined by the module.
  • the module address memory section 3 and the circuit control section 4 are loaded from a medium (CD-ROM, MO or the like) where the programs are stored and installed in a computer connected to the programmable logic circuit 1, the computer functions as the programmable logic circuit control apparatus that executes the above-described processes.
  • a method of providing a computer with the programs is not limited.
  • programs may be uploaded to a BBS (Bulletin Board System) of a communication circuit, and distributed to the computer via the communication circuit.
  • each program may be transmitted in a modulated wave which is a carrier wave modulated by a signal representing the program, and a unit which receives the modulated wave demodulates the modulated wave to restore the program.
  • the computer activates the program and executes the program in the same way as executing other application programs under the control of an OS (Operating System).
  • OS Operating System
  • a recording medium may store a program excluding that part.
  • a program for executing individual functions or steps that a computer performs should be stored in the recording medium according to the invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Quality & Reliability (AREA)
  • Automation & Control Theory (AREA)
  • Logic Circuits (AREA)
  • Stored Programmes (AREA)
  • Executing Machine-Instructions (AREA)
  • Programmable Controllers (AREA)

Abstract

L'invention concerne un appareil et un procédé de commande de circuit logique programmable et un programme associé facilitant une exécution sans à-coups de plusieurs procédés dans des procédures compliquées. Une section de mémoire d'adresse de module (3) stocke des données indiquant l'adresse d'un module à lire par une section de commande de circuit (4) ou un état destiné à un procédé de ramification et une distance de saut pour chaque page. La section de commande de circuit (4) lit des données stockées sur la page supérieure dans la section de mémoire d'adresse de module (3). En fonction des données, la section de commande de circuit (4) lit un module, reconfigure un circuit logique programmable (1) et lit des données de la page suivante ou saute. Chaque fois qu'une nouvelle page est lue, la section de commande de circuit (4) exécute des procédés en fonction des données stockées sur cette page, reconfigurant ainsi de manière séquentielle le circuit logique programmable (1).
EP04808169A 2003-12-26 2004-12-27 Appareil et procede de commande de circuit logique programmable et programme associe Withdrawn EP1697829A4 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003433210A JP3838367B2 (ja) 2003-12-26 2003-12-26 プログラマブル論理回路制御装置、プログラマブル論理回路制御方法及びプログラム
PCT/JP2004/019819 WO2005064456A1 (fr) 2003-12-26 2004-12-27 Appareil et procede de commande de circuit logique programmable et programme associe

Publications (2)

Publication Number Publication Date
EP1697829A1 true EP1697829A1 (fr) 2006-09-06
EP1697829A4 EP1697829A4 (fr) 2007-05-02

Family

ID=34736508

Family Applications (1)

Application Number Title Priority Date Filing Date
EP04808169A Withdrawn EP1697829A4 (fr) 2003-12-26 2004-12-27 Appareil et procede de commande de circuit logique programmable et programme associe

Country Status (6)

Country Link
EP (1) EP1697829A4 (fr)
JP (1) JP3838367B2 (fr)
KR (1) KR20070007270A (fr)
CN (1) CN1973259A (fr)
TW (1) TWI290282B (fr)
WO (1) WO2005064456A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7579864B2 (en) * 2005-11-25 2009-08-25 Panasonic Corporation Logic block control system and logic block control method
JP4997821B2 (ja) * 2006-05-10 2012-08-08 富士ゼロックス株式会社 データ処理装置及びそのプログラム
CN100444133C (zh) * 2006-06-13 2008-12-17 深圳市研祥智能科技股份有限公司 计算机访问扩充内存的方法
CN100456232C (zh) * 2007-03-19 2009-01-28 中国人民解放军国防科学技术大学 针对流处理的存储访问与调度装置
JP5277615B2 (ja) * 2007-11-22 2013-08-28 富士ゼロックス株式会社 データ処理装置及びデータ処理プログラム

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6023564A (en) * 1996-07-19 2000-02-08 Xilinx, Inc. Data processing system using a flash reconfigurable logic device as a dynamic execution unit for a sequence of instructions

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3611714B2 (ja) * 1998-04-08 2005-01-19 株式会社ルネサステクノロジ プロセッサ
JP3587095B2 (ja) * 1999-08-25 2004-11-10 富士ゼロックス株式会社 情報処理装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6023564A (en) * 1996-07-19 2000-02-08 Xilinx, Inc. Data processing system using a flash reconfigurable logic device as a dynamic execution unit for a sequence of instructions

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2005064456A1 *

Also Published As

Publication number Publication date
JP3838367B2 (ja) 2006-10-25
WO2005064456A1 (fr) 2005-07-14
CN1973259A (zh) 2007-05-30
TW200601029A (en) 2006-01-01
TWI290282B (en) 2007-11-21
KR20070007270A (ko) 2007-01-15
EP1697829A4 (fr) 2007-05-02
JP2005190343A (ja) 2005-07-14

Similar Documents

Publication Publication Date Title
US6434735B1 (en) Method for programming an FPGA and implementing an FPGA interconnect
US5640106A (en) Method and structure for loading data into several IC devices
US5892961A (en) Field programmable gate array having programming instructions in the configuration bitstream
US7725698B2 (en) Operation apparatus having sequencer controlling states of plurality of operation units and operation apparatus control method therefor
US6105105A (en) Data processing system using configuration select logic, an instruction store, and sequencing logic during instruction execution
JPH03171922A (ja) プログラマブル論理装置用入力回路及びプログラマブル論理装置で使用するための論理回路並びにプログラマブル論理装置
WO2002021694A2 (fr) Architecture type reseau prediffuse programmable a superposition de tuiles possible
US3978456A (en) Byte-by-byte type processor circuit
US6766505B1 (en) Parallel programming of programmable logic using register chains
CN110780921A (zh) 数据处理方法和装置、存储介质及电子装置
US5911039A (en) Integrated circuit device comprising a plurality of functional modules each performing predetermined function
US4326266A (en) Monitoring system for a modular digital data processor
US7093045B2 (en) Method and apparatus for bus arbitration capable of effectively altering a priority order
WO2005064456A1 (fr) Appareil et procede de commande de circuit logique programmable et programme associe
US20070296457A1 (en) Programmable Logic Circuit Control Apparatus, Programmable Logic Circuit Control Method and Program
EP0238125A2 (fr) Commande séquentielle programmable
US7509479B2 (en) Reconfigurable global cellular automaton with RAM blocks coupled to input and output feedback crossbar switches receiving clock counter value from sequence control unit
JP4468452B2 (ja) グローバルセルオートマトンを組み込むためのリコンフィギュアラブルなアーキテクチャをもつコンピュータ装置
JP2006302132A (ja) 信号処理装置及び再構成可能論理回路装置及び再構成可能順序回路
US6621295B1 (en) Reconfigurable priority encoding
US6147509A (en) Semiconductor logical device capable of circuit switching without being influenced by transitional effects
JP2004200311A (ja) 論理検証装置
JPH07154241A (ja) プログラマブル集積回路を用いた電子回路
US20020114200A1 (en) System for rapid configuration of a programmable logic device
Moraes et al. Development of a tool-set for remote and partial reconfiguration of FPGAs

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20060626

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): BE DE FR GB

RIN1 Information on inventor provided before grant (corrected)

Inventor name: KIKUCHI, SYUICHI,TOKYO ELECTRON DEVICE LIMITED

Inventor name: MURAKAMI, KAZUAKI

DAX Request for extension of the european patent (deleted)
RBV Designated contracting states (corrected)

Designated state(s): BE DE FR GB

A4 Supplementary search report drawn up and despatched

Effective date: 20070403

RIC1 Information provided on ipc code assigned before grant

Ipc: G06F 15/78 20060101AFI20070328BHEP

Ipc: G06F 9/32 20060101ALI20070328BHEP

17Q First examination report despatched

Effective date: 20070629

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20090304