EP1686727A1 - Datenverteilungssystem - Google Patents

Datenverteilungssystem Download PDF

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Publication number
EP1686727A1
EP1686727A1 EP04732203A EP04732203A EP1686727A1 EP 1686727 A1 EP1686727 A1 EP 1686727A1 EP 04732203 A EP04732203 A EP 04732203A EP 04732203 A EP04732203 A EP 04732203A EP 1686727 A1 EP1686727 A1 EP 1686727A1
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Prior art keywords
data
input
unit
output
data fragment
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EP04732203A
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English (en)
French (fr)
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EP1686727B1 (de
EP1686727A4 (de
Inventor
Satoshi c/o Mitsubishi Denki Kabushiki K. UDOU
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40013—Details regarding a bus controller
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40208—Bus networks characterized by the use of a particular bus standard
    • H04L2012/40221—Profibus

Definitions

  • the present invention relates to a data distribution system used in a field of control.
  • a network in which the number of inputs and outputs of the input/output unit is 8 or more is referred to as the field network, and a network in which the number of inputs and outputs of the input/output u nit is less than 8 is referred to as the sensor/actuator network.
  • the controller controls the input/output information of several tens to several thousands inputs/outputs via the field network or the sensor/actuator network. That is, the controller monitors the input state of an input unit and controls the output state of an output unit. Therefore, as shown in Fig. 1, recent networks have been made hierarchical such that the inputs of from several hundreds to several thousands are divided into small groups of inputs of several tens, and data transmission within each group is performed via the sensor/actuator network.
  • Fig. 1 is a conceptual diagram when the field network and the sensor/actuator network are hierarchical.
  • a transfer apparatus 121 m connected to the field network 111 is arranged in the group m.
  • a plurality of input/output units 122 ... are connected to the transfer apparatus 121 via a sensor/actuator network 112 having a length of from several to several hundreds of meters. That is, the transfer apparatus 121 transmits to the controller 110, input state data received from the input/output units 122 ... belonging to its own group, and also distributes control data received from the controller 110 to the input/output units 122 ... of its own group.
  • Fig. 2 is a diagram for explaining data distribution to the input/output units performed in one group shown in Fig. 1.
  • Fig. 2 depicts a case that the controller 110 transmits onto the field network 111, a transmission frame 123m addressed to group m, for controlling the output state of the input/output unit 122mn in the group m, and the transfer apparatus 121 m in the group m creates a transmission frame 123mn addressed to the input/output unit 122mn from the transmission frame 123m received from the field network 111, to transmit the data to the sensor/actuator network 112.
  • the transmission frame 123m is a bit string including a header field 71, a data field 72, and a check field 73.
  • the transmission frame 123mn is a bit string including a header field 75, a data field 76, and a check field 77.
  • the configuration of such a transmission frame is generally used in a serial communication, and the similar configuration is used in the Non-patent Literatures 1 to 6.
  • the correspondence between the bit arrangement in the data field and the input/output ports of the input/output units is determined fixedly such that the least significant bit (LSB) represents the state of the 0-th input/output port.
  • LSB least significant bit
  • the unit in the data field in the transmission frame specified in the Non-patent Literatures 1, 2, and 5 is 1 byte.
  • the unit in the data field in the transmission frame specified in the Non-patent Literature 4 is 4 or 2 bytes.
  • the unit in the data field in the transmission frame specified in the Non-patent Literature 3 is 0.5 byte (4 bits are fixed).
  • the unit in the data field in the transmission frame specified in the Non-patent Literature 6 is 0.5 byte, 1 byte, or 2 bytes.
  • the data field 72 in the transmission frame 123m includes 2xN bits (N is a multiple of 4), the first bit on the header field 71 side is the least significant bit (LSB), and the last bit on the check field 73 side is the most significant bit (MSB).
  • LSB least significant bit
  • MSB most significant bit
  • Fig. 2 it is shown that the input/output unit 122mn has two output ports mnP0 and mnP1, and hence, 2 bit data addressed to the respective input/output units 122mn is stored in the data field 72.
  • the first and the second bits are data addressed to an input/output unit 122m1
  • the third bit and the fourth bit are data addressed to an input/output unit 122m2.
  • the data field 76 includes 8 bits, the first bit b0 on the header field 75 side is the least significant bit (LSB), and the eighth bit b7 on the check field 77 side is the most significant bit (MSB).
  • LSB least significant bit
  • MSB most significant bit
  • the transfer apparatus 121 m receives the transmission frame 123m, and fetches the (2 ⁇ (m-1)+1)th bit to the (2 ⁇ m)th bit in the data field 72 of the transmission frame 123m, in order to create the transmission frame 123mn, and stores these data in bits b0 to b1 in the data field 76 of the transmission frame 123mn, and stores "0" in bits b2 to b7. That is, in the depicted example, "00000001" is stored in the data field 76.
  • Fig. 3 illustrates a process in which the transfer apparatus 121 m uses an 8-bit microcomputer to create the transmission frame 123mn to be distributed to an input/output unit 122m8 having a station number n, from the transmission frame 123m.
  • Fig. 4 is a diagram for explaining the processing content related to part "a" shown in Fig. 3.
  • the transfer apparatus 121 m defines constants and variables, and after initializing the variables, obtains the value in the data field 72 in the transmission frame 123m according to a function get_field_network_data().
  • the transfer apparatus 121m then shifts the variable d123mn rightward (in a direction toward the LSB) by 6 bits, which is the number of bits obtained by multiplying 2 by 3, which is a surplus obtained by dividing "8-1" by 4, so that data addressed to the input/output unit 122m8 is stored in order of from the LSB of the variable d123mn.
  • AND operation of the variable d123mn and 0x03 (hexadecimal) is performed in order to set 0 into the bits storing no data.
  • generation of data d123mn is complete, and the data d123mn is transmitted according to a function send_sensor_actuator_network().
  • Fig. 4 the processing in part "a” shown in Fig. 3 is shown in column (A), a processing operation actually performed by a microcomputer is shown in column (B), and the required number of clocks is shown in column (C).
  • FIG. 5 depicts an example in which an output port has the same address
  • Fig. 6 depicts an example in which the output port has a different address
  • Fig. 7 depicts details of the processing content relating to part "b" shown in Fig. 6.
  • the input/output unit 122m8 defines a constant in a constant defining section, declares variables in a variable defining section, and then obtains the value in the data field 76 in the transmission frame 123mn according to a function get_sensor_actuator_network_data() into a variable d123mn. Based on the value of the low-order 2 bits in the variable d123mn, when the value is 1, the output state of the output port mnPk is turned ON, and when the value is 0, the output state of the output port mnPk is turned OFF.
  • Fig. 7 the processing in part "b" shown in Fig. 6 is shown in column (A), a processing operation actually performed by a microcomputer is shown in column (B), and the required number of clocks is shown in column (C). As shown in column (C), as for the number of clocks required when the microcomputer executes a command, if one clock is required for one command, a total of 12 clocks are required for the processing for the 2 lines in part "b" shown in Fig. 6.
  • Fig. 8 is a diagram for explaining the configuration of a conventional hierarchical data distribution system and contents of the process procedure of the transfer apparatus.
  • the transfer apparatus 211 is connected to the controller 110 via the field network 111, and to the input/output units 250q via the sensor/actuator network 112.
  • the configuration and the contents of the process procedure of the input/output units 250q shown in Fig. 8 are shown in Figs. 9 to 11.
  • the transfer apparatus 211 includes a receiver 221, a dividing unit 222, a reception buffer 223, a specifying unit 224, an operation unit 225, and a transmitter 226.
  • the receiver 221 Upon receiving a transmission frame transmitted by the controller 110 via the field network 111, the receiver 221 extracts a bit string 113 including a data field, and provides the bit string to the dividing unit 222.
  • the bit string 113 includes 16 bits.
  • the positions of the LSB and the MSB in the bit string 113 are displayed in the opposite direction to those shown in Fig. 2.
  • the eleventh to the sixteenth bits, of which the sixteenth bit is the most significant bit, are not used.
  • the dividing unit 222 divides the bit string 113 received from the receiver 221 into data having a 1-byte length, and provides the data to the reception buffer 223 to store the data.
  • the bit string 113 since the bit string 113 includes 16 bits, the bit string 113 is divided into two, and hence, the reception buffer 223 stores a low-order data fragment 231 a and a high-order data fragment 231 b.
  • the operation unit 225 generates a data fragment 132q to be sent to the input/output unit 250q, from a data fragment 131 q extracted by the specifying unit 224.
  • the operation unit 225 includes an AND circuit 225a to which the data fragment 131 A is input, a shift register 225b to which the data fragment 131B is input, an AND circuit 225c to which the processing result by the shift register 225b is input, a shift register 225d to which the data fragment 131Ca is input, a shift register 225e to which the data fragment 131 Cb is input, an OR circuit 225f to which the processing results by the shift registers 225d and 225e are input, and an AND circuit 225g to which the processing result by the OR circuit 225f is input.
  • the transmitter 226 stores the data fragment 132q generated by the operation unit 225 in a bit string 114q including a data field in the transmission frame, and transmits the bit string 114q to the sensor/actuator network 112.
  • the receiver 251 q Upon reception of the transmission frame transmitted by the transfer apparatus 211 via the sensor/actuator network 112, the receiver 251 q extracts the bit string 114q including the data field therefrom, so that the bit string 114q is stored in the data fragment storage unit 252q.
  • the comparator 253qr sets an output state 254qr to OFF, and when the (r+1)th bit is "1", sets the output state 254qr to ON.
  • the controller 110 sets a data field storing a bit string 113 ("1111111101010101" in the depicted example) including the data 141A ("01" in the depicted example) of two bits addressed to an input/output unit 250A, the data 141B ("0101" in the depicted example) of four bits addressed to an input/output unit 250B, and the data 141 C ("1101” in the depicted example) of four bits addressed to an input/output unit 250C, in a transmission frame, and transmits the bit string 113 to the transfer apparatus 211 via the field network 111.
  • the receiver 221 extracts the bit string 113 including the data field.
  • the extracted bit string 113 is divided by the dividing unit 222 into the low-order data fragment 231 a including the low-order bytes "01010101" and the high-order data fragment 231 b including the high-order bytes "11111111", and both data fragments are stored in the reception buffer 223.
  • the low-order data fragment 231 a stored in the reception buffer 223 includes the data 141 A ("01 ”) to be transferred to the input/output unit 250A, the data 141B ("0101") to be transferred to the input/output unit 250B, and half of the data 141 C (low-order 2 bits "01 ”) to be transferred to the input/output unit 250C, and the high-order data fragment 231 b includes the remaining half of the data 141 C (high-order 2 bits "11") to be transferred to the input/output unit 250C.
  • the specifying unit 224 creates the data fragment 131A by adding a station number A to the low-order data fragment 231 a in which the data 141A to be transferred to the input/output unit 250A is stored, and sends the data fragment 131A to the operation unit 225. Further, the specifying unit 224 creates the data fragment 131 B by adding a station number B to the low-order data fragment 231 a in which the data 141 B to be transferred to the input/output unit 250B is stored, and sends the data fragment 131 B to the operation unit 225.
  • the specifying unit 224 creates the data fragments 131 Ca and 131Cb by adding a station number C to the low-order data fragment 231 a and the high-order data fragment 231 b, and sends the data fragments to the operation unit 225.
  • the operation unit 225 When all the data 141q addressed to the input/output unit 250q is included in one data fragment 131 q, the operation unit 225 performs shift operation with respect to the data fragment 131q so that the data 141 q is stored in order from the LSB of the data fragment 132q, and performs AND operation with respect to the data fragment 131q so that bits other than the data 141q are set to "0", to create the data fragment 132q to be sent to the transmitter 226.
  • the data 141q is divided into two data fragments 131 qa and 131 qb
  • the data 141 q is extracted from the data fragments 131 qa and 131 qb, to generate the data fragment 132q by performing the shift operation and OR operation so that the data 141 q is stored in order of from the LSB of the data fragment 132q, to send the data fragment 132q to the transmitter 226, after setting bits other than the data 141q to "0".
  • the operation unit 225 can determine from the station number A that the low-order 2 bits need only to be extracted from the data fragment 131 A.
  • AND operation of the data fragment 131A ("01010101") and a constant "00000011” is performed by the AND circuit 225a, and the obtained data "0000001” is sent to the transmitter 226 as a data fragment 132A.
  • the transmitter 226 creates a transmission frame having a data field in which the data fragment 132A includes a bit string 114A, and transmits the transmission frame to the input/output unit 250A.
  • a data fragment storage unit 252A stores the bit string 114A ("0000001 ") extracted from the data field in the transmission frame received by a receiver 251A.
  • a comparator 253A0 performs AND operation of the data "00000001” stored in the data fragment storage unit 252A and a constant "00000001", and since the operation result is not "0", sets an output 254A0 to ON.
  • a comparator 253A1 performs AND operation of the data "00000001” stored in the data fragment storage unit 252A and a constant "00000010", and since the operation result is "0", sets an output 254A1 to OFF.
  • the operation unit 225 the data 141 B ("0101 ") addressed to the input/output unit 250B is included in the data fragment 131B ("01010101") output by the specifying unit 224. Therefore, the operation unit 225 can determine from the station number B that the third to the sixth bits in the data fragment 131 B need only to be extracted. In order to justify the bit position to the right end, the operation unit 225 provides the data fragment 131 B to the shift register 225b, to shift the data bit rightward by 2 bits, to generate a data fragment 131B0 ("00010101").
  • a data fragment storage unit 252B stores the bit string 114B ("00000101") extracted from the data field in the transmission frame received by a receiver 251 B.
  • a comparator 253B0 performs AND operation of the data "00000101" stored in the data fragment storage unit 252B and the constant "00000001", and since the operation result is not "0", sets an output 254B0 to ON.
  • a comparator 253B1 performs AND operation of the data "00000101" stored in the data fragment storage unit 252B and the constant "00000010", and since the operation result is "0", sets an output 254B1 to OFF.
  • a comparator 253B2 performs AND operation of the data "00000101” stored in the data piece storage unit 252B and a constant "00000100", and since the operation result is not "0", sets an output 254B2 to ON.
  • a comparator 253B3 performs AND operation of the data "00000101” stored in the data piece storage unit 252B and a constant "00001000”, and since the operation result is "0", sets an output 254B3 to OFF.
  • the data 141 C (“1101") addressed to the input/output unit 250C is divided into two, and included in the data fragment 131Ca ("01010101") and the data fragment 131Cb ("11111111") output by the specifying unit 224. Therefore, the operation unit 225 can determine from the station number C that the high-order 2 bits need only to be extracted from the data fragment 131 Ca and the low-order 2 bits need only to be extracted from the data fragment 131Cb. In order to justify the bit position to the right end, the operation unit 225 provides the data fragment 131Ca to the shift register 225d, to shift the data bit rightward by 6 bits, to generate a data fragment 131C0 ("00000001 ").
  • the operation unit 225 provides the data fragment 131 Cb to the shift register 225e, to shift the data bit leftward by 2 bits, to generate a data fragment 131 C 1 ("11111100").
  • OR operation of the data fragment 131C0 and the data fragment 131C1 is performed by an OR circuit 225f, to generate a data fragment 131 C2 ("11111101 ").
  • a data fragment storage unit 252C stores the bit string 114C ("00001101 ") extracted from the data field in the transmission frame received by a receiver 251 C.
  • a comparator 253C0 performs AND operation of the data "00001101” stored in the data fragment storage unit 252C and the constant "00000001", and since the operation result is not "0", sets an output 254C0 to ON.
  • a comparator 253C1 performs AND operation of the data "00001101" stored in the data fragment storage unit 252C and the constant "00000010", and since the operation result is "0", sets an output 254C1 to OFF.
  • a comparator 253C2 performs AND operation of the data "00001101” stored in the data fragment storage unit 252C and the constant "00000100", and since the operation result is not "0", sets an output 254C2 to ON.
  • a comparator 253C3 performs AND operation of the data "00001101” stored in the data fragment storage unit 252C and the constant "00001000", and since the operation result is not "0", sets an output 254C3 to ON.
  • Fig. 12 illustrates a case in which the transfer apparatus 211 uses an 8-bit microcomputer to execute the processing.
  • Fig. 13 is a diagram for explaining the details of the process related to part "c" shown in Fig. 12.
  • the process in part "c" shown in Fig. 12 is shown in column (A)
  • a processing operation actually performed by the microcomputer is shown in column (B)
  • the required number of clocks is shown in column (C).
  • column (C) as for the number of clocks required when the microcomputer executes a command, if one clock is required for one command, a total of 99 clocks are required for the process in part "c" shown in Fig. 12.
  • the time required until the transfer apparatus finishes processing for distributing data to all input/output units through the sensor/actuator network is calculated by multiplying the processing time for one unit by the number of input/output units. Therefore, there is a problem in that a delay in the processing due to the shift process causes performance deterioration in the distribution processing.
  • the present invention has been achieved in order to solve the above problems. It is an object of the present invention to provide a data distribution system, which does not require the bit shift operation by the transfer apparatus.
  • a data distribution system includes a controller that transmits a bit string including a plurality of individual data, a transfer apparatus that receives the bit string from the controller, extracts the individual data from the bit string received, and transfers the individual data to corresponding input/output units, and a plurality of input/output units, each of which controls an input/output state based on the individual data received from the transfer apparatus.
  • the transfer apparatus includes a dividing unit that divides the bit string received from the controller, into data fragments having a size easy to handle, a specifying unit that specifies, from the data fragments, a data fragment that includes the individual data addressed to a target input/output unit, an operating unit that processes the specified data fragment without performing a bit shift operation, generates one target data fragment for each of the input/output units, and transmits the target data fragment to the respective input/output units, and a transmitting unit that transmits template information to the respective input/output units, where the template information indicates an area where the individual data relative to the corresponding input/output unit is stored in the target data fragment.
  • the input/output unit includes a storing unit that stores the template information received from the transfer apparatus, and an extracting unit that extracts the individual data used by the input/output unit from the target data fragment received from the transfer apparatus, based on the template information stored.
  • the bit shift operation by the transfer apparatus is not required, a data fragment to be transmitted to the input/output unit can be generated in short time. Therefore, it is possible to improve the processing efficiency of the process in which one controller distributes individual data to a plurality of input/output units.
  • Fig. 14 is a diagram for explaining a configuration of a data distribution system and a process executed by a transfer apparatus according to one embodiment of the present invention.
  • the transfer apparatus 20 is connected to the controller 10 via a field network 12, and to the input/output units 50q via a sensor/actuator network 17.
  • the configuration and the processing content of the input/output units 50q are shown in Figs. 15 to 17.
  • the transfer apparatus 20 includes a receiver 21, a dividing unit 22, a reception buffer 23, a specifying unit 24, an operation unit 25, and a transmitter 26.
  • the receiver 21 Upon receiving a transmission frame transmitted by the controller 10 via the field network 12, the receiver 21 extracts a bit string 13 including a data field, and provides the bit string to the dividing unit 22.
  • the bit string 13 includes 16 bits.
  • the position of the LSB in the bit string 13 is at the right end, and the position of the MSB is at the left end.
  • the first and the second bits on the lowest order side indicate data 41A
  • the third to the sixth bits indicate data 41 B
  • the seventh to the tenth bits indicate data 41 C
  • the eleventh to the sixteenth bits, of which the sixteenth bit is the most significant bit, are not used.
  • Data 41 q is data to be transmitted to the input/output unit 50q.
  • the dividing unit 22 divides the bit string 13 received from the receiver 21 into data having a 1-byte length, and provides the data to the reception buffer 23 to store the data.
  • the bit string 13 since the bit string 13 includes 16 bits, the bit string 13 is divided into two, and hence, the reception buffer 23 stores a low-order data fragment 23a and a high-order data fragment 23b.
  • four one-byte data fragments 31A, 31B, 31C1, and 31C0 are extracted.
  • the data fragment 31A includes the data 41A.
  • the data fragment 31 B includes the data 41 B.
  • the data fragment 31C1 includes high-order two bits of the data 41 C
  • the data fragment 31C0 includes low-order two bits of the data 41 C.
  • the operation unit 25 generates a data fragment 32q to be sent to the input/output unit 50q, from the data fragments 31A, 31B, 31C1, and 31C0 extracted by the specifying unit 24.
  • the operation unit 25 includes an AND circuit 25b to which the data fragment 31 C1 is input, an AND circuit 25a to which the data fragment 31C0 is input, and an OR circuit 25c to which the processing result by the AND circuits 25b and 25a is input.
  • the transmitter 26 stores the data fragment 32q generated by the operation unit 25 in a bit string 14q including a data field in the transmission frame, and transmits the bit string 14q to the sensor/actuator network 17.
  • template information including a bit pattern indicating an area in which the data 41q applied to the input/output unit 50q is stored in the bit string 14q to be transmitted by the transfer apparatus 20, is input to the input/output unit 50q in one-to-one correspondence with the comparators 53qr.
  • the transfer apparatus 20 transfers the template information before starting data distribution process to the input/output unit 50q, such as at the time of startup of the system.
  • the receiver 51q Upon reception of the transmission frame transmitted by the transfer apparatus 20 onto the sensor/actuator network 17, the receiver 51q extracts the bit string 14q including the data field therefrom, so that the bit string 14q is stored in the data fragment storage unit 52q.
  • the receiver 51 q also allows a template storage unit 52qr to store the template information received separately from the transfer apparatus 20.
  • the comparator 53qr performs AND operation of the data fragment 32q stored by the data fragment storage unit 52q and the template information stored by the template storage unit 52qr, and when the result is "0", sets an output state 54qr to OFF, and when the result is not "0", sets the output state 54qr to ON.
  • the transfer apparatus 20 receives an instruction from the controller 10 before starting the data distribution processing to the input/output unit 50q, and transmits the template information to the respective input/output units 50q.
  • the template information is stored in the template storage unit 55qr.
  • template information "00000001” is stored in a template storage unit 55A0
  • template information "00000010” is stored in a template storage unit 55A1.
  • template information "00000100” is stored in a template storage unit 55B0
  • template information "00001000” is stored in a template storage unit 55B1
  • template information "00010000” is stored in a template storage unit 55B2
  • template information "00100000” is stored in a template storage unit 55B3.
  • template information "01000000” is stored in a template storage unit 55C0
  • template information "10000000” is stored in a template storage unit 55C1
  • template information "00000001” is stored in a template storage unit 55C2
  • template information "00000010” is stored in a template storage unit 55C3.
  • the controller 10 sets in a transmission frame, a data field that stores the bit string 13 ("1111111101010101" in the depicted example) including the data 41A ("01" in the depicted example) of two bits addressed to the input/output unit 50A, the data 41B ("0101" in the depicted example) of four bits addressed to the input/output unit 50B, and the data 41 C ("1101” in the depicted example) of four bits addressed to the input/output unit 50C, and transmits the bit string 13 to the transfer apparatus 20 via the field network 12.
  • the receiver 21 extracts the bit string 13 including the data field.
  • the extracted bit string 13 is divided by the dividing unit 22 into the low-order data fragment 23a including the low-order bytes "01010101" and the high-order data fragment 23b including the high-order bytes "11111111", and the both data fragments are stored in the reception buffer 23.
  • the low-order data fragment 23a stored in the reception buffer 23 includes the data 41 A ("01 ") to be transferred to the input/output unit 50A, the data 41 B ("0101") to be transferred to the input/output unit 50B, and half of the data 41 C (low-order 2 bits "01 ”) to be transferred to the input/output unit 50C, and the high-order data fragment 23b includes the remaining half of the data 41 C (high-order 2 bits "11") to be transferred to the input/output unit 50C.
  • the specifying unit 24 creates the data fragment 31A by adding a station number A to the low-order data fragment 23a in which the data 41A to be transferred to the input/output unit 50A is stored, and sends the data fragment 31 A to the operation unit 25. Further, the specifying unit 24 creates the data fragment 31 B by adding a station number B to the low-order data fragment 23a in which the data 41 B to be transferred to the input/output unit 50B is stored, and sends the data fragment 31 B to the operation unit 25.
  • the specifying unit 24 creates the data fragments 31C1 and 31C0 by adding a station number C to the low-order data fragment 23a and the high-order data fragment 23b, and sends the data fragments to the operation unit 25.
  • the operation unit 25 designates the data fragment 31 q as the data fragment 32q to be sent to the transmitter 26, without performing any special processing.
  • the operation unit 25 sets bits other than the data 41 q in the data fragments 31q0 and 31q1 to "0", and generates the data fragment 32q to be sent to the transmitter 26, by performing OR operation of the two data fragments.
  • the operation unit 25 sends the data fragment 31A as data fragment 32A directly to the transmitter 26.
  • the transmitter 26 creates a transmission frame having a data field in which the data fragment 32A includes a bit string 14A, to transmit the transmission frame to the input/output unit 50A via the sensor/actuator network 17.
  • data fragment storage unit 52A stores the bit string 14A ("01010101 ") extracted from the data field in the transmission frame received by receiver 51A.
  • a comparator 53A0 performs AND operation of the data "01010101” stored in the data fragment storage unit 52A and the template information "00000001” stored in the template storage unit 55A0, and since the operation result is not "0", sets an output 54A0 to ON.
  • a comparator 53A1 performs AND operation of the data "01010101" stored in the data fragment storage unit 52A and the template information "00000010” stored in the template storage unit 55A1, and since the operation result is "0", sets an output 54A1 to OFF.
  • the operation unit 25 sends the data fragment 31 B as data fragment 32B directly to the transmitter 26.
  • the transmitter 26 creates a transmission frame having a data field in which the data fragment 32B includes a bit string 14B, to transmit the transmission frame to the input/output unit 50B via the sensor/actuator network 17.
  • data fragment storage unit 52B stores the bit string 14B ("01010101") extracted from the data field in the transmission frame received by receiver 51 B.
  • a comparator 53B0 performs AND operation of the data "01010101” stored in the data fragment storage unit 52B and the template information "00000100” stored in the template storage unit 55B0, and since.the operation result is not "0", sets an output 54B0 to ON.
  • a comparator 53B1 performs AND operation of the data "01010101" stored in the data fragment storage unit 52B and the template information "00001000" stored in the template storage unit 55B1, and since the operation result is "0", sets an output 54B1 to OFF.
  • a comparator 53B2 performs AND operation of the data "01010101” stored in the data fragment storage unit 52B and the template information "00010000” stored in the template storage unit 55B2, and since the operation result is not “0", sets an output 54B2 to ON.
  • a comparator 53B3 performs AND operation of the data "01010101” stored in the data fragment storage unit 52B and the template information "00100000” stored in the template storage unit 55B3, and since the operation result is "0", sets an output 54B3 to OFF.
  • the data 41 C addressed to the input/output unit 50C is divided into two, and included in the data fragment 31C0 ("01010101") and the data fragment 31C1 ("11111111") output by the specifying unit 24. Therefore, the operation unit 25 can determine from the station number C that the high-order 2 bits need only to be extracted from the data fragment 31C0 and the low-order 2 bits need only to be extracted from the data fragment 31C1. In order to set bits other than the high-order 2 bits to "0" in the data fragment 31C0, the AND circuit 25a of the operation unit 25 performs AND operation of the data fragment 31C0 ("01010101") and a constant "11000000", to generate a data fragment 31 C2 ("01000000").
  • AND operation of the data fragment 31C1 (“11111111”) and a constant "00000011” is performed by the AND circuit 25b in order to set bits other than the low-order 2 bits to "0", to generate a data fragment 3103 ("00000011").
  • the OR circuit 25c performs OR operation of the data fragment 31C2 and the data fragment 31C3 to generate a data fragment 32C ("01000011"), and provides the data fragment 32C to the transmitter 26.
  • the transmitter 26 creates a transmission frame having a data field in which the data fragment 32C includes a bit string 14C, and transmits the transmission frame to the input/output unit 50C via the sensor/actuator network 17.
  • data fragment storage unit 52C stores the bit string 14C ("01000011") extracted from the data field in the transmission frame received by receiver 51 C.
  • a comparator 53C0 performs AND operation of the data "01000011” stored in the data fragment storage unit 52C and the template information "01000000” stored in the template storage unit 55C0, and since the operation result is not "0", sets an output 54C0 to ON.
  • a comparator 53C1 performs AND operation of the data "01000011” stored in the data fragment storage unit 52C and the template information "10000000” stored in the template storage unit 55C1, and since the operation result is "0", sets an output 54C1 to OFF.
  • a comparator 53C2 performs AND operation of the data "01000011” stored in the data fragment storage unit 52C and the template information "00000001” stored in the template storage unit 55C2, and since the operation result is not "0", sets an output 54C2 to ON.
  • a comparator 53C3 performs AND operation of the data "01000011” stored in the data fragment storage unit 52B and the template information "00000010” stored in the template storage unit 55C3, and since the operation result is not "0", sets an output 54C3 to ON.
  • Fig. 18 illustrates a case in which the transfer apparatus 20 uses an 8-bit microcomputer to execute the process.
  • Fig. 19 is a diagram for explaining details of the process related to part "d" shown in Fig. 18.
  • a constant defining unit defines constants
  • a variable defining unit declares variables
  • a variable initializing unit defines an initial value of the variables.
  • the value of the bit string 13 is stored in a variable d13 according to a function get_field_network_data(), to execute the process in order of data transmission to the input/output units 50q in a subsequent for-loop.
  • Fig. 19 the processing in part "d" shown in Fig. 18 is shown in column (A), a processing operation actually performed by a microcomputer is shown in column (B), and the required number of clocks is shown in column (C).
  • column (C) the number of clocks required for the microcomputer to perform the process for one line is expressed as 1, the number of clocks for lines that are not executed as a result of condition decision is expressed as 0, and the number of clocks for lines to be executed is expressed as 1, and the total of number of clocks 30 is shown in the lowermost line.
  • Figs. 20 and 21 are diagrams for specifically explaining the process in which the input/output unit 50q determines the output state from data stored in the data fragment storage unit 52q.
  • Fig. 20 illustrates a case that the input/output unit 50q uses an 8-bit microcomputer to execute the processing.
  • Fig. 21 illustrates details of the process related to part "e" shown in Fig. 20.
  • a constant defining unit defines constants
  • a variable defining unit declares variables
  • Fig. 21 the processing in part "e” shown in Fig. 20 is shown in column (A), a processing operation actually performed by a microcomputer is shown in column (B), and the required number of clocks is shown in column (C).
  • column (C) it is seen that 12 clocks are required for executing the process in part "e” shown in Fig. 20.
  • the number of clocks required for executing the processing is 12 clocks.
  • the present invention is suitable as a data distribution system in which one controller distributes individual data to a plurality of input/output units, and the processing efficiency of which is improved.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)
  • Programmable Controllers (AREA)
  • Information Transfer Between Computers (AREA)
  • Selective Calling Equipment (AREA)
EP20040732203 2003-11-21 2004-05-11 Datenverteilungssystem Expired - Fee Related EP1686727B1 (de)

Applications Claiming Priority (2)

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JP2003392869A JP4137773B2 (ja) 2003-11-21 2003-11-21 データ分配システム
PCT/JP2004/006612 WO2005050922A1 (ja) 2003-11-21 2004-05-11 データ分配システム

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EP1686727A1 true EP1686727A1 (de) 2006-08-02
EP1686727A4 EP1686727A4 (de) 2012-01-18
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EP (1) EP1686727B1 (de)
JP (1) JP4137773B2 (de)
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PL398136A1 (pl) * 2012-02-17 2013-08-19 Binartech Spólka Jawna Aksamit Sposób wykrywania kontekstu urzadzenia przenosnego i urzadzenie przenosne z modulem wykrywania kontekstu
US9857228B2 (en) * 2014-03-25 2018-01-02 Rosemount Inc. Process conduit anomaly detection using thermal imaging

Citations (2)

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EP1043867A2 (de) * 1999-02-18 2000-10-11 Weidmüller ConneXt GmbH & Co. Verfahren und Vorrichtung zur seriellen Daten-übertragung
US20010044866A1 (en) * 1996-03-07 2001-11-22 Smyers Scott D. Isochronous data pipe for managing and manipulating a high-speed stream of isochronous data flowing between an application and a bus structure

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EP0382246A3 (de) * 1989-02-09 1991-09-11 Nec Corporation Bitadressierungsanordnung
JPH11122250A (ja) * 1997-10-13 1999-04-30 Omron Corp 通信制御システム
US6223285B1 (en) * 1997-10-24 2001-04-24 Sony Corporation Of Japan Method and system for transferring information using an encryption mode indicator
US7006631B1 (en) * 2000-07-12 2006-02-28 Packet Video Corporation Method and system for embedding binary data sequences into video bitstreams
JP3804770B2 (ja) * 2001-11-12 2006-08-02 オムロン株式会社 制御システム及びスレーブ
KR20060021180A (ko) * 2004-09-02 2006-03-07 파츠닉(주) 고용량 탄탈콘덴서의 특성 안정화방법

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US20010044866A1 (en) * 1996-03-07 2001-11-22 Smyers Scott D. Isochronous data pipe for managing and manipulating a high-speed stream of isochronous data flowing between an application and a bus structure
EP1043867A2 (de) * 1999-02-18 2000-10-11 Weidmüller ConneXt GmbH & Co. Verfahren und Vorrichtung zur seriellen Daten-übertragung

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US20060080480A1 (en) 2006-04-13
US7320040B2 (en) 2008-01-15
WO2005050922A1 (ja) 2005-06-02
JP2005157583A (ja) 2005-06-16
KR100730859B1 (ko) 2007-06-20
KR20050117545A (ko) 2005-12-14
JP4137773B2 (ja) 2008-08-20
EP1686727B1 (de) 2013-03-27
EP1686727A4 (de) 2012-01-18

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