Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Definitions

• Computer systems, or other data processing systems include integrated circuit devices having a subset of memory in which data is changed more often than data in other subsets of the memory.
• the subset of memory that is more frequently changed tends to fail to due the effects of the great number of change cycles it undergoes .
• a wide variety of endurance enhancement techniques are known to attempt to decrease the potential for failure of the memory cells. For example, redundant memory cells are provided so that if one memory cell fails, another memory cell will take over and provide the required data. Also wear leveling techniques are known in the art . Most endurance enhancement techniques operate at the block level rather than the bit level .
• Counters are often used to keep track of the total number of erase/program cycles of a block and then to switch to a redundant block before the first block fails or to occasionally switch blocks to even out the wear.
• a total-write-counter field indicates a total number of write-erase cycles of the block and an incremental -write- counter field indicates an incremental number of write- erase cycles since a wear-leveling operation for the block. The total and incremental numbers must exceed thresholds for wear leveling for the block change to occur.
• a plurality of non-volatile memory cells, associated with a plurality of flag cells, is used in the present invention to increase the endurance of a non-volatile memory cell. For instance two, three or more nonvolatile memory cells associated with two, three or more flag cells, may be used.
• a pair of non-volatile memory cells with associated first and second flag cells disposed on the integrated circuit.
• the pair of nonvolatile memory cells function as a single larger memory cell with twice the endurance of a regular single nonvolatile memory cell.
• the managing data of the first flag cell and the managing data of the second flag cell form a data set.
• a current data set is utilized to determine to which memory cell of the pair of memory cells to write a new value and from which of the pair of memory cells to read a currently stored value.
• the current data set is changed to a different data set whenever a new value is written to a designated memory cell to indicate an alternate memory cell to be written to next and an alternate memory cell to be read from next .
• the current data set has logic values which are input into logic control means, such as logic control circuitry, forming a part of the integrated circuit to determine to which memory cell to write new data and from which memory cell to read data.
• logic control means also determine from the current data set the logic values to which the data set should be changed after each successive write/erase cycle.
• the memory cells and flag cells are programmed with program circuitry known in the art and according to the determination of the logic control means. With each successive write operation to an alternate non-volatile memory cell, logic control means change the current data set to a different data set which becomes the current data set so that an alternate memory cell is read to and written from.
• sense amplifier 16 is associated with flag cell Fl_ sense amplifier 18 is associated with flag cell F2
• sense amplifier 20 is associated with non-volatile memory cell VI
• sense amplifier 22 is associated with non-volatile memory cell V2 to sense the output of each Fl, F2 , VI and V2 cell.
• a sense signal may be toggled to initialize the system after new value 24 has been written to the designated non-volatile memory cell and after the current data set has been changed to update each flag cell and nonvolatile memory cell .
• flag cell Fl_ flag cell F2 non-volatile memory cell VI and nonvolatile memory cell V2 are erased to 0 as shown in step 30.
• the managing data of flag cell Fl and flag cell F2 form a data set which is used, as shown in block 32, to determine from which memory cell to read a currently stored value and to which memory cell to write a new value.
• the logic control circuitry from the first data set, determines to read a currently stored value from nonvolatile memory cell VI, as shown in block 34.
• the logic control circuitry 12 determines from the second data set to read the currently stored value from non-volatile memory cell V2 , as shown in block 38.
• the logic control circuitry 12 determines to write the new value to non-volatile memory cell VI as shown in block 40.
• the logic control circuitry 12 utilizes the second data set to determine a third data set that is different from the second data set to which to change the second data set.
• the logic control circuitry 12 When a new value 24 is written to one of the pair of nonvolatile memory cells, the logic control circuitry 12, utilizes the third data set to determine to write the new value to non-volatile memory cell V2 , as shown in block 44.
• the logic control circuitry utilizes the third data set to determine a fourth data set that is different from the third data set which to change the third data set to.
• flag cell F2 neither the erase or write function is asserted leaving the value as 1.
• flag cell F2 could be erased and have a 1 written to it .
• the logic control circuitry determines from the fourth data set to read the currently stored value from non-volatile memory cell V2 , as shown in block 46.
• the logic control circuitry from the fourth data set determines to write a new value to non-volatile memory cell VI, as shown in block 48.
• program circuitry 14 before each non-volatile memory cell has the new value written to it, as described above or in other embodiments, program circuitry 14 performs an erase operation to the non-volatile memory cell to which the new value will be written.
• the erase function is coupled to the write function and occurs before the write function.
• managing data is alternately written to the flag cells and alternately erased from the flag cells as the data sets are changed.
• the wear of the flag cells is substantially level and at substantially the same rate as the associated pair of memory cells.
• the group of different data sets is equally divided in number between those current data sets indicating to write a new value to non-volatile memory cell VI and between those current data sets indicating to write a new value to non-volatile memory cell V2.
• a multiplexer 54 which utilizes one of four flag cell data sets to determine from which non-volatile memory cell, VI or V2 , to read a currently stored value.
• a DATA DUT value is read from only one of the memory cells VI and V2 each time a different data set is input into the multiplexer 54.
• Fig. 3B an embodiment of the logic control circuitry of the present invention is shown. This embodiment utilizes the four different data sets shown in Fig. 3A and Fig. 3C.
• a WRITE signal is another input of AND gate 72. If the output of the AND gate 72 is 1, the Fl input/output block 56 will write to one, as shown by the WRITE_TO_ONE function. If a 1 is not asserted, it will not write to
• Inverter 81 is shown in Fig. 3E inverting signal F2 to F2B.
• Data signals FIB and F2B are inputs of AND gate 86, the output of which is an input of AND gate 88.
• a WRITE signal is also an input of the AND gate 88. If the output of the AND gate 88 is 1 the Fl input/output block 60 will write to one, as shown by the WRITE_TO_ONE function. If a 1 is not asserted, it will not write to 1.
• a 1 is the output of AND gate 70, and XOR gates 64, 74 and 78, thus a 1 is an input of the AND gates 66, 72, 76 and 80. Therefore, the erase and write functions may be asserted in flag cell Fl and memory cell VI, though not simultaneously in each cell .
• the WRITE signal of flag cell Fl is a 1 which asserts the WRITE_TO_ONE function. Therefore, a 1 is written to the flag cell Fl, as shown by the "Next" column of Fig. 3C. The 1 becomes DOUT for input/output block 56 for flag cell Fl (Fig. 3B) .
• the input/output block 58 for VI may be erased before writing, although since it is already at 0, this is not necessary.
• the WRITE signal is a 1 which asserts the WRITE_TO_ONE function.
• DATA_IN or the new value, is written to the memory cell VI, as shown by the "Erase/Write to" column of Fig. 3C.
• the new value becomes DOUT for VI.
• the outputs of the XNOR gates 82, 90 and 94 and AND gate 86 are 0. Therefore, the output of the AND gates 84, 88, 92, and 96 must also be 0.
• XOR gates 64, 74 and 78 and AND gate 70 are 0.
• the outputs for the AND gates 66, 72, 76 and 80 must also be 0. Accordingly, neither the erase or write functions are asserted and the values remain the same.
• the currently stored value of non-volatile memory cell VI is "Read from" cell VI, as shown in Fig. 3C.
• the output DOUT of input/output block 56 for flag cell Fl remains 1 (Fig. 3B) .
• a 1 is the output of XNOR gates 82, 90 and 94, thus a 1 is an input for the AND gates 84, 92 and 96.

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