EP1667101A1 - Automatische Anpassung der Versorgungsspannung eines Elektrolumineszenz-Schirmes entsprechend der gewünschten Helligkeit - Google Patents

Automatische Anpassung der Versorgungsspannung eines Elektrolumineszenz-Schirmes entsprechend der gewünschten Helligkeit Download PDF

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Publication number
EP1667101A1
EP1667101A1 EP05111703A EP05111703A EP1667101A1 EP 1667101 A1 EP1667101 A1 EP 1667101A1 EP 05111703 A EP05111703 A EP 05111703A EP 05111703 A EP05111703 A EP 05111703A EP 1667101 A1 EP1667101 A1 EP 1667101A1
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Prior art keywords
voltage
transistor
column
drain
pol
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Withdrawn
Application number
EP05111703A
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English (en)
French (fr)
Inventor
Danika Chaussy
Céline MAS
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STMicroelectronics SA
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STMicroelectronics SA
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Publication of EP1667101A1 publication Critical patent/EP1667101A1/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3216—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using a passive matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3283—Details of drivers for data electrodes in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to electroluminescent display matrix screens composed of a set of light-emitting diodes. These are for example screens composed of organic diodes ("OLED" of the English Organic Light Emitting Display) or polymers ("PLED” of the English Polymer Light Emitting Display).
  • OLED organic diodes
  • PLED polymers
  • the present invention relates more particularly to the regulation of the supply voltage of the control circuits of the light-emitting diodes of such screens.
  • FIG. 1 represents a matrix screen comprising n columns C 1 to C n and k lines L 1 to L k making it possible to address n * k light-emitting diodes d whose anodes are connected to a column and the cathodes to a line.
  • Line control circuits CL 1 to CL k are used to bias lines L 1 to L k respectively . Only one line is activated at a time, and is biased to ground. Unactivated lines are biased to a line V voltage.
  • Column control circuits CC 1 to CC n are used to bias the columns C 1 to C n, respectively .
  • the columns addressing the light-emitting diodes that we wish to activate are biased by a current at a voltage V COL greater than the threshold voltage of the light emitting diodes of the screen.
  • the columns that we do not want to activate are grounded.
  • a light emitting diode connected to the activated line and to a V COL polarized column is then conducting and emits light.
  • the voltage V line is sufficiently high so that the light-emitting diodes connected to the non-activated lines and the columns at the voltage V COL are not conductive and do not emit light.
  • FIG. 2 represents a conventional example of a DC column control circuit and of a line control circuit CL respectively addressing a column C and a line L connected to a light emitting diode d of the screen.
  • the line control circuit CL comprises a power inverter 1 controlled by a line control signal ⁇ L.
  • the power inverter 1 comprises an NMOS transistor 2 making it possible to discharge the line L when ⁇ L is at the high level and a PMOS transistor 3 making it possible to charge the line L at the bias voltage V line when ⁇ L is at the low level.
  • the column control circuit CC comprises a current mirror made in the present example with two transistors 4, 5 of the PMOS type.
  • the transistor 4 constitutes the reference branch of the mirror and the transistor 5 constitutes the duplication branch.
  • the sources of transistors 4 and 5 are connected to a bias voltage V POL of the order of 15 V for OLED screens.
  • the gates of transistors 4 and 5 are connected to each other.
  • the drain and the gate of transistor 4 are connected to each other.
  • the transistor 4 is therefore diode-mounted, the source-gate voltage (Vsg 4 ) being equal to the source-drain voltage (Vsd 4 ).
  • the drain of the transistor 4 is connected to the source of a power transistor 6 of the PMOS type.
  • the drain and the gate of transistor 6 are connected to each other.
  • the drain of transistor 6 is connected to a terminal of a current source 7 whose other terminal is connected to ground GND.
  • the flow crossing the transistor 4 is fixed by the current source 7 which provides a current I LUM called "luminance
  • the drain of the transistor 5 is connected to the source of a power transistor 8 of the PMOS type.
  • the drain of the transistor 8 is connected to the column C.
  • a switch 9, controlled by a control signal ⁇ C is adapted to connect the gate of the transistor 8 to the bias voltage V POL , for example when the control signal ⁇ C is at the high level, and at the gate of transistor 6 when the control signal ⁇ C is at the low level.
  • the transistor 8 is on and the column C is charged until reaching the voltage V COL .
  • the line control signals ⁇ L and column ⁇ C are respectively high and low, the light emitting diode d is on and the current flowing through the diode is equal to the luminance current I LUM .
  • the grounding circuit of the column C when the control signal ⁇ C is high is not shown.
  • the bias voltage V POL is equal to the sum of the drain-source voltage Vds 2 of the transistor 2, the voltage V d at the terminals of the light-emitting diode d, the source-drain voltage Vsd 8 of the transistor 8 and the source-drain voltage Vsd 5 of the transistor 5.
  • the transistor 5 When the copying of the current I LUM is correct, the transistor 5 is in saturation mode and the voltage Vsd 5 is at least equal to the source-drain voltage Vsd 4 of the transistor 4.
  • a correct copy of the current in the duplication branch imposes so that the bias voltage V POL is at least equal to the sum mentioned above when the current flowing through it is equal to the luminance current I LUM . If the bias voltage V POL is too low, the current flowing through the light-emitting diode d is lower than the current I LUM and the luminance of the diodes is insufficient.
  • the luminance current I LUM supplied by the current source 7 can generally vary depending on the desired luminance for the screen.
  • the source-drain voltage Vsd 4 of the diode-connected transistor 4 increases and the voltage V d of the light-emitting diode d also increases. It follows that the bias voltage V POL must be large enough so that the transistor 5 is in saturation irrespective of the luminance current.
  • control circuits which have a fixed polarization voltage V POL and determined according to the desired maximum luminance current I LUM .
  • the disadvantage of such circuits is their high power consumption.
  • An object of the present invention is to provide a device for regulating the bias voltage of column control circuits providing a voltage of V POL polarization as low as possible regardless of the aging of the light emitting diodes of the screen.
  • Another object of the present invention is to provide a device for regulating the control circuit bias voltage of simple design.
  • the present invention provides a device for regulating the bias voltage of column control circuits of a matrix screen composed of light-emitting diodes distributed in rows and columns, the column control circuits being adapted to select columns for making the light emitting diodes of the selected columns and a selected line of the matrix screen conductive, the device comprising a first measuring circuit providing a first measurement signal representative of the highest voltage among the voltages of the selected columns ; a second measurement circuit providing a second measurement signal representative of the least voltage among the voltages of the selected columns; and an adjustment circuit receiving the first and second measurement signals and adapted to decrease the bias voltage if the first measurement signal is less than a first comparison signal and to increase the bias voltage if the second measurement signal is greater than a second comparison signal.
  • the adjustment circuit comprises a first storage circuit, adapted to store the first measurement signal for at least the duration of the display of an image on the matrix screen in the first embodiment. no new measurement of the first measurement signal; and a second storage circuit adapted to store the second measurement signal for at least the duration of displaying an image on the matrix screen in the absence of a new measurement of the second measurement signal.
  • the first measurement circuit is adapted to measure the maximum voltage among the column voltages of the matrix screen, the measurement circuit comprising a protection circuit adapted to deactivate the measurement circuit for each column associated with a non-conductive light emitting diode.
  • the column control circuits are in the form of a current mirror comprising a reference branch and a plurality of duplication branches connected to the bias voltage, each duplication branch being connected. to a column, the reference branch comprising a PMOS type field effect reference transistor whose source is connected to the bias voltage, and whose drain is connected to a reference current source supplying a current equal to one luminance current, the gate and the drain of the reference transistor being connected together.
  • each duplication branch of the current mirror comprises a PMOS type field effect duplicating transistor whose source is connected to the bias voltage and whose drain is connected to said column, the gates of the transistors of each branch. being connected together.
  • the first measurement circuit comprises, for each column, a PMOS type field effect protection transistor whose source is connected to the bias voltage and whose gate is connected to the drain. of the duplication transistor of the duplication branch associated with said column and an NMOS-type field effect measurement transistor whose drain is connected to the drain of the protective transistor and whose gate is connected to the column, the sources of the first measuring transistors being connected to a measuring point.
  • the reference branch furthermore comprises a PMOS-type field effect reference power transistor whose source is connected to the drain of the reference transistor, the gate and drain of the reference power transistor being connected to the reference current source.
  • Each duplication branch further comprises a PMOS type field effect duplication power transistor whose source is connected to the drain of the duplication transistor and whose drain is connected to the column, and whose gate is adapted to be connected to the drain of the reference power transistor to select said column, the first comparison signal being the voltage at the drain of the reference power transistor.
  • the second measurement circuit comprises, for each column, a PMOS type field effect measurement transistor whose drain is connected to a reference potential and whose gate is connected to the column, the sources of the second measurement transistors being connected to a measuring point.
  • the second comparison signal is equal to the bias voltage reduced by a determined constant voltage.
  • the present invention also provides a matrix screen comprising light-emitting diodes distributed in rows and columns and column control circuits adapted to select columns for making conductive the light-emitting diodes of the selected columns and a selected line, said matrix screen comprising furthermore a device for regulating the bias voltage of the column control circuits as described above.
  • the present invention also provides a method for regulating the bias voltage of column control circuits of a matrix screen composed of light-emitting diodes distributed in rows and columns, the column control circuits being adapted to select columns for rendering conductive electroluminescent diodes selected columns and a selected line of the screen matrix.
  • the method includes decreasing the bias voltage when the highest voltage among the selected column voltages is less than a first comparison voltage and increasing the bias voltage when the lowest voltage among the selected column voltages is greater than at a second comparison voltage.
  • the column control circuits are in the form of a current mirror comprising a reference branch and a plurality of duplication branches connected to the bias voltage, each duplication branch being connected.
  • the reference branch comprising a PMOS-type field-effect reference transistor whose source is connected to the bias voltage, the gate and the drain of the reference transistor being connected together, and a power transistor of PMOS type field effect reference whose source is connected to the drain of the reference transistor, the gate and the drain of the power transistor being connected to a reference current source providing a current equal to a predefined luminance current.
  • the first comparison signal is the voltage at the drain of the reference power transistor and the second comparison signal is the voltage at the drain of the reference transistor.
  • FIG. 3 represents an exemplary embodiment of column control circuits and the regulation device according to the present invention.
  • the column control circuits comprise a current mirror 40 composed in the present example of a reference branch b ref and n duplication branches b 1 to b n .
  • Each branch is composed of a PMOS transistor, P ref for the reference branch and P 1 to P n for the branches b 1 to b n .
  • the sources of the transistors of each of the branches are connected to the bias voltage V POL and the gates are connected to each other.
  • the drain and the gate of the transistor P ref of the reference branch b ref are connected to a source of a power PMOS transistor X ref .
  • the gate and the drain of the power transistor X ref are connected together.
  • the drain of the transistor X ref is connected to the drain of a NMOS transistor N ref.
  • the gate and the drain of the transistor N ref are connected together.
  • the source of the transistor N ref is connected to a terminal of a reference current source 42 at a point C ref .
  • the other terminal of the current source 42 is connected to GND ground.
  • V ref is noted the voltage between the point C ref GND GND, V CASC the voltage between the drain of the transistor X ref GND and ground GNIR and V MIRROR the voltage between the drain of the transistor P ref and ground GND.
  • the reference current source 42 provides a luminance current I LUM .
  • the drain of each transistor P i i being between 1 and n, is connected to the source of a PMOS power transistor X i whose drain is connected to a column C i .
  • Each power transistor, X ref and X 1 to X n allows to maintain the voltage between the source and the drain of the transistor, P ref and P 1 to P n , corresponding in the operating range of this transistor.
  • each power transistor X i i being between 1 and n, is connected to a terminal of a switch I i at two positions controlled by a signal ⁇ Ci and adapted to connect the gate of the transistor X i to the drain of the transistor X ref , when the signal ⁇ Ci is for example at the low level, or at the bias voltage V POL , when the signal ⁇ Ci is at the high level.
  • the transistor X i is on and the voltage of the column C i is stabilized at the operating voltage V COLi of the column while the current I LUM circulates in the column.
  • the control circuits furthermore comprise, for each column, a switch (not shown) adapted to connect the column C i to the ground GND.
  • the present invention consists in providing for each duplication branch b i , i being between 1 and n, a first measuring circuit m i comprising a PMOS transistor P ' i , the source of which is connected to the bias voltage V POL and whose gate is connected to the drain of the transistor P i of the corresponding duplication branch b i .
  • the drain of each transistor P ' i is connected to the source of a power PMOS transistor X' i whose gate is connected to the gate of the power transistor X i of the corresponding duplication branch b i .
  • the power transistor X ' i makes it possible to maintain the voltage between the source and the drain of the associated transistor P' i in the operating range of this transistor.
  • each power transistor X ' i is connected to the drain of a NMOS transistor N i , mounted as a follower, whose gate is connected to the column C i .
  • the sources of the transistors N 1 to N n are connected, at a point C MAX , to a terminal of a current source 44 whose other terminal is connected to ground GND.
  • V MAX is the voltage between the C MAX point and GND ground.
  • the current source 44 supplies a bias current I POL for biasing the NMOS transistors N 1 to N n .
  • a switch 46 controlled by a signal T ON , allows to connect the point C MAX to a terminal of a capacitor C HMAX whose other terminal is connected to ground GND.
  • the voltage across the capacitor C HMAX attacks the inverting input (-) of an operational amplifier A MAX mounted as a comparator.
  • the non-inverting input (+) of the amplifier A MAX is connected to the point C ref .
  • the amplifier A MAX provides a binary control signal V POL_High .
  • a second measuring circuit comprising a PMOS type transistor P " i whose gate is connected to the column C i and whose drain is connected to the ground GND.
  • the sources of the transistors P “ 1 to P" n are connected at a point C MIN to a terminal of a current source 47 supplying a current I ' POL for biasing the PMOS transistors P “ 1 to P" n .
  • V MIN is noted the voltage between point C MIN and the ground GND.
  • a switch 48 controlled by the signal T oN, connects the point C MIN to a terminal of a capacitor C HMIN whose other terminal is connected GND
  • the voltage across the capacitor C HMIN drives the non-inverting input (+) of a comparator- equipped operational amplifier A.
  • the inverting input (-) of the amplifier A MIN is connected to a terminal of a constant voltage generator 50, providing a constant voltage V COMP , the other terminal of which is connected to the terminal polarization voltage V POL .
  • Amplifier A MIN provides a binary control signal V POL_Low .
  • control signals V POL_High , V POL_Low are supplied to an adjustment module 52 which modifies the value of the bias voltage V POL as a function of the values of the control signals.
  • the invention consists in regulating the bias voltage V POL so that, for each active column C i , the voltage of the column V COLi best follows the following relation: V CCAC ⁇ V COLLAR i ⁇ V MIRROR
  • V COLMAX the highest voltage, denoted V COLMAX, is used among the voltages of the active columns C 1 to C n which is compared with the voltage V CASC to determine if the polarization voltage V POL is too high.
  • the voltage of each column C i is stabilized at a column voltage V COLi that can vary from one column to the other. Since the transistors N 1 to N n are mounted in a follower, the voltage V MAX follows the highest voltage V COLMAX among the voltages of the columns C 1 to C n . More precisely, the voltage V MAX is equal to the difference between the voltage V COLMAX and the gate-source voltage (imposed by I POL ) of the transistor N i of the column C i having the highest column voltage V COLi . Switch 46 is closed only when at least one pixel of a line is selected.
  • the voltage V MAX is applied across the capacitor C HMAX .
  • the duration of closure of the switch 46 may vary but does not exceed the duration of a phase of activation of a line of the screen to prevent the discharge of the capacitor C HMAX with the current I POL .
  • the amplifier A MAX compares the voltage V MAX with the voltage V ref . This amounts to comparing the voltage V COLMAX with the voltage V CASC considering that the gate-source voltages of the transistor N ref and the transistors N 1 to N n are equal.
  • the amplifier A MAX supplies, for example, a control signal V POL_High at level “0" when the voltage V MAX is greater than the voltage V ref and a control signal V POL_High at the level "1" when the voltage V MAX is lower. at the voltage V ref .
  • Some of the active columns may have an "open" pixel defect.
  • An "open" pixel corresponds to a break in the link between the column and the anode of the light-emitting diode of the pixel or a break in the connection between the line and the cathode of the light-emitting diode of the pixel. Since an open column C i is at high impedance, the voltage V COLi of the column rises to the bias voltage V POL . The voltage V COLMAX would then be equal to V POL , which would be incorrect.
  • the device according to the invention makes it possible not to take into account an open column for the determination of V COLMAX .
  • an "open" pixel for example the pixel of the column C 1
  • the power transistor X 1 when the power transistor X 1 is conducting, the column being open and at high impedance, the voltage at the drain of the transistor P 1 goes up to the bias voltage V POL .
  • the voltage on the gate of the transistor P ' 1 is then equal to the bias voltage V POL and the transistor P' 1 is blocked. No current therefore passes through the transistor P ' 1 .
  • the transistor N 1 is then no longer powered and can not charge the capacitor C HMAX .
  • the V COLMAX voltage thus obtained can not be used to determine if the polarization voltage V POL is too low. Indeed, if the bias voltage V POL became too low, the voltage V COLi of each column C i active would be equal to the bias voltage V POL so that the associated transistor P ' i would be blocked. The capacitor C HMAX would then be discharged by the current I POL and the voltage V MAX could decrease below the voltage V CASC thus indicating, erroneously, that the bias voltage V POL would be too high.
  • V COLMIN the lowest voltage, denoted V COLMIN , is used among the voltages of the active columns which is obtained separately from the voltage V COLMAX .
  • the voltage V COLMIN is then compared with the voltage V MIRROR to determine if the polarization voltage V POL is too low.
  • the voltage V MIN follows the most weak V COLMIN among the voltages of the active columns C 1 to C n . More precisely, the voltage V MIN is equal to the sum of the voltage V COLMIN and of the source-gate voltage of the transistor P " i of the column C i to the voltage V COLMIN. In theory, if it could be considered that the gate-source voltage of the transistor P ref was equal to the gate-source voltage of the transistor P " i of the column C i at the voltage V COLMIN , comparing the voltage V COLMIN to the voltage V MIRROR would be equivalent to comparing V MIN to V POL .
  • V MIN is compared with a voltage which is lower than the bias voltage V POL of the constant voltage V COMP , for example fixed at 300 mV.
  • the amplifier A MIN compares the voltage V MIN with the voltage V POL -V COMP and supplies a command signal V POL Low at "1" when the voltage V MIN is greater than the voltage V POL -V COMP and a signal of command V POL_Low at "0" when the voltage V MIN is lower than the voltage V POL -V COMP .
  • the capacitances of the capacitors C HMIN and C HMAX are large enough to limit leakage at these capacitors for at least the duration corresponding to the activation of all the lines of the screen. This makes it possible to provide a correct polarization voltage V POL even in the case where only one line of the screen is illuminated when displaying an image on the screen.
  • FIG. 4 represents an exemplary embodiment of a circuit corresponding to the comparator A MIN and the constant voltage source V COMP .
  • the circuit comprises an NMOS transistor 50 whose drain and gate are connected to the bias voltage V POL .
  • the source of the transistor 50 is connected to the source of a PMOS transistor 52.
  • the gate and the drain of the transistor 52 are connected to a terminal of a constant current source 54 whose other terminal is connected to ground GND.
  • the circuit comprises an adjustable resistor R, one terminal of which is connected to the bias voltage V POL and the other terminal of which is connected to the drain of an NMOS transistor 56.
  • the gate of the transistor 56 corresponds to the non-inverting input (+ ) of the amplifier A MIN of FIG. 3.
  • the source of the transistor 56 is connected to the source of a PMOS transistor 58.
  • the gate of the transistor 58 is connected to the gate of the transistor 52 and the drain of the transistor 58 is connected. GND ground.
  • the drain of the transistor 56 is connected to the gate of a PMOS transistor 60 whose source is connected to the bias voltage V POL .
  • the current I Low at the drain of the transistor 60 supplies the control signal V POL_Low after a current-voltage conversion.
  • V COL1 associated with column C 1 has the lowest operating voltage V COLMIN . It is considered that the voltage of the column C 1 must remain lower than V MIRROR , that is to say the sum of the voltage V CASC and the gate-source voltage of the transistor X ref , since beyond this value the copy is bad.
  • the voltage V MIRROR is also equal to the difference between the bias voltage V POL and the gate-source voltage of the transistor P ref .
  • the voltage V MIN applied across the capacitor C HMIN is equal to the voltage V POL -Vgs Pref + Vgs P "1 , that is to say equal to V POL if we consider that the two gate-source voltages are identical.
  • the transistor 58 is off and the current I Low is zero.
  • V MIN is greater than V POL
  • a current flows in the transistor 58 and therefore in the power transistor 60.
  • the current I Low coming from the drain of the transistor 60 can then be converted into voltage to obtain the control signal V POL_Low .
  • the gate-source voltages of the transistors P ref and P " 1 are not perfectly identical and the voltage V MIN is compared with the voltage V POL -V COMP , where the voltage V COMP is positive, to take account of the The dimensions of the transistors 50 and 56 and the value of the resistor R are adjusted so as to adjust the gain of the comparator and the voltage for which it switches over.
  • the present invention is susceptible of various variations and modifications which will be apparent to those skilled in the art.
  • the current mirror can be realized with a larger number of transistors per branch.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
EP05111703A 2004-12-06 2005-12-05 Automatische Anpassung der Versorgungsspannung eines Elektrolumineszenz-Schirmes entsprechend der gewünschten Helligkeit Withdrawn EP1667101A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0452868A FR2879008A1 (fr) 2004-12-06 2004-12-06 Adaptation automatique de la tension d'alimentation d'un ecran electroluminescent en fonction de la luminance souhaitee

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EP1667101A1 true EP1667101A1 (de) 2006-06-07

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EP05111703A Withdrawn EP1667101A1 (de) 2004-12-06 2005-12-05 Automatische Anpassung der Versorgungsspannung eines Elektrolumineszenz-Schirmes entsprechend der gewünschten Helligkeit

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US (1) US7911424B2 (de)
EP (1) EP1667101A1 (de)
FR (1) FR2879008A1 (de)

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