EP1658646A2 - Compose comportant au moins une unite de memoire en materiau organique, destine en particulier a etre utilise dans des structures cmos, dispositif a semiconducteur et procede de fabrication d'un dispositif a semiconducteur - Google Patents

Compose comportant au moins une unite de memoire en materiau organique, destine en particulier a etre utilise dans des structures cmos, dispositif a semiconducteur et procede de fabrication d'un dispositif a semiconducteur

Info

Publication number
EP1658646A2
EP1658646A2 EP04786208A EP04786208A EP1658646A2 EP 1658646 A2 EP1658646 A2 EP 1658646A2 EP 04786208 A EP04786208 A EP 04786208A EP 04786208 A EP04786208 A EP 04786208A EP 1658646 A2 EP1658646 A2 EP 1658646A2
Authority
EP
European Patent Office
Prior art keywords
electrode
group
binding
silicon
semiconductor component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04786208A
Other languages
German (de)
English (en)
Inventor
Marcus Halik
Hagen Klauk
Günter Schmid
Ute Zschieschang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1658646A2 publication Critical patent/EP1658646A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/50—Bistable switching devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0014—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/191—Deposition of organic active material characterised by provisions for the orientation or alignment of the layer to be deposited
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/40—Organosilicon compounds, e.g. TIPS pentacene
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/701—Organic molecular electronic devices

Definitions

  • the invention relates to a compound according to the preamble of claim 1, a semiconductor component according to claim 13 and a method for producing a • •
  • the memory cell of a semiconductor component could ideally be reduced to orders of magnitude in the molecular range (size depending on the type of molecule about 0.5 to 5 n).
  • a number of individual molecules e.g. 100
  • the electrode area e.g. 10 n x 10 nm
  • Molecules per memory cell 1 nm 3 per molecule, 100 nm 2 per memory cell) are considered for the production of a memory function.
  • Collier et al. describes a write-once memory cell that is based on the material class of the rotaxanes in connection with a bispyridinium unit. Scanning tunneling microscopy (STM) is increasingly being used to investigate the switching behavior of individual molecules (see Gittins et al. And Donhauser et al.). In Gittins et al. describes the switching behavior of a bispyrdinium compound on a gold nanoparticle. In Donhauser et al. the switching behavior of phenylene ethynylene oligomers is described by isolation with alkanethiolates.
  • the molecular storage media described so far have preferably been examined on gold electrodes, as a result of the great experience that exists when depositing monolayers on gold (see Y. Xia, G.M. Whitesides, Angew. Chem. 1998, 568 to 594).
  • the molecular monolayers are fixed on the gold surface using a thiol group (-SH). Since the gold / thiol system is not a covalent bond of the thiol / ttiiolate with the gold atoms, but the self-organization effect of the monolayer is mainly based on the reduction in the configurative entropy, this system is only of limited stability.
  • SAMs self-organizing monolayers
  • thiol anchor groups on gold surfaces are not stable, for example, against the action of various organic and inorganic solvents.
  • these SAMs are only partially temperature-stable with regard to diffusion. This means that the molecules migrate or desorb (since they are not covalently bound) at elevated temperatures above room temperature on the gold surface and thus change their properties (GM Whitesides et al., J. Am. Chem.
  • Electrode material for the bottom electrode in silicon CMOS processes is problematic since gold is a dangerous dopant in close contact with the semiconductor silicon. In terms of process technology, the use of gold for the bottom electrode is therefore undesirable.
  • a symmetrical molecular design with two identical anchor groups, as in Gittins et al. described.
  • a symmetrical molecule design increases the probability that the molecules do not arrange themselves as a closed monolayer (standing vertically or slightly angled on the metal), but have a high concentration of impurities, which are due to the simultaneous "binding" to the anchor groups (and thus to a parallel arrangement of the molecules to the gold substrate).
  • This interference arrangement is based on the driving force of the anchor group to orient itself towards the metal.
  • the object of the present invention is to create a connection, a semiconductor component and a method for producing the semiconductor component, with which it is possible to efficiently implement molecular storage layers on conventional substrates.
  • connection has at least one first anchor group with a reactive group for covalent binding to a first electrode, in particular a bottom electrode of a memory cell and at least one second anchor group with a reactive group for binding to a second electrode, in particular a top electrode of a memory cell.
  • the anchor groups make it possible to use organic molecular storage materials for the integration on silicon-based circuits. This enables the integration to be carried out in a simple manner on silicon substrates, using only standard CMOS materials for the bottom electrodes (silicon, aluminum, titanium, copper), while specifically avoiding silicon-CMOS-incompatible materials (gold ). Due to the specific covalent connection of the organic storage units via an anchor group to the electrode materials, the inventive ones
  • Storage cells are significantly more stable (in terms of temperature, chemicals and lifespan) compared to non-covalently bound compounds (eg compounds based on thiol).
  • the connection thus has a storage unit which is provided at its ends with anchor groups which are selected selectively for a specific electrode material.
  • the first anchor group and the second anchor group are chemically different. This enables the connection to be automatically aligned with the electrodes used.
  • At least a first anchor group comprising a halosilane and / or a Alkoxysilen- • group.
  • the second anchor group (2) advantageously has at least one
  • -SH group a -S0 2 H group and / or a -PR 3 group for binding to a second electrode (20) made of gold
  • at least one -NR 2 group and / or -SH group for binding to a second electrode (20 ) made of copper
  • at least one -NC group for binding to a second electrode (20) made of platinum
  • at least one -P0 3 H 2 group for binding to a second electrode (20) made of indium tin oxide (ITO) and / or at least one -COOH group and / or a -CONHOH group for binding to a second electrode (20) made of Al (AlO x ).
  • the storage unit has a linear molecular group, a conjugated phenylene ethynylene oligomer and / or a compound with a bispyridyl group.
  • at least one anchor group is connected to a molecular storage unit via a linker, wherein it is advantageous if at least one linker. is an n-alkane or an aryl. Special electrical effects can be achieved if the linkers are designed differently, in particular have different lengths.
  • the object is also achieved by a semiconductor component with the features of claim 13.
  • the semiconductor component has at least one self-organizing monolayer with a connection according to at least one of claims 1 to 12, the self-organizing monolayer being arranged between at least a first electrode and a second electrode. This means that CMOS silicon platforms can be used efficiently.
  • a first electrode in particular a bottom electrode, has or consists of silicon, titanium, aluminum, titanium and / or copper. It is also advantageous if at least one second electrode, in particular a top electrode, has or consists of aluminum, titanium, gold, copper, platinum, ITO, TiN x / TaN x , WN X or Al (AlO x ).
  • the object is also achieved by a method according to claim 16, in which a compound according to at least one of claims 1 to 12 is applied to a substrate by gas phase deposition or liquid phase deposition.
  • the gas phase separation takes place at a pressure of 10 "s to 400 mbar, its temperature from 80 to 300 ° C and / or under a protective gas atmosphere.
  • the organic storage molecules are preferably deposited from the gas phase, but can also be from solution.
  • the molecules are selectively covalently bound to a Si / SiO 2 surface (bottom electrode) using a suitable anchor group.
  • the consequence of this covalent connection is that the organic storage molecules are very stable in terms of temperature, chemicals and diffusion, which significantly improves subsequent processes (deposition and structuring of the top electrode) and longevity of the storage matrix.
  • the liquid phase is advantageously deposited from a slightly polar, aprotic solvent, in particular toluene, tetrahydrofuran, cyclohexane, at a concentration of 10 4 to 1%.
  • a slightly polar, aprotic solvent in particular toluene, tetrahydrofuran, cyclohexane, at a concentration of 10 4 to 1%.
  • At least one first electrode for controlling at least one memory cell is applied to the substrate, then
  • At least one second electrode is connected to at least one memory cell.
  • At least one second electrode is connected to at least one memory cell.
  • an oxide layer in particular an SiO 2 layer, is generated on the substrate by thermal oxidation, in particular in an oxidation furnace or rapid thermal processing, and / or a brief exposure to an oxygen plasma.
  • FIG. 1 shows a schematic, perspective view of a monomolecular storage layer of a semiconductor component according to the invention between a bottom and a To electrode;
  • FIG. 2a shows a schematic structure of an embodiment of the connection according to the invention
  • FIG. 2b shows a schematic representation of an embodiment of the connection according to the invention in connection with bottom and top electrodes
  • the invention relates inter alia to Connections that are particularly suitable for stable integration in silicon CMOS platforms in order to subsequently use them to generate a memory matrix with a control unit based on silicon CMOS technology.
  • a memory matrix (without control electronics) is shown schematically in FIG. 1.
  • a self-organizing monolayer 101 with a storage unit is arranged between a top electrode 20 and a bottom electrode 10.
  • the substrate on which the electrodes 10, 20 and the monolayer 101 are arranged is not shown.
  • An anchor group 1 for connecting the connection to a first electrode 10 (not shown here) (here the bottom electrode).
  • This anchor group 1 consists e.g. from a reactive silicon group (halosilane, alkoxysilene) that selectively covalently binds to a substrate 100 (e.g. silicon with a few nanometer thick native oxide layer).
  • a memory unit 3 which can be designed depending on the usable memory effect.
  • a second anchor group 2 for connection to a second electrode 20 not shown here (here top electrode). Depending on the electrode material used, this anchor group consists of corresponding reactive groups:
  • ITO Indium Tin Oxide
  • AI A10 X
  • COOH -CONHOH etc.
  • FIG. 2a shows various embodiments of the connection according to the invention.
  • FIG. 2 b schematically shows how these connections are connected to a bottom electrode 10 and a top electrode 20.
  • the bottom electrodes 10 are defined on a silicon substrate on which the silicon CMOS control electronics have already been implemented. This can be done, for example, using high-resolution photolithography or high-resolution imprint techniques.
  • the advantage is the use of silicon (its electrical conductivity can be selectively increased by doping up to 10 5 , S, / cm) as the electrode material, since silicon is already present as a substrate.
  • silicon can easily be provided with a very thin oxide layer (e.g. some Angstroem thickness), which is important for the covalent connection of the first anchor group 1. This means that the substrate on which the semiconductor components are produced also serves as electrode material, as a result of which the deposition and structuring of a process-critical metal layer is eliminated.
  • base metals such as e.g. B. Aluminum, titanium or copper can be used as the material for the bottom electrodes 10.
  • connection of the first anchor groups 1 to base metals is similar to the connection to a Si / Si0 2 surface.
  • Base metals especially aluminum and titanium, are (in contrast to gold) compatible with existing silicon CMOS forms.
  • anchor groups 1, 2 are used at the ends of the molecules in order to ensure the material selectivity during the deposition. Due to the difference there is a selective
  • the organic compounds with the storage element are separated either from a solution or from the gas phase (at reduced pressure and elevated temperature).
  • the covalent bond of the compound occurs spontaneously with the formation of an R-Si-O-Si bond.
  • This bond is very stable chemically, since it is the same chemical bond as, for example, in quartz.
  • the thermal stability of the bond will determined by the organic radical R of the storage molecule, but not by the “anchor bond” itself, so that its thermostability theoretically corresponds to that of quartz. Normally, monolayers that are anchored using this method are stable up to over 200 ° C.
  • the working voltage of the memory cell can be adjusted over the length of the linker unit.
  • the top electrode 20 can be applied to the SAM structured on the bottom electrodes 10. This can be done by flat deposition of a metal layer and its subsequent structuring (see FIGS. 3a to 3d), or by the structured deposition of metal surfaces (see FIGS. 4a to 4d).
  • the upper metal layer also binds to the organic storage layer by means of the second anchor group 2. This stabilizes the storage matrix with regard to chemical, thermal and long-term stability.
  • a memory cell constructed in this way also offers the advantage that, due to the asymmetrical structure of the memory cell (two different armature groups 1, 2), a rectifier function is achieved. Rectifying cells make reading out the stored information considerably easier.
  • the following shows how connections according to the invention can be connected to different electrode materials.
  • Storage molecules (R) are made using various bond formations
  • CMOS-compatible metal electrodes made of aluminum or titanium the binding to the native or deposited oxide layer takes place in accordance with
  • first anchor groups 1 are discussed below, the first anchor groups 1 being specified which are suitable for a specific surface type.
  • Variant a delivers good results in the production of monolayers on silicon surfaces.
  • the organic molecules which show the corresponding functionality, can be applied by vapor deposition or immersion in a suitable solution of the molecules.
  • a gas phase deposition is particularly advantageous since in the semiconductor industry the "dry" processes are increasingly displacing the wet chemical processes.
  • the gas phase separation takes place in a closed reactor with heating.
  • the reactor interior is evacuated several times after loading with the silicon substrates (wafers) and aerated with inert gas (Ar, N 2 ) in order to remove residual oxygen.
  • Ar, N 2 inert gas
  • the working pressure and working temperature are set, which essentially depend on the rest R (pressure: about 10 "s to 400 mbar; temperature: about 80 to 300 ° C).
  • the ideal process conditions depend on the volatility (Vapor pressure) of the molecules.
  • the corresponding process window is limited by the thermal stability of the molecular residues.
  • the coating time for a gas phase deposition is 30 minutes to 24 hours depending on the process conditions.
  • a solution can also be deposited from a solution.
  • Dried, slightly polar, aprotic solvents for example toluene, tetrahydrofuran, cyclohexane
  • Concentrations of the solutions in the range of about 10 ⁇ 4 to 1 are particularly suitable for the production of dense layers.
  • the deposition takes place by immersing the silicon substrate (wafer) in the prepared solution, then rinsing with the pure process solvent, optional rinsing with a volatile solvent (e.g. acetone, dichloromethane) and finally drying (oven, hotplate) under protective gas.
  • a volatile solvent e.g. acetone, dichloromethane
  • the memory cells 102 (see, for example, FIGS. 3c, 4c) must be isolated from one another on a substrate 100 in order to individualize them, ie each memory cell 102 must be activated by the bottom electrode 10 (bit line) and top electrode 20 (Word line) can be controlled individually (see for example Fig. 1 and 3d, 4d).
  • both the electrodes 10, 20 C crossed lines botto-electrode-top electrode) and the active storage layer 101 (ie the self-organizing monolayer SAM) have to be structured.
  • a first embodiment is the structuring of the memory cells by etching the memory SAM 101, the individual steps being shown in FIGS. 3a to 3d.
  • bottom electrodes 10 e.g. made of silicon, aluminum, titanium, copper
  • bottom electrodes 10 are deposited as bit lines on the square substrate 100 shown schematically in FIG. 3a.
  • a self-organizing monolayer 101 with a corresponding embodiment of the connection according to the invention is deposited as a storage SAM (FIG. 3b).
  • the first anchor group 1 is aligned with the bottom electrode 10.
  • etching mask After applying an etching mask, a subtractive structuring of the memory SAM 101 is carried out (FIG. 3c). Finally, the etching mask is removed and the top electrodes 20 (word lines) are structured (FIG. 3d). The resulting memory cells 102 can thus be controlled by bottom electrodes 10 and top electrodes 20.
  • FIGS. 4a to 4d A second, particularly advantageous embodiment for the production of semiconductor components is shown in FIGS. 4a to 4d.
  • the memory SAM 101 is not applied over the entire area here.
  • the substrate 100 is provided with defined botto electrodes 10 as bit lines (e.g. made of silicon, aluminum, titanium, copper) (FIG. 4a). Then one
  • Passivation layer 103 (approx. 2 to 7 nm thick) is applied, the passivation layer 103 having contact holes 104 (FIG. 4b). In a next process step, these contact holes 104 are filled with the SAM material using an embodiment of the connection according to the invention (FIG. 4c). Then the top electrodes 20 are arranged as word lines (FIG. 4d).
  • the SAM When structuring by means of the contact holes 104, the SAM is bound in each case in the contact holes 104 on the Silicon bottom electrode 10 underneath.
  • the passivation layer 103 is therefore not suitable for the covalent attachment (targeted attachment) of the organic storage molecules.
  • Passivation layers are e.g. organic or inorganic layers that do not form a covalent bond with the respective anchor group, with a layer thickness that corresponds approximately to the length of the organic storage molecule
  • both deposition methods gas phase deposition
  • the contact hole method (FIGS. 4a to 4d) is particularly advantageous since the storage array is mechanically stabilized at the same time.
  • the embodiment of the invention is not limited to the preferred exemplary embodiments specified above. Rather, a number of variants are conceivable which make use of the connection according to the invention, the semiconductor component according to the invention and the method according to the invention even in the case of fundamentally different types.
  • first electrode (bottom electrode) 20 second electrode (top electrode)

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un composé comportant au moins une unité de mémoire en matériau organique, lequel composé est en particulier destiné à être utilisé dans des structures CMOS. Ce composé est caractérisé par a) au moins un premier groupe d'ancrage (1) pourvu d'un groupe réactif permettant la liaison par covalence à une première électrode (10), en particulier une électrode inférieure d'une cellule de mémoire (102), et b) au moins un deuxième groupe d'ancrage (2) pourvu d'un groupe réactif permettant la liaison à une deuxième électrode (20), en particulier une électrode supérieure d'une cellule de mémoire (102). Ladite invention concerne également un dispositif à semiconducteur et un procédé de fabrication d'un dispositif à semiconducteur. On obtient ainsi un composé, un dispositif à semiconducteur et un procédé de fabrication d'un dispositif à semiconducteur, qui permettent efficacement de former des couches de mémoire moléculaires sur des substrats classiques.
EP04786208A 2003-08-29 2004-08-27 Compose comportant au moins une unite de memoire en materiau organique, destine en particulier a etre utilise dans des structures cmos, dispositif a semiconducteur et procede de fabrication d'un dispositif a semiconducteur Withdrawn EP1658646A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10340610A DE10340610B4 (de) 2003-08-29 2003-08-29 Verbindung mit mindestens einer Speichereinheit aus organischem Speichermaterial, insbesondere zur Verwendung in CMOS-Strukturen, Halbleiterbauelement und ein Verfahren zur Herstellung eines Halbleiterbauelementes
PCT/DE2004/001936 WO2005022658A2 (fr) 2003-08-29 2004-08-27 Compose comportant au moins une unite de memoire en materiau organique, destine en particulier a etre utilise dans des structures cmos, dispositif a semiconducteur et procede de fabrication d'un dispositif a semiconducteur

Publications (1)

Publication Number Publication Date
EP1658646A2 true EP1658646A2 (fr) 2006-05-24

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EP04786208A Withdrawn EP1658646A2 (fr) 2003-08-29 2004-08-27 Compose comportant au moins une unite de memoire en materiau organique, destine en particulier a etre utilise dans des structures cmos, dispositif a semiconducteur et procede de fabrication d'un dispositif a semiconducteur

Country Status (4)

Country Link
US (1) US20060211257A1 (fr)
EP (1) EP1658646A2 (fr)
DE (1) DE10340610B4 (fr)
WO (1) WO2005022658A2 (fr)

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Publication number Priority date Publication date Assignee Title
US8758935B2 (en) 2009-02-04 2014-06-24 National University Of Singapore Soluble polymer with multi-stable electric states and products comprising such polymer
JP2023081627A (ja) * 2021-12-01 2023-06-13 キオクシア株式会社 有機分子メモリ

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EP0643883B1 (fr) * 1992-06-01 2003-10-01 Yale University Dispositif electronique a echelle subnanometrique et son procede de fabrication
US5475341A (en) * 1992-06-01 1995-12-12 Yale University Sub-nanoscale electronic systems and devices
EP1542869A4 (fr) * 1999-09-20 2005-06-22 Univ Yale Dispositifs electroniques a l'echelle moleculaire
US20040248381A1 (en) * 2000-11-01 2004-12-09 Myrick James J. Nanoelectronic interconnection and addressing
DE10132640A1 (de) * 2001-07-05 2003-01-23 Infineon Technologies Ag Molekularelektronik-Anordnung und Verfahren zum Herstellen einer Molekularelektronik-Anordnung
DE10324388A1 (de) * 2003-05-28 2004-12-30 Infineon Technologies Ag Schaltungselement mit einer ersten Schicht aus einem elektrisch isolierenden Substratmaterial und Verfahren zur Herstellung eines Schaltungselements
DE10329247A1 (de) * 2003-06-24 2005-01-27 Infineon Technologies Ag Verbindung zur Bildung einer selbstorganisierenden Monolage, eine Schichtstruktur, ein Halbleiterbauelement und ein Verfahren zur Herstellung einer Schichtstruktur

Non-Patent Citations (1)

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Title
See references of WO2005022658A2 *

Also Published As

Publication number Publication date
WO2005022658A2 (fr) 2005-03-10
WO2005022658A3 (fr) 2005-11-03
DE10340610A1 (de) 2005-04-07
DE10340610B4 (de) 2007-06-06
US20060211257A1 (en) 2006-09-21

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