EP1616392A2 - Systeme et procede de transmission de signaux de largeur de bande ultralarge - Google Patents

Systeme et procede de transmission de signaux de largeur de bande ultralarge

Info

Publication number
EP1616392A2
EP1616392A2 EP04715618A EP04715618A EP1616392A2 EP 1616392 A2 EP1616392 A2 EP 1616392A2 EP 04715618 A EP04715618 A EP 04715618A EP 04715618 A EP04715618 A EP 04715618A EP 1616392 A2 EP1616392 A2 EP 1616392A2
Authority
EP
European Patent Office
Prior art keywords
signal
ultrawide bandwidth
frequency
band
recited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP04715618A
Other languages
German (de)
English (en)
Inventor
Matthew L. Welborn
John W. Mccorkle
Richard D. Roberts
Phuong T. Huynh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc, Motorola Inc filed Critical Freescale Semiconductor Inc
Publication of EP1616392A2 publication Critical patent/EP1616392A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/7163—Spread spectrum techniques using impulse radio
    • H04B1/71632—Signal aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/7163—Spread spectrum techniques using impulse radio
    • H04B1/71635—Transmitter aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0004—Modulated-carrier systems using wavelets

Definitions

  • the present invention relates in general to wireless communication systems, such as ultra-wide band (UWB) systems, including mobile transceivers, centralized transceivers, and related equipment. More specifically the present invention relates to the transmission of data between two wireless devices using multiple frequency bands.
  • UWB ultra-wide band
  • UWB radio can provide a fast, low power transmission scheme.
  • UWB signals generally have a continuous fractional bandwidth (i.e., the ratio of the -10 dB bandwidth to the center frequency) of at least 25%.
  • a signal can fall outside of this basic range and still be considered "UWB.”
  • the Federal Communications Commission (FCC) refers to a signal in the 3.1 to 10.6 GHz range with a center frequency of 500 MHz as UWB.
  • FCC Federal Communications Commission
  • UWB devices suffer several important limitations.
  • One of the biggest of these limitations is the restrictions imposed on UWB transmissions by the FCC.
  • the FCC issued regulations regarding the use of UWB devices.
  • These regulations imposed significant bandwidth and spectral power limits on any UWB transmissions. They also limited the bandwidth available for UWB transmission.
  • UWB Universal Mobile Broadband
  • the FCC has allocated the range of 3.1 GHz to 10.6 GHz for UWB, and the UNII band falls in the range of 5.15 to 5.85 GHz.
  • the UNII band is used by unlicensed devices such as cordless phones and 802.1 la wireless local area network (WLAN) devices. Because of the high power levels permitted devices in the UNII band (sometime up to one hundred times the power levels of UWB transmissions), it is preferable for UWB devices to avoid transmitting in those bands.
  • the UNII band is offered as an example of a frequency band that a UWB device may wish to avoid, in some embodiments it may be desirable to avoid other frequency bands. Furthermore, as the circumstances change, these restrictions may be increased or decreased, reducing or expanding the bandwidth available for UWB transmissions.
  • UWB devices operating in these regions may wish to avoid these frequency bands as well. Therefore, it would be desirable to provide a UWB device that would be easily modified to broadcast using different bandwidths and different center frequencies. This would allow the device to account for changes in available spectrum over the course of time, and in different jurisdictions.
  • FIG. 1 is a block diagram of an ultra-wide band transceiver according to a preferred embodiment of the present invention
  • FIG. 2 is a block diagram of a circuit for generating a single-band UWB signal, according to a preferred embodiment of the present invention.
  • FIG. 3 is a graph showing the frequency response of an ultra-wide band signal produced by the circuit of FIG. 2 according to a first preferred embodiment of the present invention
  • FIG. 4 is a graph showing the frequency response of an ultra-wide band signal produced by the circuit of FIG. 2 according to a second preferred embodiment of the present invention
  • FIG. 5 is a block diagram of a circuit for generating a dual-band UWB signal, according to a preferred embodiment of the present invention
  • FIG. 6 is a frequency graph of the output of the circuit of FIG. 5 in a low band mode, according to preferred embodiments of the present invention
  • FIG. 7 is a frequency graph of the output of the circuit of FIG. 5 in a high band mode, according to preferred embodiments of the present invention
  • FIG. 8 is a frequency graph of the output of the circuit of FIG. 5 in a dual- band mode, according to preferred embodiments of the present invention
  • FIG. 9 is a diagram showing a multiple network design using both frequency division multiplexing and code division multiplexing, according to a preferred embodiment of the present invention.
  • FIG. 10 is a block diagram of a circuit for generating a single or dual-band UWB signal, according to a preferred embodiment of the present invention.
  • FIG. 11 shows an alternate embodiment of the wavelet code generator path according to a preferred embodiment of the present invention
  • FIG. 12 is a block diagram of a circuit for generating a single-band UWB signal, according to another preferred embodiment of the present invention.
  • FIG. 1 is a block diagram of an ultra-wide band (UWB) transceiver according to a preferred embodiment of the present invention.
  • the transceiver includes three major components, a receiver 110, a transmitter 120, and a radio controller and interface 130.
  • the receiver 110 is attached to a receiving antenna 112, and includes a front end 114, a UWB waveform correlator 116, and a receiving timing generator 118.
  • the transmitter is attached to a transmitting antenna 122, and includes a UWB waveform generator 124, an encoder 126, and a transmitting timing generator 124.
  • a single radio controller and interface 130 servicing both the receiver 110 and transmitter 120
  • alternate embodiments could include a separate radio controller and interface 130 for each of the receiver 110 and transmitter 120.
  • a single antenna that is switched between transmitting and receiving may be used in place of the separate receiving and transmitting antennas 112 and 122.
  • the receiving and transmitting timing generators 118 and 128 may also be combined into a single timing generator or may be maintained as separate units.
  • the radio controller and interface 130 is preferably a processor-based unit that is implemented either with hard wired logic, such as in one or more application specific integrated circuits (ASICs) or in one or more programmable processors.
  • the radio controller and interface 130 either serves as a medium access control (MAC) controller or serves as a MAC interface between the UWB wireless communication functions implemented by the receiver 110 and transmitter 120 and applications that use the UWB communications channel for exchanging data with remote devices.
  • MAC medium access control
  • the receiving antenna 112 converts an incoming UWB electromagnetic waveform into an electrical signal (or optical signal) and provides this electrical signal to the radio front end 114.
  • the radio front end 114 processes the electric signals so that the level of the signal and spectral components of the signal are suitable for processing in the UWB waveform correlator 116. This processing may include spectral shaping, such as a matched filtering, partial matched filtering, simple roll-off, etc.
  • the UWB waveform correlator 116 After front end processing, the UWB waveform correlator 116 then correlates the incoming signal with different candidate signals generated based on a clocking signal from the timing generator 118 to determine whether the receiver 110 is synchronized with the incoming signal and if so, to determine the data contained in the received incoming signal.
  • the timing generator 118 operates under the control of the radio controller and interface 130 to provide a clocking signal CLK R that is used in the correlation process performed in the UWB waveform correlator 116.
  • This clocking signal CLK R has a phase that is preferably varied with respect to the incoming signal received at the receiving antenna 112.
  • the UWB waveform correlator uses the clocking signal CLK R to locally generate a correlation signal that matches a portion of the incoming signal and has the phase of the clocking signal CLK R .
  • the UWB waveform correlator 116 When the locally-generated correlation signal (the locally-generated signal) and the incoming signal are aligned with one another in phase, the UWB waveform correlator 116 provides high signal- to-noise ratio (SNR) data to the radio controller and interface 130 for subsequent processing.
  • SNR signal- to-noise ratio
  • the UWB waveform correlator 116 can be considered to have a correlation window containing the local signal. As the phase of the clocking signal is varied with respect to that of the incoming signal, the correlation window is shifted. The correlation window is then compared to a snapshot of the incoming signal until an acceptable correlation result is obtained for the two signals, indicating that an acquisition lock has been achieved. In some circumstances, the output of the UWB waveform correlator 116 is the data itself. In other circumstances, the UWB waveform correlator 116 simply provides an intermediate correlation result, which the radio controller and interface 130 uses to determine the data and determine when the receiver 110 is synchronized with the incoming signal.
  • the UWB waveform correlator 116 operates in two modes of operation, a signal track mode ("track mode”) and a signal acquisition mode ("acquisition mode").
  • the acquisition mode is used when synchronization either has not occurred or has been lost, and the receiver 110 is working to achieve such synchronization.
  • the track mode is used when synchronization has occurred and needs to be maintained.
  • the radio controller and interface 130 provides a control signal to the receiver 110 to acquire synchronization.
  • This control signal instructs the receiver 110 to slide the correlation window within the UWB waveform correlator 116 to try and match the phase of the incoming signal and achieve an acquisition lock. In particular, this is achieved by adjusting the phase and frequency of the clock output from the timing generator 118 until a desirable correlation result is obtained.
  • the receiver enters the track mode.
  • the transceiver operates to maintain and improve synchronization.
  • the radio controller and interface 130 analyzes the correlation result from the UWB waveform correlator 116 to determine whether the correlation window in the UWB waveform correlator 116, i.e., the phase of the local signal from the timing generator, needs to be adjusted.
  • the receiver 110 provides data to an input port ("RX Data In”) of the radio controller and interface 130, which in turn provides this data to an external process, via an output port (“RX Data Out”).
  • the external process may be any one of a number of processes performed with data that is either received via the receiver 110 or is to be transmitted via the transmitter 120 to a remote receiver.
  • the radio controller and interface 130 receives source data at an input port ("TX Data In”) from an external source.
  • the radio controller and interface 130 then applies the data to the encoder 126 of the transmitter 120 via an output port (“TX Data Out”).
  • the radio controller and interface 130 also provides control signals to the transmitter 120 for use in identifying the signaling sequence of UWB pulses.
  • the receiver 110 and the transmitter 120 functions may use joint resources, e.g., a common timing generator and/or a common antenna.
  • the encoder 126 receives user coding information and data from the radio controller and interface 130 and preprocesses the data and coding so as to provide a timing input for the UWB waveform generator 124.
  • the UWB waveform generator 124 in turn produces UWB pulses encoded in shape and/or time to convey the data to a remote location.
  • the encoder 126 performs this function in accordance with a timing signal CLK T received from the transmitting timing generator 128.
  • the encoder 126 produces the control signals necessary to generate the required modulation.
  • the encoder 126 may take a serial bit stream and encode it with a forward error correction (FEC) algorithm (e.g., such as a Reed Solomon code, a Golay code, a Hamming code, a Convolutional code, etc.).
  • FEC forward error correction
  • the encoder 126 may also interleave the data to guard against burst errors.
  • the encoder 126 may also apply a whitening function to prevent long strings of "ones" or “zeros.”
  • the encoder 126 may also apply a user specific spectrum spreading function, such as generating a predetermined length chipping code (also called a code word) that is sent as a group to represent a bit (e.g., inverted for a "one" bit and non-inverted for a "zero” bit, etc.).
  • the encoder 126 may divide the serial bit stream into subsets in order to send multiple bits per wavelet or per chipping code, and generate a plurality of control signals in order to affect any combination of desired modulation schemes.
  • the radio controller and interface 130 may provide some identification, such as user ID, etc., of the source from which the data on the input port ("TX Data In") is received.
  • this user ID may be inserted in the transmission sequence, as if it were a header of an information packet.
  • the user ID itself may be employed to encode the data, such that a receiver receiving the transmission would need to postulate or have a priori knowledge of the user ID in order to make sense of the data.
  • the ID may be used to apply a different amplitude signal (e.g., of amplitude "f ') to a fast modulation control signal as a way of impressing the encoding onto the signal.
  • the output from the encoder 126 is applied to the UWB waveform generator 124, which then produces a sequence of UWB wavelet shapes at wavelet times according to the command signals it receives from the encoder 126. These wavelet shapes may be prepared based on one of any number of different schemes.
  • the output from the UWB generator 124 is then provided to the transmitting antenna 40, which then transmits the UWB energy to a receiver.
  • the data is encoded into the signal by exploiting the shape of the wavelets.
  • the data is preferably encoded by bi-phase modulating a series of wavelets arranged according to a binary or ternary chipping code provided by the encoder 126. (A ternary code is used in the preferred embodiment.)
  • the wavelets used are three consecutive cycles of an oscillating signal, e.g., a sinusoidal waveform. In alternate embodiments, however, this could be altered. The number of cycles could be increased or decreased; the type of oscillating signal could be changed; or a differently shaped waveform could be used altogether, such as a Gaussian monopulse, or the like.
  • the chipping codes are strings of individual wavelets that are modulated according to a set pattern.
  • length 12 and 24 ternary code words are used.
  • each bit is represented by a bi-phase modulated code word
  • each code word is represented by a string of 12 or 24 wavelets modulated in a ternary fashion according to a set pattern, e.g., a ternary pattern in the preferred embodiment.
  • a particular transmission might use a length 12 code word as follows: 0 -1 -1 -1 1 1 1 -1 1 1 1 -1 1.
  • code words used could vary according to network, device, or even by transmission.
  • code words of length 12 and 24 are preferable in the present embodiment, other code word lengths can be chosen as desired.
  • FIG. 2 is a block diagram of a circuit for generating a single-band UWB signal, according to a preferred embodiment of the present invention.
  • the signal-generating circuit includes a code word generator 205, a first mixer 210, a band pass filter 215, a second mixer 220, an antenna 225, a reference frequency clock 230, a xN phase-locked loop (PLL) circuit 235, a divide-by-K circuit 240, a bit source 245, and a xM PLL circuit 250.
  • the circuit uses a repetition of multiple cycles of an oscillating signal as a UWB wavelet.
  • the reference frequency clock 230 generates a reference signal that will be used by the rest of the circuit.
  • the reference signal is a sinusoidal waveform with a frequency of 684 MHz, though this could be changed in frequency and waveform in alternate embodiments.
  • the reference signal can have frequency that varies greatly. It could be a very low frequency signal, lower than the center frequency of the lowest band in use, or it could be a very high frequency signal, having a frequency that is as high is higher than the highest band in use.
  • the reference signal preferably has a frequency that corresponds to a value in a center frequency band for the signal generated by the device. This can mean that the reference signal's frequency is within a range of the center frequency of the signal, that the reference signal's frequency is equal to the center frequency of the signal, that the reference signal's frequency is an N times the center frequency of the signal, that the reference signal's frequency is 1/N times the center frequency of the signal, or the like, where N is an integer.
  • the reference frequency is in the range of 300 MHz to 9.2 GHz, though values outside of that range can be used in some embodiments. In particular, as the speed of devices increases, correspondingly faster reference frequencies can be used. Specific values that are used for the frequency of the reference signal in preferred embodiments include 684 MHz, 1.368 GHz, 2.376 GHz, 4.104 GHz, 5.4 GHz, and 8.208 GHz.
  • the xN PLL 235 multiplies the reference frequency of the reference signal by N and provides a signal with this new frequency as a clocking signal to the code word generator 205.
  • N 2
  • the xN PLL 235 provides a clocking signal to the code word generator 205 that is twice the reference frequency (i.e., 1.368 GHz).
  • the value of N could be changed in alternate embodiments to account for different code word lengths and/or spectral bands (specified by center frequency and bandwidth).
  • the code word generator 205 provides a length L code word used to represent bits of data.
  • the rate at which individual elements of the code word (called chips) are output is equal to the frequency of the clocking signal provided from the xN PLL 235. This rate can be called the chipping rate of the code word generator 205.
  • the divide-by-K circuit 240 divides the frequency of the reference signal by K and provides a signal with this new frequency as a clocking signal to the bit source 245.
  • K 12
  • the divide-by-K circuit 240 provides a clocking signal to the bit source 245 that is one twelfth the reference frequency (i.e., 57 MHz).
  • the value of K could be changed in alternate embodiments to any value (preferably an integer) to account for different data rates.
  • the bit source 245 provides the bits of data that need to be sent by the device. This can be any sort of desired data source, so long as it provides bit data.
  • the rate at which bits are output is equal to frequency of the clocking signal provided from the divide-by-K circuit 240. This rate can be called the symbol rate of the bit source 445.
  • a given symbol is made up of P bits, where P is an integer greater than 0.
  • the bit source 445 outputs P bits each time the clocking signal provided from the divide- by-K circuit 240 cycles.
  • P is 1 and the symbol rate is 57 Ms/s, though these values could be changed in alternate embodiments.
  • the first mixer 210 multiplies the output of the code word generator 205 with the output of the bit source 245. Because the clocking signal provided to the bit
  • the value of P bits are held for the duration of an entire code word (i.e., for the duration of L wavelets).
  • the first mixer serves to modulate the code word generated by the code word generator 205 with the data bits provided by the bit source 245.
  • the xM PLL 250 multiplies the frequency of the reference signal by M and provides a signal with this new frequency as a clocking signal as a clocking signal to the second mixer 220.
  • M 6 times the reference frequency (i.e., 4.104 GHz).
  • the value of M could be changed in alternate embodiments to account for different code word lengths.
  • the value of M divided by the value of N is equal to the number of cycles of the reference signal that are used to form each wavelet of the UWB signal used by the circuit of FIG.2.
  • each wavelet is made up of three cycles of the
  • the second mixer 220 mixes the output of the xM PLL 250 and the output of the first mixer 210. This has the effect of mixing the UWB wavelets generated at the xM PLL 250 with the data-modulated code word output from the first mixer 210, to create a final UWB signal stream. Because the frequency of the signal output from
  • the xM 250 PLL is — (i.e., 3 in the preferred embodiment) times the frequency
  • the xM PLL 250 will provide 3 cycles of its signal for every element of the code word, thus generating 3 -cycle wavelets.
  • the band pass filter 215 serves to ensure that the transmitted energy is within the proper band.
  • a similar band pass filter can be used in the receiver to protect the received signal from interference from other bands.
  • the transmitted waveform preferably has a center frequency equal to the reference frequency multiplied by M, i.e., 4.104 GHz in the preferred embodiment, and a -3 dB bandwidth equal to the reference frequency multiplied by ⁇ , i.e., 1.368 GHz in the preferred embodiment.
  • the band pass filter 215 preferably has a center frequency equal to the reference frequency multiplied by M, e.g., 4.104 GHz in a preferred embodiment, and lower and upper cutoff frequencies that define the desired operational band, e.g. upper and lower 20 dB cutoff frequencies of 3.1 GHz and 5.1GHz, respectively, in a preferred embodiment.
  • M e.g. 4 GHz
  • lower and upper cutoff frequencies that define the desired operational band e.g. upper and lower 20 dB cutoff frequencies of 3.1 GHz and 5.1GHz, respectively, in a preferred embodiment.
  • This value is preferably chosen to give a response comparable to the -3 dB bandwidth, which makes the values of the cutoff frequencies used by the band pass filter 215 linearly related to the upper and lower -3 dB bandwidth limits, and so proportional to the reference frequency.
  • the various parameters for reference frequency, bandwidth, and circuit coefficients can vary in alternate embodiments.
  • the antenna 225 is configured to transmit the signal provided from the second mixer 220.
  • one of the xN PLL 235, the divide-by-K circuit 240, and the xM PLL 250 could be eliminated if the reference frequency were chosen accordingly.
  • some of the PLLs could be replaced with frequency dividers and vice versa.
  • any one of the code word generator 205, the bit source 245, and the second mixer 220 could receive the output of the reference frequency clock 230 directly.
  • each of these three elements preferably receives a clocking signal that either is the reference signal or is derived from the reference signal.
  • FIG. 2 discloses the use of PLL circuits for all of the multiplying circuits, alternate embodiments could use other types of multipliers.
  • FIG. 2 discloses the use of a band pass filter 215 after the second mixer 220
  • alternate embodiments could replace the functionality of the band pass filter 215 with a low pass filter located immediately before the second mixer 220.
  • This low pass filter would preferably have a center frequency equal to the reference frequency multiplied by M, i.e., 4.104 GHz in the preferred embodiment
  • M i.e. 4 GHz
  • the frequency response of the circuit of FIG. 2 can be modified relatively easily by simply changing the reference frequency clock 230, and altering the parameters of the band pass filter 215 to account for this change.
  • the band pass filter 215 is changed by altering its center frequency and its upper and lower cutoff points.
  • cutoff points can be set according to any of a variety of criteria, but using a -10 dB point (i.e., the point at which the strength of the signal is down 10 dB) or a -20 dB point (i.e., the point at which the strength of the signal is down 20 dB) are preferred criteria.
  • the bandwidth of the band pass filter 215 is preferably proportional to the reference frequency, though the exact proportion will depend upon what particular
  • FIG. 3 is a graph showing the frequency response of a UWB signal produced by the circuit of FIG. 2 according to a first preferred embodiment of the present invention
  • FIG. 4 is a graph showing the frequency response of a UWB signal produced by the circuit of FIG. 2 according to a second preferred embodiment of the present invention.
  • the frequency of the reference signal and the center frequency of the band pass filter 215 are both chosen to be 684 MHz
  • K is 12
  • L is 24, M is 6, and N is 2
  • the -20 dB bandwidth of the band pass filter is about 2 GHz. This provides a signal that can easily avoid UNII band in the United States.
  • the circuit of FIG. 3 the circuit of FIG.
  • the frequency of the reference signal and the center frequency of the low pass filter 215 are both chosen to be 666 MHz, K is 12, L is 24, M is 6, and N is 2, and the -20 dB bandwidth of the band pass filter is about 1.8 GHz.
  • This provides a signal that can easily avoid the Japanese equivalent of the U.S. UNII band, which is set at 4.90 TO 5.4 GHz.
  • FIGs. 3 and 4 graphically show how easily the frequency response of the circuit of FIG. 2 can be modified by altering the frequency of the reference signal generated by the reference frequency clock 230, and the parameters of the band pass filter 215.
  • FIG. 12 is a block diagram of a circuit for generating a single-band UWB signal, according to another preferred embodiment of the present invention.
  • the signal generating circuit includes an I/Q oscillator 1205, a lookup table 1210 first and second DAC circuits 1212 and 1214, a vector modulator 1220, a clocking signal generator 1225, a bit sources 1230, a wavelet code generators 1240, a switch 1295, a xN circuit 1297, and a selecting circuit 1299. It also may comprise first and second band pass filters 1280 and 1285.
  • the wavelet code generator 1240 further comprises an encoder 1250 and a mixer 1270.
  • This embodiment of the clocking signal generator further comprises a xM circuit 1222 and a divide-by-L circuit 1227. 4/079938
  • the I/Q oscillator 1205 produces an oscillating signal at an oscillating frequency.
  • the I/Q oscillator comprises a voltage controlled oscillator/phase locked loop (VCO/PLL) that provides a first in-phase and quadrature phase (I/Q) signal.
  • VCO/PLL voltage controlled oscillator/phase locked loop
  • the lookup table (LUT) 1210 contains data necessary to create sine and cosine waves of varying phase. It is controlled by a phase control signal, which instructs the lookup table 1210 to output the data corresponding the sine/cosine value for that phase.
  • phase control signal which instructs the lookup table 1210 to output the data corresponding the sine/cosine value for that phase.
  • the digital sine and cosine signals are received at the first and second DAC circuits 1212 and 1214, which convert the digital sine and cosine signals into analog sine and cosine signals, These analog sine and cosine signals are output at the I and Q outputs of the DAC circuits 1212 and 1214 as a second I/Q signal.
  • the vector modulator 1220 accepts the first I/Q signal from the I/Q oscillator 1205 and the second I/Q signal from the first and second DAC circuits 1212 and
  • This base clocking signal has a base clock frequency close to the oscillating frequency (e.g., +/- 10%), but is varied in phase and frequency based on the value and rate of change of the second I/Q signal.
  • the clocking signal generator 1225 provides clocking signals to the bit source 1230 and the wavelet code generator 1240.
  • the clocking signal generator 1225 provides a bit rate clock, a chip rate clock, and a wavelet center frequency clock.
  • the clocking signal generator 1225 passes the base clock directly as the chip rate clock, passes the base clock through the xM circuit 1222 to provide a wavelet center frequency clock that has M times the frequency of the base clock, and passes the base clock through the divide-by-L circuit to provide a bit rate clock that is 1/L times the frequency of the base clock.
  • the bit source 1230 provides the wavelet code generator with a stream of incoming bits. This can be accomplished through the use of an incoming bit stream signal and a data latch, or any other desired means of providing data bits.
  • the bit rate clock instructs the bit source 1230 as to when it should cycle through bit values.
  • the wavelet code generator 1240 accepts bit data and converts them into an ultrawide bandwidth signal having the bit values modulated into code words.
  • the encoder 1250 generates a code word that is upright or inverted based on the value of a received bit.
  • the wavelet code generator 1240 generates a coded sequence of wavelets (i.e., chips) based on the chip rate clock.
  • a chip is an inverted or non-inverted wavelet, or could be a null (i.e., a missing or zero) wavelet. This could be altered in other embodiments, however.
  • the encoder 1250 comprises a code word generator and a mixer, as shown by elements 205 and 210 in FIG. 2 and elements 405A, 405B, 410A, and 410B in FIG. 5.
  • the mixer 1070 modulates the code words generated by the encoder 1050 into wavelets, each chip in the code word being represented by one or more wavelets (as determined the ratio of the chip rate clock and wavelet center frequency clock.
  • the first and second BPFs 1080 and 1085 serve to remove extraneous frequency elements from the processed signals. Preferably their parameters are determined as noted above with respect to the filters used in the circuit of FIG. 2.
  • the first, second, and third switches 1291, 1293, and 1295 switch allow the device to selectively choose whether use a first band or a second band.
  • the selecting circuit 1299 provides the signal to choose which band to use.
  • the second and third switches 1293 an 1295 can be eliminated as well.
  • the first switch 1291 In operation, if the selecting circuit selects the first band, the first switch 1291 will connect the output of the vector modulator 1230 to the clocking signal generator 1230, and the second and third switches 1293 and 1295 will connect the wavelet code generator 1240 to the output transmit signal via the first BPF 1280. If, however, the selecting circuit selects the second band, the first switch 1291 will connect the output of the xN circuit 1297 to the clocking signal generator 1230, and the second and third switches 1293 and 1295 will connect the wavelet code generator 1240 to the output transmit signal via the second BPF 1285.
  • the xN circuit will provide the clocking signal generator 1230 with an input signal with N times the frequency of the vector modulator 1220.
  • N is the ratio of the center frequencies of the first and second bands; M is the number of cycles in a wavelet; and L is the code length used.
  • the circuit of FIG. 12 allows for two separate bands, but shares the same elements save for the switches 1291, 1293, and 1295, the xN circuit 1297, and the selecting circuit 1299. This allows for a very small device, and one that can be manufactured more cheaply than other selective band devices.
  • FIG. 5 is a block diagram of a circuit for generating a dual-band UWB signal, according to a preferred embodiment of the present invention.
  • the signal- generating circuit includes a first-band code word generator 405A, a first-band first mixer 410A, a first-band band pass filter 415A, a first-band second mixer 420A, a first-band antenna 425 A, a first-band xNi phase-locked loop (PLL) circuit 435 A, a first-band divide-by-Ki circuit 440A, a first-band bit source 445A, a first-band xMi PLL circuit 450A, second-band code word generator 405B, a second-band first mixer 41 OB, a second-band band pass filter 415B, a second-band second mixer 420B, a second-band antenna 425B, a second-band xNi phase-locked loop (PLL) circuit
  • PLL phase-locked loop
  • the elements in the signal-generating circuit of FIG. 5 operate like their counterparts in FIG. 2.
  • the first band xN] PLL 435, the first-band divide- by-Kj circuit 440A, and the a first-band Mi PLL circuit 45 OA use parameters Ni, Ki, and Mi, respectively
  • the second-band xN PLL 435, the second-band divide-by-K 2 circuit 440A, and the a second-band xM 2 PLL circuit 450A use parameters N 2 , K 2 , and M .
  • M M, ,
  • both must use the same wavelet (i.e., the same number of
  • one of the first band xN] PLL 435, the first-band divide-by-Ki circuit 440A, the first-band xMj PLL circuit 450A, the second-band xN 2 PLL 435, the second-band divide-by-K 2 circuit 440A, and the a second-band xM 2 PLL circuit 450 A could be eliminated if the reference frequency were chosen accordingly.
  • some of the PLLs could be replaced with frequency dividers and vice versa.
  • any one of the first-band code word generator 405 A, the first-band bit source 445A, the first-band second mixer 420A, second-band code word generator 405B, the second-band bit source 445B, the second-band second mixer 420B could receive the output of the reference frequency clock 430 directly.
  • the circuit of FIG. 5 discloses separate first-band and second-band bit sources 445A and 445B, the two could be combined into one.
  • This combined bit source could either provide its data to one of a plurality of separate UWB signals, or could provide its data to multiple signals, either sending the same data in multiple bands at the same time to enhance successful transmission, or sending different data in multiple bands at the same time to increase throughput.
  • circuit of FIG. 5 uses only two bands, alternate embodiments could be used that employ a greater number of bands.
  • alternate embodiments can add additional copies of the circuitry of FIG. 2, adjust the various parameters of the circuit to achieve the desired frequency response, and connect that circuit to the reference frequency clock 430.
  • FIGs. 6, 7, and 8 are frequency graphs of the output of the circuit of FIG. 5 for different modes of operation, according to preferred embodiments of the present invention.
  • FIG. 6 is a frequency graph of a low band mode
  • FIG. 7 is a frequency graph of a high band mode
  • FIG. 8 is a frequency graph of a dual-band mode.
  • L is 24, Ki is 12, Ni is 2, Mj is 6, K 2 is 6, N 2 is 4, and M 2 is 12, the reference frequency is 684 MHz, the center frequency of the first-band band pass filter 415A is 684 MHz, with an upper -20 dB cutoff of about 5.1 GHz, and a lower -20 dB cutoff of about 5.1 GHz.
  • the clock signal provided to the first-band code word generator 405A is 1.368 GHz; the clock signal provided to the first-band bit source 445 A is 57 MHz; the clock signal provided to the first-band second mixer 420A is 4.104 GHz; the clock signal provided to the second-band code word generator 405B is 2.736 GHz; the clock signal provided to the second-band bit source 445B is 114 MHz; and the clock signal provided to the second-band second mixer 420B is 8.208 GHz.
  • the low band 610 is set between 3.1 and 5.15 GHz
  • the high band 710 is set between 5.825 GHz and 10.6 GHz.
  • Both the low band 610 and the high band 710 in this embodiment are arranged so that they do not interfere with the UNII band 510.
  • the low band 610 can be set between 3.5 and 4.6 GHz
  • the high band 710 can be set between 7.0 GHz and 9.2 GHz.
  • different frequencies can be chosen based on a variety of criteria that include: the presence of interfering bands, desired data rates, power consumption restrictions, ease and cost of implementation, etc. For example, higher data rates are possible at higher frequencies, though cost and difficult of implementation will rise.
  • different frequency combinations will locate the resulting UWB signal in a particular place in the spectrum. This can be advantageous if the location of the signal remains in a part of the spectrum that avoids strong interfering bands.
  • the designs shown above in FIGs. 2 and 5 allow these frequencies to be more easily changed to account for whatever reasons a user might wish to change them.
  • FIG. 10 is a block diagram of a circuit for generating a single or dual-band UWB signal, according to a preferred embodiment of the present invention.
  • the signal generating circuit includes an I/Q oscillator 1005, a lookup table 1010 first and second DAC circuits 1012 and 1014, a vector modulator 1020, a clocking signal generator 1025, first and second bit sources 1030 and 1035, first and second wavelet code generators 1040 and 1045, a summer 1090, and a switch 1095. It also may comprise first and second band pass filters 1080 and 1085.
  • the first wavelet code generator 1040 further comprises a first encoder 1050 and a first mixer 1070, and may comprise a first low pass filter (LPF) 1060.
  • the second wavelet code generator 1045 further comprises a second encoder 1055 and a second mixer 1075, and may comprise a second LPF 1065.
  • This embodiment of the clocking signal generator further comprises a xN circuit 1021, a xM] circuit 1022, a xM 2 circuit 1023, a divide-by-Li circuit 1027, and a divide-by-L 2 circuit 1028.
  • the I/Q oscillator, 1005 produces an oscillating signal at an oscillating frequency.
  • the I/Q oscillator comprises a voltage controlled oscillator/phase locked loop (VCO/PLL) that provides a first in-phase and quadrature phase (I/Q) signal.
  • VCO/PLL voltage controlled oscillator/phase locked loop
  • the I/Q oscillator 1005 could comprise a VCO/PLL that feeds outputs with a 50% duty cycle into the inputs of a poly-phase filter. If the poly-phase filter is chosen to have the required bandwidth and phase/amplitude tolerance, then it will output the desired I/Q signal.
  • the I/Q oscillator 1005 could comprise a
  • VCO/PLL operating at twice the desired frequency feeds that outputs a signal with a 50% duty cycle into a pair of divide-by-2 frequency dividers that provide the desired I/Q signal.
  • the I/Q oscillator 1005 could comprise a VCO/PLL operating at four times the desired frequency feeds that outputs a signal with any duty cycle to a divide-by-4 frequency divider that provides the desired I/Q signal.
  • the lookup table (LUT) 1010 contains data necessary to create sine and cosine waves of varying phase. It is controlled by a phase control signal, which instructs the lookup table 1010 to output the data corresponding the sine/cosine value for that phase. These digital sine and cosine signals are each output at one of the I and Q outputs of the lookup table 1010.
  • the digital sine and cosine signals are received at the first and second DAC circuits 1012 and 1014, which convert the digital sine and cosine signals into analog sine and cosine signals, These analog sine and cosine signals are output at the I and Q outputs of the DAC circuits 1012 and 1014 as a second I/Q signal.
  • the vector modulator 1020 accepts the first I/Q signal from the I/Q oscillator 1005 and the second I/Q signal from the first and second DAC circuits 1012 and 1014, and produces a base clocking signal.
  • This base clocking signal has a base clock frequency close to the oscillating frequency (e.g., +/- 10%), but is varied in phase and frequency based on the value and rate of change of the second I/Q signal.
  • the clocking signal generator 1025 provides clocking signals to the first and second bit sources 1030 and 1035, and the first and second wavelet code generators 1040 and 1045.
  • the clocking signal generator 1025 provides first and second bit rate clocks, first and second chip rate clocks, and first and second wavelet center frequency clocks. In alternate embodiments with multiple bands, the clocking signal generator would preferably provide a bit rate clock, a chip rate clock, and a wavelet center frequency clock for each band.
  • the first and second bit sources 1030 and 1035 provide the first and second wavelet code generators with a stream of incoming bits. This can be accomplished through the use of an incoming bit stream signal and a data latch, or any other desired means of providing data bits.
  • the first and second bit rate clocks instruct the first and second bit sources 1030 and 1035, respectively, as to when they should cycle through bit values.
  • Each of the first and second wavelet code generators 1040 and 1045 accept bit data and convert them into ultrawide bandwidth signals having the bit values modulated into code words.
  • the first and second encoders 1050 and 1055 generate a code word that is upright or inverted based on the value of a received bit.
  • the first and second wavelet code generators 1040 and 1045 generate a coded sequence of wavelets (i.e., chips) based on the first and second chip rate clocks, respectively.
  • a chip is an inverted or non-inverted wavelet, or could be a null (i.e., a missing or zero) wavelet. This could be altered in other embodiments, however.
  • each of the first and second encoders 1050 and 1055 comprise a code word generator and a mixer, as shown by elements 205 and 210 in FIG. 2 and elements 405A, 405B, 410A, and 410B in FIG. 5.
  • the first mixer 1070 and second mixers 1075 modulate the code words generated by the first and second encoders 1050 and 1055 into wavelets, each chip in the code word being represented by one or more wavelets (as determined the ratio of the corresponding chip rate clock and wavelet center frequency clock.
  • the first and second LPFs 1060 and 1065, and the first and second BPFs 1080 and 1085 serve to remove extraneous frequency elements from the processed signals. Preferably their parameters are determined as noted above with respect to the filters used in the circuit of FIG. 2.
  • the summer 1090 adds the output of the first and second wavelet code generators 1040 and 1045, to provide a signal that can be broadcast in both bands.
  • the switch 1095 allows the device to selectively choose whether to connect an transmission block to the output of the first wavelet code generator 1040 (i.e., the first band alone), to the output of the second wavelet code generator 1045 (i.e., the second band alone), or to the output of the summer 1090 (i.e., the first and second bands combined.)
  • the clocking signal generator 1025 provides the various clocking signals as follows.
  • the output of the vector modulator 1020 i.e., the base frequency
  • the base frequency is passed through the divide-by-Li circuit 1027 to provide the first bit rate clock
  • the output of the xN circuit 1021 is provided to the divide-by-L 2 circuit 1028 to provide the second bit rate clock.
  • the first bit rate clock is equal to the first chip rate clock divided by Li
  • the second bit rate clock is equal to the second chip rate clock divided by L 2 .
  • the base frequency is passed through the Mi circuit 1023 to provide the first wavelet center frequency clock, while the output of the xN circuit 1021 is provided to the xM 2 circuit 1023 to provide the second wavelet center frequency clock.
  • the first wavelet center frequency clock is equal to the first chip rate clock multiplied by Mi
  • the second wavelet center frequency clock is equal to the second chip rate clock multiplied by M 2 .
  • Li is the length of the code word set used by the first band
  • L 2 is the length of the code word set used by the second band
  • N is the ratio between the center frequencies of the first and second bands
  • Mi is the number of cycles in a wavelet in the first band
  • M 2 is the number of cycles in a wavelet in the first band.
  • the clocking signal generator 1025 could be implemented differently.
  • the output of the vector modulator 1020 i.e., the base frequency
  • the base frequency is passed through a divide- by-N circuit to provide a first wavelet center frequency clock that has a frequency of 1/N times the second wavelet center frequency clock.
  • the base frequency is passed through the divide-by-M 2 circuit to provide the second chip rate clock, while the output of the divide-by-N circuit is provided to a divide-by-Mi circuit to provide the first chip rate clock.
  • the output of the divide-by-M 2 circuit is provided to a divide-by-L2 circuit to provide the second bit rate clock, while the output of the xN circuit is provided to the divide-by-Li circuit to provide the first bit rate clock.
  • the parameters for Li, L 2 , N, Mi, and M 2 are the same as in the embodiment of FIG. 10.
  • the output of the vector modulator 1020 (i.e., the base frequency) is provided unaltered as a first chip rate clock, is passed through a divide-by-L i circuit to provide the first bit rate clock, and is provided to a xMi circuit to provide the first wavelet center frequency clock.
  • the output of the xMi circuit is then provided to a xN circuit to provide the wavelet center frequency clock; the output of the xN circuit is provided to a divide-by-M circuit to provide the second chip rate clock, and the output of the divide-by-M 2 circuit is provided to a divide-by-L 2 circuit to provide a second bit rate clock.
  • the parameters for Li, L 2 , N, Mi, and M 2 are the same as in the embodiment of FIG. 10.
  • the output of the vector modulator 1020 is provided unaltered as a first chip rate clock, is passed through a divide-by-L i circuit to provide the first bit rate clock, and is provided to a xMi circuit to provide the first wave
  • the base frequency (i.e., the base frequency) is provided unaltered as a first wavelet center frequency clock, is passed through a divide-by-Li circuit to provide the first bit rate clock, and is provided to a xMi circuit to provide the first wavelet center frequency clock.
  • the output of the xMi circuit is then provided to a xN circuit to provide the wavelet center frequency clock; the output of the xN circuit is provided to a divide-by-M 2 circuit to provide the second chip rate clock, and the output of the divide-by-M 2 circuit is provided to a divide-by-L 2 circuit to provide a second bit rate clock.
  • the parameters for L ls L 2 , N, M ls and M 2 are the same as in the embodiment of FIG. 10.
  • multiple summers or a complex multiplexer could be used to provide different combinations of bands.
  • the switch 1095 could then choose between this variety of available output options. Because of the common clocking source, the alignment of the wavelets in both bands can be forced to a phase that results in the two wavelets having a controlled orthogonality relationship.
  • FIG. 11 shows an alternate embodiment of the wavelet code generator path according to a preferred embodiment of the present invention.
  • a T-flip-flop 1110, a D-flip-flop 1120, and a whitening mixer 1130 can be added to a regular wavelet code generator path to provide an alternate wavelet encoder.
  • the T-flip-flop 1110 and the D-flip-flop 1120 are provided in series. Since data is random, uncorrelated, and zero mean, when it is fed forward into the whitening mixer 1130 (placed between the mixer 1070, 1075 and the band pass filter 1080, 1085 any spurious tones left in the normal encoder will be whitened by the whitening mixer 1130. For example, if the first or second wavelet center frequency clock leaked through the mixer 1070, 1075 and spread into the data stream, the whitening mixer would remove it.
  • alternate embodiments can use a variety of methods to increase the data rate of a UWB transmission. Some embodiments could map multiple bits per symbol (i.e., P can be greater than 1), which may require QPSK waveform modulation for high values of P. Other embodiments may use shorter code word lengths, which may require forward error correction. Spectral Modes of Operation
  • the circuit shown in FIG. 5 provides three spectral modes of operation: a low band mode, a high band mode, and a dual-band mode.
  • a low band mode the device operates only using the low band 610
  • the high band mode the device operates only using the high band 710
  • the dual-band mode the device operates using both the low band 610 and the high band 710.
  • the device is limited to a lower data rate, but enjoys a greater range than the high band mode. This is because of the inherent relationship between data rate and range when all else is constant. Similarly, if the high band mode is used, it can achieve a higher data rate but with a shorter range than the low band mode. And if the dual-band is used a higher data rate than either the low band or the high band mode can be achieved, but the device will be limited to the range of the high band.
  • Using only the low band mode or only the high band mode also offers the advantage of allowing adjacent networks to engage in frequency division multiplexing. This can be used in place of or in addition to a code division multiplexing scheme based on the use of different code words.
  • FIG. 9 is a diagram showing a multiple network design using both frequency division multiplexing and code division multiplexing, according to a preferred embodiment of the present invention.
  • a plurality of wireless networks 620A, 620B, 620C, 620D, 630A, 630B, and 630C are set up adjacent to each other in a number of nearby rooms 610.
  • the dual-band mode can also provide certain unique advantages. For example, it is possible using the dual-band mode to have true duplex communication. With an appropriate diplexer, one transceiver can transmit on one of the bands (high or low), while the other transceiver transmits on the other band.
  • FEC forward error correction
  • the circuits of FIGs. 2 and 5 could be easily modified to avoid any newly-forbidden frequencies. For example, if spectral protection were provided for the range of 4.9-5.0 GHz, the circuit of FIG. 5 could be modified such that the low band 610 would avoid these frequencies.
  • the circuits of FIGs. 2 and 5 could be easily modified to take advantage of any newly-available frequencies.
  • the circuits of FIGs. 2 and 5 could be easily modified to take advantage of any newly-available frequencies.
  • a single band and dual-band embodiments are disclosed, multi-band modes using higher numbers of bands are possible.
  • alternate embodiments can add additional copies of the circuitry of FIG. 2 and adjust the various parameters of the circuit to achieve the desired frequency response.
  • a single reference frequency generator can be provided for all of the bands to use.

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  • Signal Processing (AREA)
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Abstract

L'invention concerne un procédé de génération d'un signal de largeur de bande ultralarge à bandes multiples. Dans ce procédé, un dispositif à largeur de bande ultralarge fournit un premier signal de référence ayant une première fréquence de référence, et un second signal de référence ayant une second fréquence de référence différente de la première fréquence de référence. Le dispositif génère un premier signal à largeur de bande ultralarge basé sur le premier signal de référence, et un second signal à largeur de bande ultralarge basé sur le second signal de référence, créant deux bandes de fréquences séparées. Ces deux signaux peuvent être générés à partir du même signal d'horloge de base, ce qui permet une mise en oeuvre et une modification sensiblement plus simples.
EP04715618A 2003-02-28 2004-02-27 Systeme et procede de transmission de signaux de largeur de bande ultralarge Withdrawn EP1616392A2 (fr)

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KR20050106454A (ko) 2005-11-09
JP2006519572A (ja) 2006-08-24
WO2004079938A3 (fr) 2005-11-17
US7570712B2 (en) 2009-08-04
WO2004079938A2 (fr) 2004-09-16
US20060251148A1 (en) 2006-11-09
CN1883127B (zh) 2012-06-20
CN1883127A (zh) 2006-12-20

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