EP1603106A1 - Verfahren und Vorrichtung zur Simulation der CRT-typischen Impuls-Bilddarstellung - Google Patents

Verfahren und Vorrichtung zur Simulation der CRT-typischen Impuls-Bilddarstellung Download PDF

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Publication number
EP1603106A1
EP1603106A1 EP04013037A EP04013037A EP1603106A1 EP 1603106 A1 EP1603106 A1 EP 1603106A1 EP 04013037 A EP04013037 A EP 04013037A EP 04013037 A EP04013037 A EP 04013037A EP 1603106 A1 EP1603106 A1 EP 1603106A1
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Prior art keywords
driving voltage
voltage pulse
control
value
line
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French (fr)
Inventor
Yu-Ren Shen
Cheng-Jung Chen
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VastView Technology Inc
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VastView Technology Inc
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0261—Improving the quality of display appearance in the context of movement of objects on the screen or movement of the observer relative to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only

Definitions

  • the present invention relates to a method and a device used for the simulating CRT impulse type image display, and more particularly, to a method and a device used for the simulating CRT impulse type image display with a liquid crystal display (LCD).
  • LCD liquid crystal display
  • liquid crystal display LCD
  • video products for example, television, computer, display, telephone handset, personal data assistant (PDA), and the like.
  • PDA personal data assistant
  • the varieties of the products are enormous, so as to stimulate the tremendous rapid progress of the technology of liquid crystal display and its direction of development is in agreement with the requirement of the future trend of development of electronic products toward the features of light weight, thin thickness, short length, small size, low power consumption, and low heat dissipation, etc.
  • the image display of CRT utilizes the "impulse type” image display. It produces light emissions by means of irradiating a single electron beam on the pixels coated with fluorescence materials.
  • curve (a) in Figure 1 the pixel only produces the emission of light in an instant of a minute portion of time in each frame period. Therefore, it seems almost no visional overlapping phenomenon will be noticed for the images displayed between the frames.
  • the LCD image display utilizes the "hold type” image display due to the intrinsic property of the LCD material. It produces the image display through the optical response (namely, the gray level response) by means of applying driving voltages on the LCD material. Nevertheless, due to the limitation of the intrinsic property of the liquid crystal material, the image it displays occupies the predominant portion of time of that frame as shown in curve (c) in Figure 1. And for every time its image changes, its luminance (or brightness) also changes stepwise. Therefore, from the viewpoint of the spectators, he may feel the overlapping of the image of the new frame on that of the old frame, so as to cause the blurring of the image outlines and produce the phenomenon of the so-called "after-image".
  • the kind of method utilized in this technology is a kind of "overdrive” method. It applies to the liquid crystal material the voltage (for example code 200) which is much higher than the originally set target voltage (for example code 120), so as to expedite and accelerate the response speed of the liquid crystal molecules, and accelerating them to reach the predetermined optical response value, and as such shortening the liquid crystal gray level response time to less than one frame period, as shown in curve (b) in Figure 1.
  • the voltage for example code 200
  • the originally set target voltage for example code 120
  • Figures 2A-2C which indicate the methods adopting by the prior art in simulating the CRT impulse type image display with LCD display device
  • the images displayed by the liquid crystal display of the prior art are composed of a series of frames 1, 2, 3, and 4.
  • the method utilized is to insert the complete black frames 11,12, and 13 between frames 1, 2; frames 2, 3; and frames 3, 4 so as to achieve the purpose of simulating CRT impulse type image display, and at the same time the backlight source at time points 14-20 corresponding to the time points of the above-mentioned frames are all in the illumination state.
  • the images displayed by the LCD display consist of the sequentially displayed frames 1-7.
  • the second method is performed by shutting off the backlight source at time points 22, 24, and 26 corresponding to the time points of frames 2, 4, and 6 and the backlight source at time points 21, 23, 25, and 27 corresponding to time points of frames 1, 3, 5, 7, and 9 are in the illumination state and in this manner, achieving the purpose of simulating CRT display impulse type image display with LCD display and eliminating the "after image".
  • Figure 2C indicates that the images displayed by the LCD display are composed of a series of sequentially displayed frames 1-4.
  • the method is carried out by inserting the complete black frames 11,12, and 13 between frames 1, 2; frames 2, 3; and frames 3, 4 respectively, and by putting the backlight source at time points 22, 24, and 26 corresponding to those of frames 11, 12, and 13 into the shut-off state, and by putting the backlight source at other time points corresponding to those of frames 1, 2, 3, and 4 into the illumination state.
  • the third method achieves the effect of simulating CRT display impulse type image display with LCD display by inserting the complete black frames between frames 1, 2, 3, and 4, and at the same time utilizing this blink light mode of alternate illumination state and shut off state by means of shutting off the backlight source at the corresponding time points.
  • the first method of inserting complete black frames between frames necessitates the addition of extra equipments, for example, frequency doubling device. Supposing that the original image displaying speed is 60 frames/min, then the application of this method necessitates the addition of the frequency doubling device to increase the image displaying speed to 120 frames/min, and wherein half of the number are used for inserting those black frames. Therefore, the utilization of this method would increase the cost of the equipment. Besides, the doubling of the image display frequency leads to the increase of electric-magnetic interference (EMI), and these are the drawbacks and limitations of the first method the prior art.
  • EMI electric-magnetic interference
  • the application of the second method also necessitates the addition of frequency doubling device, so as to achieve the equivalent number of display frames/unit time. Since half of the frames displayed in the unit time correspond to the backlight shut-off state and cannot be displayed as visible images. Therefore, the second method will increase the cost of the equipment, and it will also cause the increase of EMI. In addition, it requires the addition of extra equipment so as to make the backlight source blink, and therefore it further increases the cost of this method. And these are the drawbacks and limitations of the second method of the prior art.
  • the third method of the prior art is the combination of the above two methods, namely, inserting the black frames and blinking the backlight modules.
  • the drawbacks and limitations of the third method includes those of the above two methods. Therefore, it is not satisfying either.
  • the method of inserting black frames is not suitable for certain liquid crystal materials. Because for certain liquid crystal materials, their optical responses are fast from brightness to dark, and are slow from dark to brightness; but for other liquid crystal materials their optical responses are slow from brightness to dark, and are fast from dark to brightness. Therefore, the effectiveness of inserting black frames at equal time intervals in simulating CRT impulse type image display is not ideal and thus not satisfying, and in certain circumstances it is even not suitable for application. And it cannot achieve the purpose of simulating CRT display with LCD display, and it is not able to achieve the effectiveness of eliminating the "after image" either.
  • the purpose of the present invention is to provide a device used for simulating CRT impulse type image display so as to overcome and improve the drawbacks and limitations of the related prior art. It neither utilizes the method of inserting black frames, nor does it utilize the method and design of blinking the backlights. Instead, it makes use of the method of providing the scanning black lines on the screen of the LCD display, to ensure achieving the purpose of simulating CRT impulse type image display, and to effectively eliminate the "after image” and phenomenon of image outline blurring, so as to significantly improve the quality of the displayed images of the LCD display, and save the spending on the additional equipment.
  • the present invention provides a device to achieve simulating CRT display with LCD display, and it basic structure comprising:
  • the present invention also provides a method used for simulating CRT impulse type image display.
  • Figure 1 is the diagram of comparison of optical response curves of CRT image display, liquid crystal image display, and the simulated CRT impulse type image display;
  • Figures 2(a) to 2(c) indicate the methods of inserting black frames, black light blinking, and the combination of the two used by the prior art in simulating CRT display with LCD display;
  • Figure 3(a) is the schematic diagram indicating the pixel array formed by the cross points of a plurality of gate lines and data lines, and the driving circuit formed by a plurality of data driver and gate driver according the first embodiment of the present invention
  • Figure 3(b) indicates the simulation device according to the first embodiment of the present invention
  • Figures 4(a) to 4(e) are the corresponding waveform diagrams of the control voltage pulse, driving voltage pulse, and the liquid crystal optical response curve generated by the simulation device according to the first embodiment of the present invention
  • Figure 5(a) is the schematic diagram indicating the pixel array formed by the cross points of a plurality of gate lines and data lines, and the driving circuit formed by a plurality of data driver and gate driver according the second embodiment of the present invention
  • Figure 5(b) indicates the simulation device according to the second embodiment of the present invention.
  • Figures 6(a) to 6(g) are the corresponding waveform diagrams of the control voltage pulse, driving voltage pulse, and the liquid crystal optical response curve generated by the simulation device according to the second embodiment of the present invention.
  • Figure 7(a) is the schematic diagram indicating the pixel array formed by the cross points of a plurality of gate lines and data lines, and the driving circuit formed by a plurality of data driver and gate driver according the third embodiment of the present invention
  • Figure 7(b) indicates the simulation device according to the third embodiment of the present invention.
  • Figures 8(a) to 8(d) are the corresponding waveform diagrams of the control voltage pulse, driving voltage pulse, and the liquid crystal optical response curve generated by the simulation device according to the third embodiment of the present invention.
  • Figure 9(a) is the schematic diagram indicating the pixel array formed by the cross points of a plurality of gate lines and data lines, and the driving circuit formed by a plurality of data driver and gate driver according the fourth embodiment of the present invention
  • Figure 9(b) indicates the simulation device according to the fourth embodiment of the present invention.
  • Figures 10(a) to 10(d) are the corresponding waveform diagrams of the control voltage pulse, driving voltage pulse, and the liquid crystal optical response curve generated by the simulation device according to the fourth embodiment of the present invention.
  • Figure 11(a) is the schematic diagram indicating the pixel array formed by the cross points of a plurality of gate lines and data lines, and the driving circuit formed by a plurality of data driver and gate driver according the fifth and sixth embodiments of the present invention
  • Figure 11(b) indicates the simulation device according to the fifth and the sixth embodiments of the present invention.
  • Figures 12(a) to 12(e) are the corresponding waveform diagrams of the control voltage pulse, driving voltage pulse, and the liquid crystal optical response curve generated by the simulation device according to the fifth embodiment of the present invention.
  • Figures 13(a) to 13(e) are the corresponding waveform diagrams of the control voltage pulse, driving voltage pulse, and the liquid crystal optical response curve generated by the simulation device according to the six embodiment of the present invention.
  • the waveforms displayed are mainly used as instruments or tools to describe the voltage applied on the liquid crystal, and the characteristics and behaviors of the liquid crystal optical response. And the features and advantages of the present invention will be explained based on the above descriptions.
  • the abscissa indicates time, and its units is millisecond (ms), with A1 to A6 as the sequentially progressing time points; and its ordinate indicates driving voltage, with "code” as its displaying unit.
  • the time of the waveform progression on the abscissa can be divided into (N-1)th, Nth, (N+1)th ,(N+2)th, and so on, equal frame time partitions as units of frame time.
  • the dotted lines in Figures 4(a), 6(a), 8(a), 10(a), and 12(a) indicate the optical response (namely, the gray level response) path characteristic curves for the liquid crystal molecules under the application of various different driving voltages.
  • the optical response is the luminance displayed by the liquid crystal, and with nits (cd/m 2 ) as its unit.
  • the waveform shown in Figure 4(b) represents the pulse of control voltage applied on the gate of transistor Q of the simulation device in Figure 3(b);
  • the waveform shown in Figure 4(c) represents the pulse of control voltage applied on the gate of transistor Q 'of the simulation device in Figure 3(b);
  • the waveform shown in Figure 4(d) represents the pulse of driving voltage applied on the source of transistor Q of the simulation device in Figure 3(b);
  • the waveform shown in Figure 4(e) represents the pulse of driving voltage applied on the source of transistor Q' of the simulation device in Figure 3(b);
  • V LC represents the pulse of output driving voltage generated by the simulation device, and
  • V COM represents the reference voltage
  • the abscissa representing time is arranged below Figure 4(e) for jointly used by Figures 4(a) to 4(e), and for being conveniently referenced and compared between Figures 4(a) to 4(e); and A1 to A6 represent the sequentially progressing points of time.
  • Figure 3(a) indicates: the pixel array formed by the cross points of a plurality of gate lines and data lines, and the driving circuit formed by a plurality of data driver and gate driver according to the first embodiment of the present invention.
  • Figure 3(b) represents the simulation device according to the first embodiment.
  • the simulation device comprises: a first input control line (G 1 );a second input control line (G 1' );a first input data line (D 1 );a second input data line (D 1' );a first capacitor (C S ); a second capacitor (C LS ); driving voltage output line; a first transistor(Q) comprising a first gate connected to the first input control line (G 1 ), a first source connected to the first input data line (D 1 ), and a first drain connected to the driving voltage output line and the first capacitor (C S ) and the drain of the second transistor(Q'); and a second transistor(Q') comprising a second gate connected to the second input control line (G 1' ), a second source connected to the second input data line (D 1' ), a second drain connected to the drain of the said first transistor and the second capacitor (C LC ) and driving voltage output line; wherein the said first capacitor and the said second capacitor are storage capacitor and liquid crystal equivalent capacitor respectively and are connected to
  • the following is the simulation method used for the simulation device according to the first embodiment of the present invention, comprising the following steps: (I) providing the first control signal (G 1 ) with periodic pulse waveforms to the first gate of the first transistor (Q) of the said circuit; (II) providing the second control signal (G 1' ) with periodic pulse waveforms to the second gate of the second transistor (Q') of the said circuit, wherein the second control signal (G 1' ) is the same as the first control signal (G 1 ) except the phase delay; (III) providing the first data signal (D 1 ) to the source of the first transistor (Q) of the said circuit, when activated by the said first control signal (G 1 ), the said circuit feeds the first data signal (D 1 )to the said driving voltage output line; (IV) providing the second data signal (D 1' )to the source of the second transistor (Q') of the said circuit, when activated by the said second control signal (G 1' ), the said circuit feeds the second data signal (D 1' )
  • the driving voltages V 1 , V 2 , V 3 can be considered as a kind of voltage value expressed in "code".
  • the said driving voltage can 6reach its target voltage momentarily, however, the liquid crystal molecules have to take a certain period of response time to reach its optical response target position after being applied the driving voltages. This is due to the intrinsic property of the liquid crystal.
  • this voltage indicates the phenomenon of alternating positive and negative phases during the control and driving process of the liquid crystal (namely, the waveforms of the pulses of driving voltages D 1 , D 1' ; and V LC indicate the phenomenon of alternating positive and negative phases relative to the reference voltage V COM ).
  • the value of driving voltage pulse D 1' in the (N-1)th frame before time point A1 is V 1' (code 0), and the value of the driving voltage pulse V LC is V 1' (code 0) of negative polarity; at time point A1, the waveform enters the Nth frame, at this time the value of the driving voltage pulse D 1 increases to V2 (code 32), and due to the activation of the control voltage pulse G 1 , therefore the value of driving voltage pulse V LC generated by the simulation device also increases to V 2 (code 32) of positive polarity and remains so until time point A2; then the time proceeds to time point A2, at this time the value of driving voltage pulse D 1' is V 1 (code 0), and due to the activation of control voltage pulse G 1' , resulting in the value of driving voltage pulse V LC to drop momentarily from V 2 (code 32) to V 1 (code 0) and is still of positive polarity, and this value is maintained until time point A3; then the time proceeds to time point A3 and enters the
  • control voltage pulses G 1, G 1' and driving voltage pulses D 1 , D 1' , and V LC at the various time points after time points A6 can easily be inferred based on the above descriptions.
  • the dotted line as shown in Fig 4(a) is the liquid crystal optical response characteristic curve produced while performing the simulation drive.
  • the output driving voltage of the simulation device between each time point is code 0 as shown in the figure, this means that the black line scanning is performed on the display screen during this period, and by doing so, it can achieve the same results as inserting black frames or shutting off the backlights, so as to achieve the purpose of simulating CRT display impulse type image display.
  • n shown at pulse G 1' in the Nth frame as shown in Figure4(c) indicates n pulses, which means that there exists the time difference of n scanning lines between the control voltage pulse G 1 and G 1' in the same frame, namely, from the standpoint of the pixel, another control driving pulse G 1 will be input, at only nG 1 pulses after the first G 1 pulse. And this interval of time represented by n can be properly adjusted by the designer depending on the actual requirements such as the property of liquid crystal material etc., so as to ensure achieving the effectiveness of simulating CRT display impulse type image display. And this is the most important advantage of the present invention over prior art.
  • Figure 5(a) indicates: the pixel array formed by the cross points of a plurality of gate lines and data lines, and the driving circuit formed by a plurality of data driver and gate driver according to the second embodiment of the present invention.
  • Figure 5(b) represents the simulation device according to the second embodiment.
  • the simulation device of the second embodiment comprises: a first input control line(G 1 ); a second input control line (G 1' ); a first input data line (D 1 ); a second input data line (D 1' ); a third input data line (D'); a fourth input data line (D); a fifth input data line (Ds); a first capacitor (C S ); a second capacitor (C LS ); a third transistor(Q3); a fourth transistor(Q4); driving voltage output line; a first transistor(Q) comprising a first gate connected to the first input control line (G 1 ), a first source connected to the input data line (D 1 ), and a first drain connected to the driving voltage output line and the first capacitor (C S ) and the drain of the second transistor(Q'); and a second transistor(Q') comprising a second gate connected to the second input control line (G 1' ), a second source connected to the second input data line (D 1' ),
  • the following is the simulation method used for the simulation device according to the second embodiment of the present invention, comprising the following steps: (I) providing the first control signal (G 1 ) with periodic pulse waveforms to the first gate of the first transistor (Q) of the said circuit; (II) providing the second control signal (G 1' ) with periodic pulse waveforms to the second gate of the second transistor (Q') of the said circuit wherein the second control signal (G 1' ) is the same as the first control signal (G 1 ) except the phase delay; (III) providing the fifth data signal (Ds) to the sources of the third transistor (Q3) and fourth transistor (Q4) connected in parallel; (IV) providing the third data signal (D') to the gate of the third transistor (Q3); (V) providing the voltage pulse generated by the drain of the third transistor to the source of the first transistor (Q1) as the first data signal (D1), when the said first transistor (Q1) is activated by the first control signal (G1), the first data signal (D1) is fed by the said circuit to the driving
  • this voltage indicates the phenomenon of alternating positive and negative phases during the control and driving process of the liquid crystal (namely, the waveforms of the pulses of driving voltages D 1 , D 1' , and V LC indicate the phenomenon of alternating positive and negative phases relative to the reference voltage V COM ).
  • the value of driving voltage pulse D 1' in the (N-1)th frame before time point A1 is V 1' (code 0), and the value of the driving voltage pulse V LC is V 1' (code 0) of negative polarity; at time point A1, the waveform enters the Nth frame, at this time the value of the driving voltage pulse D 1 increases to V2 (code 32), and due to the activation of the control voltage pulse G 1 , therefore the value of driving voltage pulse V LC generated by the simulation device also increases to V 2 (code 32) of positive polarity and remains so until time point A2; then the time proceeds to time point A2, at this time the value of driving voltage pulse D 1' is V 1 (code 0), and due to the activation of control voltage pulse G 1' , resulting in the value of driving voltage pulse V LC to drop momentarily from V 2 (code 32) to V 1 (code 0) and is still of positive polarity, and this value is maintained until time point A3; then the time proceeds to time point A3 and enters the
  • control voltage pulses G 1 , G 1' and driving voltage pulses D 1 , D 1' , and V LC at the various time points after time points A6 can easily be inferred based on the above descriptions.
  • Figures 6(d) and 6(e) indicate the waveforms of the voltage pulses of the third and fourth data signals of Figure 5(a).
  • the dotted line as shown in Fig 6(a) is the liquid crystal optical response characteristic curve produced while performing the simulation drive.
  • the output driving voltage of the simulation device between each time point is code 0 as shown in the figure, this means that the black line scanning is performed on the display screen during this period, and by doing so, it can achieve the same results as inserting black frames or shutting off the backlights, so as to achieve the purpose of simulating CRT display impulse type image display.
  • n shown at pulse G 1' in the Nth frame as shown in Figure 6(c) indicates n pulses, which means that there exists the time difference of n scanning lines between the control voltage pulse G 1 and G 1' in the same frame, namely, from the standpoint of the pixel, another control driving pulse G 1 will be input, at only nG 1 pulses after the first G 1 pulse. And this interval of time represented by n can be properly adjusted by the designer depending on the actual requirements such as the property of liquid crystal material etc., so as to ensure achieving the effectiveness of simulating CRT display impulse type image display. And this is the most important advantage of the present invention over prior art.
  • the waveform of the driving voltage pulse V LC output by the simulation device of the present Embodiment as shown above is the same as that of Embodiment 1, so as to avoid it being too complicated to understand in the process of explanation.
  • the waveform can be designed to have various variations according to the actual requirements of the LCD display.
  • Figure 7(a) indicates: the pixel array formed by the cross points of a plurality of gate lines and data lines, and the driving circuit formed by a plurality of data driver and gate driver according to the third embodiment of the present invention.
  • Figure 7(b) represents the simulation device according to the third embodiment.
  • the simulation device comprises: a first input control line(G 1 ); a second input control line (G 1' ); a first input data line (D 1 ); a first capacitor (C S ); a second capacitor (C LS ); driving voltage output line; a first transistor (Q) comprising a first gate connected to the first input control line (G 1 ), a first source connected to the first input data line (D 1 ), and a first drain connected to the driving voltage output line and the first capacitor (C S ) and the second drain of the second transistor (Q'); and a second transistor (Q') comprising a second gate connected to the second input control line (G 1' ), a second source connected to ground, a second drain connected to the drain of the said first transistor and the second capacitor (C LC ) and driving voltage output line; wherein the said first capacitor and the said second capacitor are storage capacitor and liquid crystal equivalent capacitor respectively and are connected to ground, and the driving voltage output line is used to output the driving voltage used
  • the following is the simulation method used for the simulation device according to the third embodiment of the present invention, comprising the following steps: (I) providing the first control signal (G 1 ) with periodic pulse waveforms to the first gate of the first transistor (Q) of the said circuit; (II) providing the second control signal (G 1' ) with periodic pulse waveforms to the second gate of the second transistor (Q') of the said circuit, wherein the second control signal (G 1' ) is the same as the first control signal (G 1 ) except the phase delay; (III) providing the first data signal (D 1 ) to the source of the first transistor (Q) of the said circuit, when activated by the said first control signal (G 1 ), the said circuit feeds the first data signal (D 1 ) to the said driving voltage output line; (IV) when activated by the second control signal (G 1' ), the ground potential voltage (code 0) is fed by the said circuit to the driving voltage output line; and (V) outputting the said output driving voltages generated by the above steps to the said pixels
  • this voltage indicates the phenomenon of alternating positive and negative phases during the control and driving process of the liquid crystal (namely, the waveforms of the pulses of driving voltages D 1 , D 1' and V LC indicate the phenomenon of alternating positive and negative phases relative to the reference voltage V COM ).
  • the value of driving voltage pulse D 1 in the (N-1)th frame before time point A1 is V 2' (code 32), and the value of the driving voltage pulse V LC is V com (since the source of the second transistor is connected to V com ); at time point A1, the waveform enters the Nth frame, at this time the value of the driving voltage pulse D 1 increases to V2 (code 32), and due to the activation of the control voltage pulse G 1 , therefore the value of driving voltage pulse V LC generated by the simulation device also increases to V 2 (code 32) of positive polarity and it remains so until time point A2; then the time proceeds to time point A2, at this time the value of driving voltage pulse D 1 is still V 2 (code 32), and due to the activation of control voltage pulse G 1' (since the source of the second transistor is connected to V com ), resulting in the value of driving voltage pulse V LC to drop momentarily from V 2 (code 32) to V 1 (code 0) and is still of positive polarity, and this value is maintained until time
  • control voltage pulses G 1 , G 1' and driving voltage pulses D 1 , D 1' and V LC at the various time points after time points A6 can easily be inferred based on the above descriptions.
  • the dotted line as shown in Figure 8(a) is the liquid crystal optical response characteristic curve produced while performing the simulation drive.
  • V LC of the simulation device between each time point V com as shown in the figure
  • n shown at pulse G 1' in the Nth frame as shown in Figure8(c) indicates n pulses, which means that there exists the time difference of n scanning lines between the control voltage pulse G 1 and G 1' in the same frame, namely, from the standpoint of the pixel, another control driving pulse G 1' will be input, at only nG 1 pulses after the first G 1 pulse.
  • this interval of time represented by n can be properly adjusted by the designer depending on the actual requirements such as the property of liquid crystal material etc., so as to ensure achieving the effectiveness of simulating CRT display impulse type image display. And this is the most important advantage of the present invention over prior art.
  • the waveform of the driving voltage pulse V LC output by the simulation device of the present Embodiment as shown above is the same as that of Embodiment 1, so as to avoid it being too complicated to understand in the process of explanation.
  • the waveform can be designed to have various variations according to the actual requirements of the LCD display.
  • Figure 9(a) indicates: the pixel array formed by the cross points of a plurality of gate lines and data lines, and the driving circuit formed by a plurality of data driver and gate driver according to the fourth embodiment of the present invention.
  • Figure 9(b) represents the simulation device according to the fourth embodiment.
  • the simulation device of the fourth Embodiment comprises: a first input controlline(G 1 ); a second input control line (G m ); a first input data line (D 1 ); a first capacitor (C S ); a second capacitor (C LS ); a driving voltage output line; and a first transistor(Q) comprising: a gate connected to the first input control line (G 1 ) or the second input control line (G m ), a source connected to the input data line (D 1 ), and a drain connected to the driving voltage output line and two capacitors (C S , C LS ) connected in parallel; and wherein the said first capacitor and second capacitor are connected to ground, and the driving voltage output line is used to output the driving voltage used for simulation to the said pixels of the LCD panel so as to display images, and it is characterized in that the said input data line is connected to a data driver, the said input control line is connected to the gate driver, the said gate driver contains: an output enable (OE)
  • OE output enable
  • the following is the simulation method used for the simulation device according to the fourth embodiment of the present invention, comprising the following steps: (I) providing the data signal (D1) with periodic pulse waveform to the source of the said first transistor (Q1); (II) providing control signals OE and STH to the gate driver, so as to generate the synchronous control signals G1, Gm and providing them to the gate of the said transistor (Q1) via the first and second input control lines; (III) when activated by the said synchronous control signals G1,Gm, the said circuit feeds the said data signal to the said driving voltage output line; and (IV) outputting the said output driving voltage generated by the above steps to the said pixels so as to display images.
  • this voltage indicates the phenomenon of alternating positive and negative phases during the control and driving process of the liquid crystal (namely, the waveforms of the pulses of driving voltages D 1 and V LC indicate the phenomenon of alternating positive and negative phases relative to the reference voltage V COM ).
  • the value of driving voltage pulse D 1 in the (N-1)th frame before time point A1 is V 1' (code 0), and the value of the driving voltage pulse V LC is V 1' (code 0) of negative polarity; at time point A1, the waveform enters the Nth frame, at this time the value of the driving voltage pulse D 1 increases to V2 (code 32), and due to the activation of the control voltage G 1 , therefore the driving voltage pulse V LC generated by the simulation device also increases to V 2 (code 32) of positive polarity and remains so until time point A2; then the time proceeds to time point A2, at this time the value of driving voltage pulse D 1 is V 1 (code 0), and due to the activation of control voltage pulse G 1 , resulting in the value of driving voltage pulse V LC to drop momentarily from V 2 (code 32) to V 1 (code 0) and is still of positive polarity, and this value is maintained until time point A3; then the time proceeds to time point A3 and enters the (N+1)th frame
  • control voltage pulses G 1 , G 1' and driving voltage pulses D 1 , and V LC at the various time points after time points A6 can easily be inferred based on the above descriptions.
  • the dotted line as shown in Figure 10 (a) is the liquid crystal display optical response characteristic curve produced while performing the simulation drive.
  • V LC of the simulation device between each time point is code 0 as shown in the figure, this means that the black line scanning is performed on the display screen during this period, and by doing so, it can achieve the same results as inserting black frames or shutting off the backlights, so as to achieve the purpose of simulating CRT display impulse type image display.
  • G m and G 1 are synchronous control voltage pulses.
  • the scanning line generated by the G m control and the scanning line generated by G 1 control are separated on the screen by m-1 scanning lines, and these two scanning lines execute scanning on the display screen in a synchronous manner.
  • the relations between the waveforms of control voltage pulse G m and driving voltage pulse D 1 , V LC are the same as those between the waveforms of control voltage pulse G 1 and driving voltage pulse D 1 , V LC (namely, the description above regarding Figures 10(a) to 10(d)), therefore, it will not be repeated here.
  • the waveform of the driving voltage pulse V LC output by the simulation device of the present Embodiment as shown above is the same as that of Embodiment 1, so as to avoid it being too complicated to understand in the process of explanation.
  • the waveform can be designed to have various variations according to the actual requirements of the LCD display.
  • the waveform of the driving voltage pulse V LC output by the simulation device of the present Embodiment as shown above is the same as that of Embodiment 1, so as to avoid it being too complicated to understand in the process of explanation.
  • the waveform can be designed to have various variations according to the actual requirements of the LCD display.
  • the separation of m scanning lines between two subsequent control voltage pulses G 1 ( Figure 10(b)) and Gm ( Figure 10(c)) in the same frame can be adjusted depending on the actual effectiveness desired to be achieved and the design requirements. And this is the important invention and feature of the present case, and it is not disclosed in all the related prior art.
  • Figures 11(a), 11(b) and Figures 12(a) to 12(e) as we explain the fifth embodiment of the present invention.
  • Figures 11(a) and 11(b) are used to describe the fifth Embodiment and the subsequent sixth Embodiment of the present invention, its purpose is to indicate that: different image display effects can be achieved on the display screen by utilizing different control methods with the same device, and this characteristic will be discussed as follows.
  • Figure 11(a) indicates: the pixel array formed by the cross points of a plurality of gate lines and data lines, and the driving circuit formed by a plurality of data driver and gate driver according to the fifth embodiment of the present invention.
  • Figure 11(b) represents the simulation device according to the fifth embodiment.
  • the simulation device of the fifth Embodiment comprises: a first input control line(G 1 ); a second input control line (G m+1 ); a third input control line (G 2m+1 ); a first input data line (D 1 ); a first capacitor (C S ); a second capacitor (C LS ); and a driving voltage output line; and a first transistor(Q) comprising a gate connected to the first input control line (G 1 ) or the second input control line (G m+1 ) or the third input control line (G 2m+1 ); a source connected to the first input data line (D 1 ), and a drain connected to the driving voltage output line and two capacitors (C S , C LS ) connected in parallel; and wherein the said first capacitor and second capacitor are the storage capacitor and liquid crystal equivalent capacitor respectively and connected to ground, and the driving voltage output line is used to output the driving voltage used for simulation to the said pixels of the LCD panel so as to display images, and it is characterized
  • the following is the simulation method used for the simulation device according to the fifth embodiment of the present invention, comprising the following steps: (I) providing the data signal (D1) with periodic pulse waveform to the source of the said first transistor (Q1); (II) providing the OE and STH control signals to the first, second, and third output enable (OE) input lines and start pulse horizontal (STH) input lines of the said gate driver, and receiving the related signals via the said input lines, the said output enable (OE) signals input by the said gate drivers are so controlled that the two sets of synchronous control voltage pulses generated at the output of the said gate drivers are selected from the following three sets of control voltage pulses: (1) (G 1 , G m ), (2) (G m+1 , G 2m ), (3) (G 2m+1 , G 3m ); and these two sets of control voltage pulses (1,3), or (1, 2), or (2, 3) are selected from the said three sets of control voltage pulses and then arranged and combined, such that they are provided to the gate of the said transistors (Q1)
  • this voltage indicates the phenomenon of alternating positive and negative phases during the control and driving process of the liquid crystal (namely, the waveforms of the pulses of driving voltages D 1 , V LC indicate the phenomenon of alternating positive and negative phases relative to the reference voltage V COM ).
  • the value of driving voltage pulse D 1 in the (N-1)th frame before time point A1 is V 1' (code 0), and the value of the driving voltage pulse V LC is V 1' (code 0) of negative polarity; at time point A1, the waveform enters the Nth frame, at this time the value of the driving voltage pulse D 1 increases to V2 (code 32), and due to the activation of the control voltage G 1 , therefore the value of output driving voltage pulse V LC generated by the simulation device also increases to V 2 (code 32) of positive polarity and it remains so until time point A2; then the time proceeds to time point A2, at this time the value of driving voltage pulse D 1 is V 1 (code 0), and due to the activation of control voltage pulse G 1 , resulting in the value of driving voltage pulse V LC to drop momentarily from V 2 (code 32) to V 1 (code 0) and is still of positive polarity, and this value is maintained until time point A3; then the time proceeds to time point A3 and enters the (N
  • control voltage pulses G m+1 , G 2m+1 and driving voltage pulses D 1 , and V LC at the various time points after time points A6 can easily be inferred based on the above descriptions.
  • the dotted line as shown in Figure 12(a) is the liquid crystal display optical response characteristic curve produced while performing the simulation drive.
  • V LC of the simulation device between each time point is code 0 as shown in the figure, this means that the black line scanning is performed on the display screen during this period, and by doing so, it can achieve the same results as inserting black frames or shutting off the backlights, so as to achieve the purpose of simulating CRT display impulse type image display.
  • the waveform of the driving voltage pulse V LC output by the simulation device of the present Embodiment as shown above is the same as that of Embodiment 6, so as to avoid it being too complicated to understand in the process of explanation.
  • the waveform can be designed to have various variations according to the actual requirements of the LCD display.
  • the purpose of the present invention is to generate two synchronous scanning lines on the display screen as shown in Figures 12 (b), 12(c) and 12(d).
  • G 1 , G m+1 , G 2m+1 are synchronous control voltage pulses, and two sets of scanning lines are generated on the display screen by the driving voltage pulses generated through the control of the said control voltage pulses, and are performed synchronous scanning separated by 2m scanning lines so as to display images.
  • Figures 11(a), 11(b) and Figures 13(a) to 13(e) as we explain sixth embodiment of the present invention.
  • Figures 11(a) and 11(b) are used to describe the sixth Embodiment and the preceding fifth Embodiment of the present invention, its purpose is to indicate that: different image display effects can be achieved on the display screen by utilizing different control methods with the same device, and this characteristic will be discussed as follows.
  • Figure 11(a) indicates: the pixel array formed by the cross points of a plurality of gate lines and data lines, and the driving circuit formed by a plurality of data driver and gate driver according to the sixth embodiment of the present invention.
  • Figure 11(b) represents the simulation device according to the sixth embodiment.
  • the simulation device of the sixth Embodiment comprises: a first input control line(G 1 ); a second input control line (G m+1 ); a third input control line (G 2m+1 ); a first input data line (D 1 ); a first capacitor (C S ); a second capacitor (C LS ); a driving voltage output line; and a first transistor(Q) comprising a gate connected to the first input control line (G 1 ) or the second input control line (G m+1 ) or the third input control line (G 2m+1 ); a source connected to the first input data line (D 1 ), and a drain connected to the driving voltage output line and two capacitors (C S , C LS ) connected in parallel; wherein the said first capacitor and second capacitor are the storage capacitor and liquid crystal equivalent capacitor respectively and connected to ground, and the driving voltage output line is used to output the driving voltage used for simulation to the said pixels of the LCD panel so as to display images, and it is characterized in that
  • the following is the simulation method used for the simulation device according to the sixth embodiment of the present invention, comprising the following steps: (I) providing the data signal (D1) with periodic pulse waveform to the source of the said first transistor (Q1); (II) providing the OE and STH control signals to the first, second, and third output enable (OE) input lines and start pulse horizontal (STH) input lines of the said gate driver, and receiving the related signals via the said input lines, the said output enable (OE) signals input by the said gate drivers are so controlled that the three sets of synchronous control voltage pulses generated at the output of the said gate drivers are selected from the following three sets of control voltage pulses: (1) (G 1 , G m ), (2) (G m+1 , G 2m ), (3) (G 2m+1 , G 3m ); and these three sets of control voltage pulses (1,2,3) are provided to the gate of the said transistors (Q1) through the corresponding first, second and third input control lines, and it is characterized in that when activated by the said three sets of synchronous control
  • this voltage indicates the phenomenon of alternating positive and negative phases during the control and driving process of the liquid crystal (namely, the waveforms of the pulses of driving voltages D 1 , V LC indicate the phenomenon of alternating positive and negative phases relative to the reference voltage V COM ).
  • the value of driving voltage pulse D 1 in the (N-1)th frame before time point A1 is V 1' (code 0), and the value of the driving voltage pulse V LC is V 1' (code 0) of negative polarity; at time point A1, the waveform enters the Nth frame, at this time the value of the driving voltage pulse D 1 increases to V2 (code 32), and due to the activation of the control voltage G 1 , therefore the value of output driving voltage pulse V LC generated by the simulation device also increases to V 2 (code 32) of positive polarity and it remains so until time point A2; then the time proceeds to time point A2, at this time the value of driving voltage pulse D 1 is V 1 (code 0), and due to the activation of control voltage pulse G 1 , resulting in the value of driving voltage pulse V LC to drop momentarily from V 2 (code 32) to V 1 (code 0) and is still of positive polarity, and this value is maintained until time point A3; then the time proceeds to time point A3 and enters the (N
  • control voltage pulses G m+1 , G 2m+1 and driving voltage pulses D 1 , and V LC at the various time points after time points A6 can easily be inferred based on the above descriptions.
  • the dotted line as shown in Figure 13(a) is the liquid crystal display optical response characteristic curve produced while performing the simulation drive.
  • V LC of the simulation device between each time point code 0 as shown in the figure, this means that the black line scanning is performed on the display screen during this period, and by doing so, it can achieve the same results as inserting black frames or shutting off the backlights, so as to achieve the purpose of simulating CRT display impulse type image display.
  • the purpose of the present invention is to generate three synchronous scanning lines on the display screen as shown in Figures 13 (b), 13(c) and 13(d).
  • G 1 , G m+1 , G 2m+1 are synchronous control voltage pulses, and three sets of scanning lines are generated on the display screen by the driving voltage pulses generated through the control of the said control voltage pulses, and perform the synchronous line scanning on the screen separated by m scanning lines so as to display images.
  • G m+1 and G 1 are synchronous control voltage pulses, and the scanning lines generated through the control of G m+1 and the scanning lines generated through the control of G 1 are separated by m scanning lines on the screen, and these two sets of scanning lines perform scanning on the screen in a synchronous manner, namely, start scanning on the screen from the first and the (m+1)th scanning lines respectively.
  • the relations between the waveforms of the control voltage pulses G m+1 and the driving voltage pulses D 1 , V LC are the same as those between waveforms of the control voltage pulse G1 and the driving voltage pulses D 1 , V LC (namely, as explained above with reference to Figures 13(a) to 13(e)), therefore, it will not be repeated here.
  • the corresponding driving voltage pulses generated by the control voltage pulses (G m+1 , G 2m ), (G 2m+1 , G 2m ), and the resulting scanning lines generated on the screen start scanning lines generated on the screen, start scanning from the (m+1)th, (2m+1)th scanning lines downward on the screen respectively in a synchronous manner (namely, the three sets of scanning lines generated on the display screen by the present embodiment, start scanning downward synchronously from the first, (m+1)th and (2m+1)th scanning lines in a repeated cyclic manner).
  • the waveform of the driving voltage pulse V LC output by the simulation device of the present Embodiment as shown above is the same as that of Embodiment 1, so as to avoid it being too complicated to understand in the process of explanation.
  • the waveform can be designed to have various variations according to the actual requirements of the LCD display.
  • the method and device of the present invention are characterized in that, the scanning black lines as described above can also achieve the similar effects of writing black frames, blinking backlights, or the combination of this two methods of the prior art, so as to simulate the CRT impulse type image display with LCD display, and apparently it is superior to the prior art for the following reasons:
  • the present invention can save the extra cost and expense of the additional frequency doubling device or the backlight blinking equipment as required by the prior art;
  • the present invention can avoid the electric magnetic interference induced by the additional equipment
  • the interval between two input control voltage pulses G1 and G1' whinin the duration of the same frame can be adjusted depending on the actual requirements, so as to make the duration of the liquid crystal optical gray level response and the black line scanning (especially the black line scanning) adjustable in the duration of the same frame. Therefore, the designer of the LCD display is able to adjust the duration of the black line scanning depending on the time required by the optical response characteristic of different liquid crystal material, and the present invention can not only provide adequate design flexibility, but can also eliminate thoroughly the phenomenon of images superposition and outlines blurring created by the "after image" of the prior art, so as to optimize the quality of the images displayed. Therefore, the present invention can indeed achieve the purpose and the effectiveness of simulating the CRT impulse type image display with LCD display.
  • the description above indicates all the features of the present invention superior to those of the prior art.
  • the method and device utilized by the present invention in simulating the CRT impulse type image display can indeed overcome and improve the drawbacks and limitations of the similar liquid crystal display of the prior art, it can save the extra cost and expense of the additional equipment and significantly improve its functions. Therefore, the method and device used by the present invention in simulating the CRT impulse type image display is indeed superior to those of the prior art.
  • the present invention does have the value of utilization in the industry, and it does contain novelty and inventive steps, and it is in conformity with the patent requirements.
EP04013037A 2004-06-02 2004-06-02 Verfahren und Vorrichtung zur Simulation der CRT-typischen Impuls-Bilddarstellung Withdrawn EP1603106A1 (de)

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US20010003448A1 (en) * 1999-12-10 2001-06-14 Takashi Nose Driving process for liquid crystal display
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