EP1554651A4 - METHOD AND DEVICE FOR QUICK CROSS-THREAD INTERRUPTS IN A MULTITHREAD PROCESSOR - Google Patents
METHOD AND DEVICE FOR QUICK CROSS-THREAD INTERRUPTS IN A MULTITHREAD PROCESSORInfo
- Publication number
- EP1554651A4 EP1554651A4 EP03776329A EP03776329A EP1554651A4 EP 1554651 A4 EP1554651 A4 EP 1554651A4 EP 03776329 A EP03776329 A EP 03776329A EP 03776329 A EP03776329 A EP 03776329A EP 1554651 A4 EP1554651 A4 EP 1554651A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- high speed
- multithreaded processor
- speed cross
- thread interrupts
- interrupts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Bus Control (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP10010949A EP2306313A1 (en) | 2002-10-15 | 2003-10-10 | Method and apparatus for high speed cross-thread interrupts in a multithreaded processor |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US404175 | 1982-08-02 | ||
US41845502P | 2002-10-15 | 2002-10-15 | |
US418455P | 2002-10-15 | ||
US10/404,175 US6971103B2 (en) | 2002-10-15 | 2003-04-01 | Inter-thread communications using shared interrupt register |
PCT/US2003/032322 WO2004036354A2 (en) | 2002-10-15 | 2003-10-10 | Method and apparatus for high speed cross-thread interrupts in a multithreaded processor |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1554651A2 EP1554651A2 (en) | 2005-07-20 |
EP1554651A4 true EP1554651A4 (en) | 2007-10-31 |
Family
ID=32073254
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP03776329A Ceased EP1554651A4 (en) | 2002-10-15 | 2003-10-10 | METHOD AND DEVICE FOR QUICK CROSS-THREAD INTERRUPTS IN A MULTITHREAD PROCESSOR |
EP10010949A Ceased EP2306313A1 (en) | 2002-10-15 | 2003-10-10 | Method and apparatus for high speed cross-thread interrupts in a multithreaded processor |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP10010949A Ceased EP2306313A1 (en) | 2002-10-15 | 2003-10-10 | Method and apparatus for high speed cross-thread interrupts in a multithreaded processor |
Country Status (6)
Country | Link |
---|---|
US (1) | US6971103B2 (ko) |
EP (2) | EP1554651A4 (ko) |
JP (1) | JP2006503385A (ko) |
KR (1) | KR101002911B1 (ko) |
AU (1) | AU2003284098A1 (ko) |
WO (1) | WO2004036354A2 (ko) |
Families Citing this family (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7546444B1 (en) | 1999-09-01 | 2009-06-09 | Intel Corporation | Register set used in multithreaded parallel processor architecture |
US7681018B2 (en) * | 2000-08-31 | 2010-03-16 | Intel Corporation | Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set |
US7437724B2 (en) * | 2002-04-03 | 2008-10-14 | Intel Corporation | Registers for data transfers |
US7334086B2 (en) | 2002-10-08 | 2008-02-19 | Rmi Corporation | Advanced processor with system on a chip interconnect technology |
US8037224B2 (en) | 2002-10-08 | 2011-10-11 | Netlogic Microsystems, Inc. | Delegating network processor operations to star topology serial bus interfaces |
US20050033889A1 (en) * | 2002-10-08 | 2005-02-10 | Hass David T. | Advanced processor with interrupt delivery mechanism for multi-threaded multi-CPU system on a chip |
US7496915B2 (en) * | 2003-04-24 | 2009-02-24 | International Business Machines Corporation | Dynamic switching of multithreaded processor between single threaded and simultaneous multithreaded modes |
US7711931B2 (en) * | 2003-08-28 | 2010-05-04 | Mips Technologies, Inc. | Synchronized storage providing multiple synchronization semantics |
US7849297B2 (en) * | 2003-08-28 | 2010-12-07 | Mips Technologies, Inc. | Software emulation of directed exceptions in a multithreading processor |
US20050050305A1 (en) * | 2003-08-28 | 2005-03-03 | Kissell Kevin D. | Integrated mechanism for suspension and deallocation of computational threads of execution in a processor |
US9032404B2 (en) * | 2003-08-28 | 2015-05-12 | Mips Technologies, Inc. | Preemptive multitasking employing software emulation of directed exceptions in a multithreading processor |
US7870553B2 (en) * | 2003-08-28 | 2011-01-11 | Mips Technologies, Inc. | Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts |
US7376954B2 (en) * | 2003-08-28 | 2008-05-20 | Mips Technologies, Inc. | Mechanisms for assuring quality of service for programs executing on a multithreaded processor |
US7836450B2 (en) * | 2003-08-28 | 2010-11-16 | Mips Technologies, Inc. | Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts |
JP4818919B2 (ja) * | 2003-08-28 | 2011-11-16 | ミップス テクノロジーズ インコーポレイテッド | プロセッサ内での実行の計算スレッドを一時停止して割り当て解除するための統合されたメカニズム |
US7594089B2 (en) * | 2003-08-28 | 2009-09-22 | Mips Technologies, Inc. | Smart memory based synchronization controller for a multi-threaded multiprocessor SoC |
US7418585B2 (en) * | 2003-08-28 | 2008-08-26 | Mips Technologies, Inc. | Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts |
US20050086667A1 (en) * | 2003-09-30 | 2005-04-21 | Feng Jin | Symmetric Scheduling for parallel execution |
US7222064B1 (en) * | 2003-10-10 | 2007-05-22 | Unisys Corporation | Instruction processor emulation having inter-processor messaging accounting |
US7451454B2 (en) * | 2004-03-31 | 2008-11-11 | Intel Corporation | Event handling mechanism |
US8074051B2 (en) | 2004-04-07 | 2011-12-06 | Aspen Acquisition Corporation | Multithreaded processor with multiple concurrent pipelines per thread |
JP4501593B2 (ja) * | 2004-08-25 | 2010-07-14 | セイコーエプソン株式会社 | 画像処理を並列処理で実行する際の負荷の割り付け |
JP4556554B2 (ja) * | 2004-08-25 | 2010-10-06 | セイコーエプソン株式会社 | 画像処理を並列処理で実行する際の負荷の割り付け |
TW200625097A (en) * | 2004-11-17 | 2006-07-16 | Sandbridge Technologies Inc | Data file storing multiple date types with controlled data access |
US7657883B2 (en) * | 2005-02-04 | 2010-02-02 | Mips Technologies, Inc. | Instruction dispatch scheduler employing round-robin apparatus supporting multiple thread priorities for use in multithreading microprocessor |
US7631130B2 (en) * | 2005-02-04 | 2009-12-08 | Mips Technologies, Inc | Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor |
US7681014B2 (en) * | 2005-02-04 | 2010-03-16 | Mips Technologies, Inc. | Multithreading instruction scheduler employing thread group priorities |
US7490230B2 (en) | 2005-02-04 | 2009-02-10 | Mips Technologies, Inc. | Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor |
US7984281B2 (en) * | 2005-10-18 | 2011-07-19 | Qualcomm Incorporated | Shared interrupt controller for a multi-threaded processor |
US7702889B2 (en) * | 2005-10-18 | 2010-04-20 | Qualcomm Incorporated | Shared interrupt control method and system for a digital signal processor |
US7971205B2 (en) | 2005-12-01 | 2011-06-28 | International Business Machines Corporation | Handling of user mode thread using no context switch attribute to designate near interrupt disabled priority status |
KR20090078790A (ko) * | 2006-09-26 | 2009-07-20 | 샌드브리지 테크놀로지스, 인코포레이티드 | 무선 통신 시스템에서 매트릭스 변환 소프트웨어 구현을 위한 장치 및 방법 |
KR101545357B1 (ko) * | 2006-11-10 | 2015-08-18 | 퀄컴 인코포레이티드 | 파이프라인 컴퓨터 처리의 병렬화를 위한 방법 및 시스템 |
US7797514B2 (en) * | 2006-11-16 | 2010-09-14 | Texas Instruments Incorporated | Scalable multi-threaded sequencing/synchronizing processor architecture |
US8181185B2 (en) * | 2007-05-31 | 2012-05-15 | Intel Corporation | Filtering of performance monitoring information |
US8190864B1 (en) * | 2007-10-25 | 2012-05-29 | Oracle America, Inc. | APIC implementation for a highly-threaded x86 processor |
US20100241834A1 (en) * | 2007-11-05 | 2010-09-23 | Sandbridge Technologies, Inc. | Method of encoding using instruction field overloading |
US8539188B2 (en) * | 2008-01-30 | 2013-09-17 | Qualcomm Incorporated | Method for enabling multi-processor synchronization |
US7657683B2 (en) * | 2008-02-01 | 2010-02-02 | Redpine Signals, Inc. | Cross-thread interrupt controller for a multi-thread processor |
CN102027456A (zh) * | 2008-03-13 | 2011-04-20 | 阿斯奔收购公司 | 用于通过停用有效阵列实现功率节省的方法 |
US9032128B2 (en) * | 2008-04-28 | 2015-05-12 | Hewlett-Packard Development Company, L.P. | Method and system for generating and delivering inter-processor interrupts in a multi-core processor and in certain shared memory multi-processor systems |
KR20110050665A (ko) | 2008-08-06 | 2011-05-16 | 아스펜 액퀴지션 코포레이션 | 정지가능하고 재시작가능한 dma 엔진 |
ATE542177T1 (de) * | 2008-08-19 | 2012-02-15 | St Microelectronics Rousset | Weiterleitungsverfahren eines unterbrechungssignals direkt an eine virtuelle bearbeitungseinheit in einem system mit einer oder mehreren physischen bearbeitungseinheiten |
JP5173714B2 (ja) | 2008-09-30 | 2013-04-03 | ルネサスエレクトロニクス株式会社 | マルチスレッドプロセッサ及びその割り込み処理方法 |
JP5225010B2 (ja) * | 2008-10-14 | 2013-07-03 | キヤノン株式会社 | プロセッサ間通信方法、マルチプロセッサシステム及びプロセッサ。 |
US9026705B2 (en) * | 2012-08-09 | 2015-05-05 | Oracle International Corporation | Interrupt processing unit for preventing interrupt loss |
US10248463B2 (en) * | 2015-02-13 | 2019-04-02 | Honeywell International Inc. | Apparatus and method for managing a plurality of threads in an operating system |
US10069949B2 (en) | 2016-10-14 | 2018-09-04 | Honeywell International Inc. | System and method for enabling detection of messages having previously transited network devices in support of loop detection |
US10929178B1 (en) | 2017-06-28 | 2021-02-23 | Apple Inc. | Scheduling threads based on mask assignments for activities |
US10810086B2 (en) | 2017-10-19 | 2020-10-20 | Honeywell International Inc. | System and method for emulation of enhanced application module redundancy (EAM-R) |
US10783026B2 (en) | 2018-02-15 | 2020-09-22 | Honeywell International Inc. | Apparatus and method for detecting network problems on redundant token bus control network using traffic sensor |
US20230169163A1 (en) * | 2021-11-29 | 2023-06-01 | Nxp B.V. | Software isolation using event driven multi-threading |
CN117171102B (zh) * | 2023-09-07 | 2024-01-26 | 山东九州信泰信息科技股份有限公司 | 一种多线程无锁高速写文件的方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000070482A1 (en) * | 1999-05-14 | 2000-11-23 | Clearwater Networks, Inc. | Interrupt and exception handling for multi-streaming digital processors |
US20020083252A1 (en) * | 2000-12-27 | 2002-06-27 | International Business Machines Corporation | Technique for using shared resources on a multi-threaded processor |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5694603A (en) * | 1982-09-28 | 1997-12-02 | Reiffin; Martin G. | Computer memory product with preemptive multithreading software |
US4980824A (en) * | 1986-10-29 | 1990-12-25 | United Technologies Corporation | Event driven executive |
US5524250A (en) * | 1991-08-23 | 1996-06-04 | Silicon Graphics, Inc. | Central processing unit for processing a plurality of threads using dedicated general purpose registers and masque register for providing access to the registers |
US6243735B1 (en) * | 1997-09-01 | 2001-06-05 | Matsushita Electric Industrial Co., Ltd. | Microcontroller, data processing system and task switching control method |
US6567839B1 (en) * | 1997-10-23 | 2003-05-20 | International Business Machines Corporation | Thread switch control in a multithreaded processor system |
US6697935B1 (en) * | 1997-10-23 | 2004-02-24 | International Business Machines Corporation | Method and apparatus for selecting thread switch events in a multithreaded processor |
US6061710A (en) * | 1997-10-29 | 2000-05-09 | International Business Machines Corporation | Multithreaded processor incorporating a thread latch register for interrupt service new pending threads |
US6430593B1 (en) * | 1998-03-10 | 2002-08-06 | Motorola Inc. | Method, device and article of manufacture for efficient task scheduling in a multi-tasking preemptive priority-based real-time operating system |
US6687818B1 (en) * | 1999-07-28 | 2004-02-03 | Unisys Corporation | Method and apparatus for initiating execution of an application processor in a clustered multiprocessor system |
US6754690B2 (en) * | 1999-09-16 | 2004-06-22 | Honeywell, Inc. | Method for time partitioned application scheduling in a computer operating system |
US6496925B1 (en) * | 1999-12-09 | 2002-12-17 | Intel Corporation | Method and apparatus for processing an event occurrence within a multithreaded processor |
US6661794B1 (en) * | 1999-12-29 | 2003-12-09 | Intel Corporation | Method and apparatus for gigabit packet assignment for multithreaded packet processing |
US20010052053A1 (en) * | 2000-02-08 | 2001-12-13 | Mario Nemirovsky | Stream processing unit for a multi-streaming processor |
US20020103847A1 (en) * | 2001-02-01 | 2002-08-01 | Hanan Potash | Efficient mechanism for inter-thread communication within a multi-threaded computer system |
US20020144004A1 (en) * | 2001-03-29 | 2002-10-03 | Gaur Daniel R. | Driver having multiple deferred procedure calls for interrupt processing and method for interrupt processing |
-
2003
- 2003-04-01 US US10/404,175 patent/US6971103B2/en not_active Expired - Lifetime
- 2003-10-10 WO PCT/US2003/032322 patent/WO2004036354A2/en active Application Filing
- 2003-10-10 JP JP2005501397A patent/JP2006503385A/ja not_active Withdrawn
- 2003-10-10 AU AU2003284098A patent/AU2003284098A1/en not_active Abandoned
- 2003-10-10 EP EP03776329A patent/EP1554651A4/en not_active Ceased
- 2003-10-10 KR KR1020057006201A patent/KR101002911B1/ko active IP Right Grant
- 2003-10-10 EP EP10010949A patent/EP2306313A1/en not_active Ceased
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000070482A1 (en) * | 1999-05-14 | 2000-11-23 | Clearwater Networks, Inc. | Interrupt and exception handling for multi-streaming digital processors |
US20020083252A1 (en) * | 2000-12-27 | 2002-06-27 | International Business Machines Corporation | Technique for using shared resources on a multi-threaded processor |
Non-Patent Citations (1)
Title |
---|
INTEL CORPORATION: "8259A PROGRAMMABLE INTERRUPT CONTROLLER", INTERNET CITATION, December 1988 (1988-12-01), pages 1 - 24, XP002451563, Retrieved from the Internet <URL:http://pdos.csail.mit.edu/6.828/2005/readings/hardware/8259A.pdf> [retrieved on 20070820] * |
Also Published As
Publication number | Publication date |
---|---|
EP2306313A1 (en) | 2011-04-06 |
KR101002911B1 (ko) | 2010-12-20 |
WO2004036354A3 (en) | 2004-11-18 |
US20040073910A1 (en) | 2004-04-15 |
AU2003284098A1 (en) | 2004-05-04 |
KR20050050126A (ko) | 2005-05-27 |
US6971103B2 (en) | 2005-11-29 |
WO2004036354A2 (en) | 2004-04-29 |
EP1554651A2 (en) | 2005-07-20 |
JP2006503385A (ja) | 2006-01-26 |
AU2003284098A8 (en) | 2004-05-04 |
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Legal Events
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DAX | Request for extension of the european patent (deleted) | ||
A4 | Supplementary search report drawn up and despatched |
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Effective date: 20080125 |
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RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: ASPEN ACQUISITION CORPORATION |
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Owner name: QUALCOMM INCORPORATED |
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Effective date: 20161219 |