EP1554651A4 - METHOD AND DEVICE FOR QUICK CROSS-THREAD INTERRUPTS IN A MULTITHREAD PROCESSOR - Google Patents

METHOD AND DEVICE FOR QUICK CROSS-THREAD INTERRUPTS IN A MULTITHREAD PROCESSOR

Info

Publication number
EP1554651A4
EP1554651A4 EP03776329A EP03776329A EP1554651A4 EP 1554651 A4 EP1554651 A4 EP 1554651A4 EP 03776329 A EP03776329 A EP 03776329A EP 03776329 A EP03776329 A EP 03776329A EP 1554651 A4 EP1554651 A4 EP 1554651A4
Authority
EP
European Patent Office
Prior art keywords
high speed
multithreaded processor
speed cross
thread interrupts
interrupts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP03776329A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP1554651A2 (en
Inventor
Erdem Hokenek
Mayan Moudgill
Sean M Dorward
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Sandbridge Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandbridge Technologies Inc filed Critical Sandbridge Technologies Inc
Priority to EP10010949A priority Critical patent/EP2306313A1/en
Publication of EP1554651A2 publication Critical patent/EP1554651A2/en
Publication of EP1554651A4 publication Critical patent/EP1554651A4/en
Ceased legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4812Task transfer initiation or dispatching by interrupt, e.g. masked
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/30101Special purpose registers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Bus Control (AREA)
EP03776329A 2002-10-15 2003-10-10 METHOD AND DEVICE FOR QUICK CROSS-THREAD INTERRUPTS IN A MULTITHREAD PROCESSOR Ceased EP1554651A4 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP10010949A EP2306313A1 (en) 2002-10-15 2003-10-10 Method and apparatus for high speed cross-thread interrupts in a multithreaded processor

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US404175 1982-08-02
US41845502P 2002-10-15 2002-10-15
US418455P 2002-10-15
US10/404,175 US6971103B2 (en) 2002-10-15 2003-04-01 Inter-thread communications using shared interrupt register
PCT/US2003/032322 WO2004036354A2 (en) 2002-10-15 2003-10-10 Method and apparatus for high speed cross-thread interrupts in a multithreaded processor

Publications (2)

Publication Number Publication Date
EP1554651A2 EP1554651A2 (en) 2005-07-20
EP1554651A4 true EP1554651A4 (en) 2007-10-31

Family

ID=32073254

Family Applications (2)

Application Number Title Priority Date Filing Date
EP03776329A Ceased EP1554651A4 (en) 2002-10-15 2003-10-10 METHOD AND DEVICE FOR QUICK CROSS-THREAD INTERRUPTS IN A MULTITHREAD PROCESSOR
EP10010949A Ceased EP2306313A1 (en) 2002-10-15 2003-10-10 Method and apparatus for high speed cross-thread interrupts in a multithreaded processor

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP10010949A Ceased EP2306313A1 (en) 2002-10-15 2003-10-10 Method and apparatus for high speed cross-thread interrupts in a multithreaded processor

Country Status (6)

Country Link
US (1) US6971103B2 (ko)
EP (2) EP1554651A4 (ko)
JP (1) JP2006503385A (ko)
KR (1) KR101002911B1 (ko)
AU (1) AU2003284098A1 (ko)
WO (1) WO2004036354A2 (ko)

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US7836450B2 (en) * 2003-08-28 2010-11-16 Mips Technologies, Inc. Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
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US7984281B2 (en) * 2005-10-18 2011-07-19 Qualcomm Incorporated Shared interrupt controller for a multi-threaded processor
US7702889B2 (en) * 2005-10-18 2010-04-20 Qualcomm Incorporated Shared interrupt control method and system for a digital signal processor
US7971205B2 (en) 2005-12-01 2011-06-28 International Business Machines Corporation Handling of user mode thread using no context switch attribute to designate near interrupt disabled priority status
KR20090078790A (ko) * 2006-09-26 2009-07-20 샌드브리지 테크놀로지스, 인코포레이티드 무선 통신 시스템에서 매트릭스 변환 소프트웨어 구현을 위한 장치 및 방법
KR101545357B1 (ko) * 2006-11-10 2015-08-18 퀄컴 인코포레이티드 파이프라인 컴퓨터 처리의 병렬화를 위한 방법 및 시스템
US7797514B2 (en) * 2006-11-16 2010-09-14 Texas Instruments Incorporated Scalable multi-threaded sequencing/synchronizing processor architecture
US8181185B2 (en) * 2007-05-31 2012-05-15 Intel Corporation Filtering of performance monitoring information
US8190864B1 (en) * 2007-10-25 2012-05-29 Oracle America, Inc. APIC implementation for a highly-threaded x86 processor
US20100241834A1 (en) * 2007-11-05 2010-09-23 Sandbridge Technologies, Inc. Method of encoding using instruction field overloading
US8539188B2 (en) * 2008-01-30 2013-09-17 Qualcomm Incorporated Method for enabling multi-processor synchronization
US7657683B2 (en) * 2008-02-01 2010-02-02 Redpine Signals, Inc. Cross-thread interrupt controller for a multi-thread processor
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US9032128B2 (en) * 2008-04-28 2015-05-12 Hewlett-Packard Development Company, L.P. Method and system for generating and delivering inter-processor interrupts in a multi-core processor and in certain shared memory multi-processor systems
KR20110050665A (ko) 2008-08-06 2011-05-16 아스펜 액퀴지션 코포레이션 정지가능하고 재시작가능한 dma 엔진
ATE542177T1 (de) * 2008-08-19 2012-02-15 St Microelectronics Rousset Weiterleitungsverfahren eines unterbrechungssignals direkt an eine virtuelle bearbeitungseinheit in einem system mit einer oder mehreren physischen bearbeitungseinheiten
JP5173714B2 (ja) 2008-09-30 2013-04-03 ルネサスエレクトロニクス株式会社 マルチスレッドプロセッサ及びその割り込み処理方法
JP5225010B2 (ja) * 2008-10-14 2013-07-03 キヤノン株式会社 プロセッサ間通信方法、マルチプロセッサシステム及びプロセッサ。
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US10810086B2 (en) 2017-10-19 2020-10-20 Honeywell International Inc. System and method for emulation of enhanced application module redundancy (EAM-R)
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US20230169163A1 (en) * 2021-11-29 2023-06-01 Nxp B.V. Software isolation using event driven multi-threading
CN117171102B (zh) * 2023-09-07 2024-01-26 山东九州信泰信息科技股份有限公司 一种多线程无锁高速写文件的方法

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Also Published As

Publication number Publication date
EP2306313A1 (en) 2011-04-06
KR101002911B1 (ko) 2010-12-20
WO2004036354A3 (en) 2004-11-18
US20040073910A1 (en) 2004-04-15
AU2003284098A1 (en) 2004-05-04
KR20050050126A (ko) 2005-05-27
US6971103B2 (en) 2005-11-29
WO2004036354A2 (en) 2004-04-29
EP1554651A2 (en) 2005-07-20
JP2006503385A (ja) 2006-01-26
AU2003284098A8 (en) 2004-05-04

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