GB2410104B - Method and apparatus for assigning thread priority in a multi-threaded processor - Google Patents
Method and apparatus for assigning thread priority in a multi-threaded processorInfo
- Publication number
- GB2410104B GB2410104B GB0506377A GB0506377A GB2410104B GB 2410104 B GB2410104 B GB 2410104B GB 0506377 A GB0506377 A GB 0506377A GB 0506377 A GB0506377 A GB 0506377A GB 2410104 B GB2410104 B GB 2410104B
- Authority
- GB
- United Kingdom
- Prior art keywords
- threaded processor
- thread priority
- assigning thread
- assigning
- priority
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Advance Control (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/888,273 US7454600B2 (en) | 2001-06-22 | 2001-06-22 | Method and apparatus for assigning thread priority in a processor or the like |
GB0323746A GB2392751B (en) | 2001-06-22 | 2002-04-18 | Method and apparatus for assigning thread priority in a multi-threaded processor |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0506377D0 GB0506377D0 (en) | 2005-05-04 |
GB2410104A GB2410104A (en) | 2005-07-20 |
GB2410104B true GB2410104B (en) | 2005-11-02 |
Family
ID=34702502
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0506377A Expired - Fee Related GB2410104B (en) | 2001-06-22 | 2002-04-18 | Method and apparatus for assigning thread priority in a multi-threaded processor |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2410104B (en) |
-
2002
- 2002-04-18 GB GB0506377A patent/GB2410104B/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
GB2410104A (en) | 2005-07-20 |
GB0506377D0 (en) | 2005-05-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20180418 |