WO2004036354A3 - Method and apparatus for high speed cross-thread interrupts in a multithreaded processor - Google Patents

Method and apparatus for high speed cross-thread interrupts in a multithreaded processor Download PDF

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Publication number
WO2004036354A3
WO2004036354A3 PCT/US2003/032322 US0332322W WO2004036354A3 WO 2004036354 A3 WO2004036354 A3 WO 2004036354A3 US 0332322 W US0332322 W US 0332322W WO 2004036354 A3 WO2004036354 A3 WO 2004036354A3
Authority
WO
WIPO (PCT)
Prior art keywords
thread
cross
interrupt
destination
multithreaded processor
Prior art date
Application number
PCT/US2003/032322
Other languages
French (fr)
Other versions
WO2004036354A2 (en
Inventor
Erdem Hokenek
Mayan Moudgill
Sean M Dorward
Original Assignee
Sandbridge Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandbridge Technologies Inc filed Critical Sandbridge Technologies Inc
Priority to EP03776329A priority Critical patent/EP1554651A4/en
Priority to JP2005501397A priority patent/JP2006503385A/en
Priority to AU2003284098A priority patent/AU2003284098A1/en
Publication of WO2004036354A2 publication Critical patent/WO2004036354A2/en
Publication of WO2004036354A3 publication Critical patent/WO2004036354A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Bus Control (AREA)

Abstract

A multithreaded processor includes an interrupt controller for processing a cross-thread interrupt directed from a requesting thread (512) to a destination thread (212). The interrupt controller in an illustrative embodiment receives a request (512) for delivery of the cross-thread interrupt to the destination thread (212), determines whether the destination thread of the cross-thread interrupt is enabled for receipt of cross-thread interrupts, and utilizes a thread identifier (212) to control delivery of the cross-thread interrupt to the destination thread (212) if the destination thread is enabled for receipt of cross-thread interrupts. The requesting thread requests delivery of the cross-thread interrupt to the destination thread by setting a corresponding interrupt pending bit in a flag register (400) of the multithreaded processor. The destination thread is enabled for receipt of cross-thread interrupts if a corresponding enable bit is set in an enable register (300) of the multithreaded processor. The flag and enable registers may be implemented within the interrupt controller.
PCT/US2003/032322 2002-10-15 2003-10-10 Method and apparatus for high speed cross-thread interrupts in a multithreaded processor WO2004036354A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP03776329A EP1554651A4 (en) 2002-10-15 2003-10-10 Method and apparatus for high speed cross-thread interrupts in a multithreaded processor
JP2005501397A JP2006503385A (en) 2002-10-15 2003-10-10 Method and apparatus for fast inter-thread interrupts in a multi-thread processor
AU2003284098A AU2003284098A1 (en) 2002-10-15 2003-10-10 Method and apparatus for high speed cross-thread interrupts in a multithreaded processor

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US41845502P 2002-10-15 2002-10-15
US60/418,455 2002-10-15
US10/404,175 US6971103B2 (en) 2002-10-15 2003-04-01 Inter-thread communications using shared interrupt register
US10/404,175 2003-04-01

Publications (2)

Publication Number Publication Date
WO2004036354A2 WO2004036354A2 (en) 2004-04-29
WO2004036354A3 true WO2004036354A3 (en) 2004-11-18

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/032322 WO2004036354A2 (en) 2002-10-15 2003-10-10 Method and apparatus for high speed cross-thread interrupts in a multithreaded processor

Country Status (6)

Country Link
US (1) US6971103B2 (en)
EP (2) EP2306313A1 (en)
JP (1) JP2006503385A (en)
KR (1) KR101002911B1 (en)
AU (1) AU2003284098A1 (en)
WO (1) WO2004036354A2 (en)

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Also Published As

Publication number Publication date
KR101002911B1 (en) 2010-12-20
KR20050050126A (en) 2005-05-27
JP2006503385A (en) 2006-01-26
WO2004036354A2 (en) 2004-04-29
AU2003284098A1 (en) 2004-05-04
AU2003284098A8 (en) 2004-05-04
EP2306313A1 (en) 2011-04-06
US20040073910A1 (en) 2004-04-15
US6971103B2 (en) 2005-11-29
EP1554651A4 (en) 2007-10-31
EP1554651A2 (en) 2005-07-20

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