JPH09251388A - Interruption control system for information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the queuing processing due to the software and also to prevent occurrence of interruptions having no factors. SOLUTION: The interruption I/O INT 300 sent from an I/O controller is given to an interruption line latch 220 and an edge detector 230. The detector 230 outputs a mask OFF signal 2311 when it detects the edge of the INT 300. An interruption acknowledge register 250 outputs a mask ON signal 251 when it is accessed by an interruption handier. An interruption mask control part 240 controls the operation of an interruption mask part 210 by the mask ON and OFF signals. The part 210 decides whether the interruption latch output 221 received from the latch 220 should be outputted to a CPU as an interruption request signal 211 based on an ON/OFF signal 241 that is sent from the part 240.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control system for an information processing apparatus, and more particularly to an interrupt mask control system.

[0002]

2. Description of the Related Art In controlling interrupts, I /
The software (SW) had to control the factors such as waiting for the timing of clear write and interrupt mask release to the O controller for an appropriate time.
If this is not done, after issuing the factor clear write command to the I / O controller, the interrupt mask may be opened before the I / O controller negates the interrupt line. In this case, an interrupt request is generated, but since the interrupt factor has already been processed, it occurs as an interrupt with no factor.

A conventional technique of this type is disclosed in Japanese Patent Laid-Open No. 5-628.
No. 0, etc.

[0004]

In the conventional interrupt control, software must perform control such as waiting for an appropriate time for clearing the factor clear write to the I / O controller and interrupt mask release.

The reason is that if the above software control is not performed, the mask may be opened before the interrupt line is negated, and an interrupt that seems to have no cause may occur.

Therefore, the present invention improves the drawbacks of the conventional interrupt control system, controls the interrupt mask by the interrupt acknowledge register and the negate of the interrupt request signal from the controller, and reduces the waiting process by software. Another object is to suppress the occurrence of interrupts that do not cause a problem in interrupt processing.

[0007]

The present invention has an interrupt line latch means for latching an interrupt request signal from an I / O controller, and when the I / O controller negates the interrupt request signal, a falling edge of the signal is output. And has an edge detection unit that outputs a mask OFF signal,
The interrupt handler has an interrupt acknowledge register that is accessed to inform when the interrupt handler returns from interrupt processing, and ON / OFF of the interrupt mask is controlled by the mask OFF signal from the edge detector and the mask ON signal from the interrupt acknowledge register. It also has an interrupt mask control section for controlling the ON / OFF control, and an interrupt mask section for masking the output from the interrupt line latch by the ON / OFF control.

In the present invention, the interrupt mask section determines whether to output the output from the latch of the interrupt line to the CPU as an interrupt request signal to the CPU according to the ON / OFF signal provided from the interrupt mask control section. To do.

[0009]

According to the present invention, by accessing the interrupt acknowledge register from software and controlling ON / OFF of the interrupt mask by negating the interrupt request signal from the I / O controller, it is possible to eliminate the cause of the software. It is not necessary to wait until the interrupt mask is released, and it is possible to further suppress the generation of interrupts that have no cause.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an information processing device including an interrupt control device to which the present invention is applied. A CPU / host controller 100 and an interrupt controller 11 are shown in FIG.
0, I / O controller A 120, and I / O controller B 130.

An interrupt request signal I / O output from the I / O controller A120 or I / O controller B130
The O INTA 121 and the I / O INTB 131 are given to the interrupt controller 110, controlled by the interrupt controller, and given to the CPU as an interrupt INT 111.

FIG. 2 is a block diagram of an interrupt control system according to an embodiment, which corresponds to the interrupt controller 110 in FIG.

Interrupt I / O from I / O controller
INT 300 is provided to interrupt line latch 220 and edge detector 230. The edge detector 230 is
Mask OFF when the edge of OINT300 is detected
The signal 231 is output.

The interrupt acknowledge register 250 is
Mask ON when accessed from interrupt handler
The signal 251 is output. Interrupt mask control unit 240
Controls the operation of the interrupt mask section 210 by the mask ON signal 251 and the mask OFF signal 231. The interrupt mask unit 210 outputs the interrupt latch output 221 from the interrupt line latch 220 to the CPU by the ON / OFF signal 241 given from the interrupt mask control unit 240.
It is determined whether or not to output to the CPU as the interrupt request signal 211 to the CPU.

FIG. 3 shows a timing chart in the case of using the embodiment of the present invention to generate an interrupt from the I / O controller and cut the cause.

Interrupt from I / O controller (A)
Is asserted at time a. At this time, the interrupt mask section is in the interrupt mask OFF state ((D) interrupt mask section) because the mask OFF signal (B) is asserted and the mask ON signal (C) is negated. Therefore, the interrupt (A) from the I / O controller is notified to the interrupt request (E) to the CPU.

At time b, the mask acknowledge signal (C) is asserted and the mask disable signal (B) is negated by accessing the interrupt acknowledge register by the process in the software interrupt handler.

At time c, software requests the I / O controller, which has generated the interrupt request, to cut off the factor. However, the software cannot know the time from the issuance of the interrupt factor reaping request to the actual withdrawal of the interrupt (A) request from the I / O controller.

At time d, the interrupt (A) request from the I / O controller is negated. At this time, the edge detection unit detects this edge, outputs an interrupt mask OFF signal to the interrupt mask control unit, and the interrupt mask control unit turns off the interrupt mask unit.

[0021]

According to the present invention, by controlling the interrupt mask at the falling edge of the interrupt line from the I / O controller, software controls the wait for the timing of clearing the interrupt factor and releasing the mask. It is not necessary, and it is possible to suppress the generation of interrupts without factors.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing apparatus including an interrupt control system according to an embodiment of the present invention.

FIG. 2 is a block diagram of an interrupt control system according to an embodiment of the present invention.

FIG. 3 is a timing diagram of interrupt mask control according to an embodiment of the present invention.

[Explanation of symbols]

100 CPU / Host Controller 110 Interrupt Controller 111 INT (Interrupt Request to CPU) 120 I / O Controller A 121 I / O INT A (I / O Controller A
130 I / O controller B 131 I / O INT B (I / O controller B)
210 interrupt mask section 211 interrupt request signal to CPU 220 interrupt signal latch 221 interrupt latch output 230 edge detector 231 mask OFF signal 240 interrupt mask control section 241 ON / OFF signal 250 interrupt acknowledge register 251 mask ON signal Interrupt from 300 I / O controller

Claims (3)

[Claims] 1. An interrupt line latch comprising: an interrupt line latched from an I / O controller; an edge sensing part for a falling edge of the interrupt line; an interrupt mask part for an interrupt line; an interrupt mask control part; and an interrupt acknowledge register. An interrupt control method for an information processing apparatus, wherein the mask control unit turns on the interrupt mask by accessing the acknowledge register, and turns off the mask when the edge sensing unit senses the falling edge of the interrupt line. 2. The O supplied from the interrupt mask controller
2. The information processing apparatus according to claim 1, wherein the interrupt mask unit determines whether to output the output from the latch of the interrupt line to the CPU as an interrupt request signal to the CPU according to the N / OFF signal. Interrupt control method. 3. The interrupt control system for an information processing apparatus according to claim 1, wherein interrupt request signals output from a plurality of I / O controllers are input.