Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30003—Arrangements for executing specific machine instructions
  • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
  • G06F9/30043—LOAD or STORE instructions; Clear instruction
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
  • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Definitions

• the present invention relates to a computer system comprising: a processor; a multi-port memory, the multi-port memory being accessible by the processor.
• the present invention further relates to a method for transmitting a vector, in said computer system.
• the present invention relates to a computer program for implementing said method.
• Vector processing is a suitable technique for processing applications that have large computational demands.
• Vector processors provide high-level operations that work on vectors, i.e. linear arrays of numbers.
• Vector processors pipeline the operations on the individual elements of a vector.
• the pipeline includes not only the arithmetic operations, but also memory accesses and effective address calculations, i addition, most high-end vector processors allow multiple operations to be done at the same time, creating parallelism among the operations on different elements.
• Vector instructions have several important properties. First, the computations of each result are independent of the computations of previous results, allowing a very deep pipeline without generating any data hazards. Second, a vector instruction is equivalent to executing an entire loop, reducing the instruction bandwidth requirement.
• a vector memory system has a large datawidth, which allows retrieving a complete vector of data elements in one memory access using a single memory address. Subsequently, these data elements can be processed in parallel.
• several problems can occur when retrieving data from a vector memory system.
• the problem of vector alignment is related to reading from a vector memory system data that cross vector boundaries, hi that case the data can be retrieved by requesting the contents of two memory addresses, i.e. two vectors, and subsequently transfer the requested data to a new vector.
• the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for vector processing.
• a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register.
• a subset of elements is selected from the first register and the second register.
• the elements from the subset are then replicated into the elements in the third register in a particular order suitable for subsequent vector processing.
• An object of the invention is to provide an improved method for vector alignment and ordering of vector elements, resulting in a better performance of vector processors.
• This object is achieved with a method for transmitting a vector, characterized in that the method comprises the steps of: passing a base memory address to an address configuration means; defining a set of memory addresses by the address configuration means using the base memory address and a configuration instruction for configuring the address configuration means; transmitting the vector to/from the multi-port memory using the set of memory addresses.
• the method allows transmitting a complete vector to or from a multi-port memory, using a single base memory address.
• the data elements of a vector can be transmitted to or from arbitrary positions within the memory, improving flexibility and avoiding problems related to vector alignment and ordering of vector elements.
• the use of a multi-port memory in combination with said address configuration means reduces the instruction width.
• a complete vector can be transmitted using a single base memory address, whereas otherwise each memory address used by the multi-port memory should be present in the instruction. For certain types of processors, such as very large instruction word processors, reducing the code size is an important issue.
• a computer system is characterized in that the computer system further comprises an address configuration means, wherein the address configuration means is conceived to define a set of memory addresses using a base memory address and a configuration instruction for configuring the address configuration means, and wherein the multi-port memory is conceived to use the set of memory addresses.
• the address configuration means is conceived to define a set of memory addresses using a base memory address and a configuration instruction for configuring the address configuration means
• the multi-port memory is conceived to use the set of memory addresses.
• Complete vectors can be transmitted to or from the multi-port memory using one base memory address, which reduces memory overhead and increases the performance of the computer system.
• the address configuration means comprises: a plurality of register files arranged to be configured by the configuration instruction, and a plurality of address calculation units for calculating the set of memory addresses; the register files are accessible by the address calculation units; the address calculation units are coupled to the multi-port memory.
• the configuration instruction configures the plurality of register files, and these register files can hold this configuration until the next configuration instruction is executed. In between, this configuration can be used repeatedly, for example during execution of a loop of instructions.
• An embodiment of the computer system according to the invention is characterized in that the configuration instruction comprises a set of offsets, each offset in combination with the base memory address defining a second memory address.
• the set of offsets can be directly loaded in the plurality of register files and used by the plurality of address calculation units, improving the performance of the address configuration means.
• Fig. 1 shows a schematic diagram of a computer system according to the invention.
• Fig. 2 shows a schematic diagram of a memory system having a multi-port memory and an address configuration means.
• Fig. 1 shows a block diagram of a computer system comprising a processor PROC, an address configuration unit ACU, a multi-port memory MEM and a system bus SB.
• the processor PROC, the address configuration unit ACU and the multi-port memory MEM are coupled via the system bus SB.
• the processor PROC may issue operations to access the multi-port memory MEM in order to read or write a vector with data elements.
• the address configuration unit ACU Prior to reading or writing a set of data elements from the multi-port memory MEM, the address configuration unit ACU should be configured by means of a configuration instruction, issued by the processor PROC.
• the configuration instruction configures the address configuration unit ACU so that it is capable of calculating a set of memory addresses specific for the set of data elements to be retrieved from the multi-port memory MEM, using a base memory address.
• the configuration of the address calculation unit ACU remains unchanged until a next configuration instruction is issued.
• the processor issues a read operation, comprising a base memory address, and the latter is sent to the address calculation unit ACU.
• the address calculation unit ACU calculates a set of memory addresses. These memory addresses are sent to the multi-port memory MEM via the system bus SB, followed by reading the data elements from the multi-port memory MEM. These data elements are sent as a single vector to the processor PROC and-used for further processing.
• a base memory address is sent to the address configuration unit ACU.
• the address configuration unit ACU calculates a set of memory addresses, which are sent to the multi-port memory MEM, via the system bus SB.
• the data elements are also sent to the multi-port memory MEM via the system bus SB.
• the data elements are written to the multi-port memory MEM.
• Fig. 2 shows a block diagram of a memory system MS, comprising a multi- port memory MEM and an embodiment of an address configuration unit ACU.
• the multi- port memory MEM comprises a RAM memory, four data input ports Datln, four address ports Addr and four data output ports DatOut.
• the address configuration unit ACU comprises an address port Addrln, four address calculation units AU, four register files RF and four data input ports Datln.
• the data inputs Datln are shared data input ports for both the address configuration unit ACU and the multi-port memory MEM.
• the address input port Addrln is coupled to the address calculation units AU, and the address calculation units AU are coupled to their corresponding address port Addr of the multi-port memory MEM.
• the data input ports Datln are coupled to the register files RF.
• the register files RF are accessible by the address calculation units AU.
• the multi-port memory MEM supports commands for reading and writing of data.
• data can be read from the RAM memory via the data output ports DatOut.
• the four data elements read from the data output ports DatOut can be combined into one vector.
• a set of four data elements can be written to the multi-port memory, via the data input ports Datln and using the address ports Addr for memory addressing.
• the address configuration units ACU support a configuration instruction, which specifies a set of offsets relative to a base memory address.
• a configuration instruction which specifies a set of offsets relative to a base memory address.
• an offset value is written to each of the register files RF, via the corresponding data input port Datln.
• the address calculation units AU fetch the offset value from their corresponding register file RF and store this value internally.
• the processor PROC issues a read operation to the memory system MS, abase memory address is provided at the address port Addrln.
• the address calculation units AU take the value of the base memory address from the address input port Addrln and add their corresponding offset value.
• the address calculation units AU send the resulting set of memory addresses to the corresponding address ports Addr, and subsequently a read command is issued to the multi-port memory MEM.
• the resulting set of data elements is provided at the data output ports DatOut of the multi-port memory MEM.
• the processor PROC may also issue a write operation to the memory system MS in order to write a set of data elements to the RAM memory.
• the address port Addrln receives a base memory address.
• the address calculation units AU calculate a set of memory addresses, using the base memory address and their corresponding offset value.
• the resulting set of memory addresses is sent to the corresponding address ports Addr of the multi-port memory MEM.
• the data elements are sent to the data input ports Datln of the multi-port memory MEM. Subsequently, a write command is issued to the multi-port memory MEM and the data elements are written to the RAM memory.
• the configuration instruction may comprise a set of commands issued to the address configuration units AU for calculating a set of offsets.
• the set of offsets received by the register files RF will be such that in combination with a base memory address the address calculation units AU are capable of defining an arbitrary set of memory addresses.
• a set of data elements can be simultaneously written to or retrieved from the multi-port memory MEM.
• the memory system MS therefore behaves as a vector memory system, having the advantage of allowing retrieving a set of data elements from arbitrary memory locations using one base memory address.
• the memory system MS has the advantage that using one memory address, a set of data elements can be addressed instead of requiring a set of memory addresses from an external source.
• the instruction width can be reduced, which is especially of interest for very large instruction word processors, where reduction of code size is an important issue.

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• Engineering & Computer Science (AREA)
• Software Systems (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Complex Calculations (AREA)
• Executing Machine-Instructions (AREA)

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• 2003
  • 2003-07-10 EP EP03741006A patent/EP1527385A1/de not_active Withdrawn
  • 2003-07-10 AU AU2003281792A patent/AU2003281792A1/en not_active Abandoned
  • 2003-07-10 JP JP2004525660A patent/JP2005534120A/ja active Pending
  • 2003-07-10 CN CN 03817860 patent/CN1672128A/zh active Pending
  • 2003-07-10 WO PCT/IB2003/003150 patent/WO2004013752A1/en not_active Ceased

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