AU2003281792A1 - Method and apparatus for accessing multiple vector elements in parallel - Google Patents
Method and apparatus for accessing multiple vector elements in parallelInfo
- Publication number
- AU2003281792A1 AU2003281792A1 AU2003281792A AU2003281792A AU2003281792A1 AU 2003281792 A1 AU2003281792 A1 AU 2003281792A1 AU 2003281792 A AU2003281792 A AU 2003281792A AU 2003281792 A AU2003281792 A AU 2003281792A AU 2003281792 A1 AU2003281792 A1 AU 2003281792A1
- Authority
- AU
- Australia
- Prior art keywords
- parallel
- vector elements
- accessing multiple
- multiple vector
- accessing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02078074.8 | 2002-07-26 | ||
EP02078074 | 2002-07-26 | ||
PCT/IB2003/003150 WO2004013752A1 (en) | 2002-07-26 | 2003-07-10 | Method and apparatus for accessing multiple vector elements in parallel |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2003281792A1 true AU2003281792A1 (en) | 2004-02-23 |
Family
ID=31197898
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2003281792A Abandoned AU2003281792A1 (en) | 2002-07-26 | 2003-07-10 | Method and apparatus for accessing multiple vector elements in parallel |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1527385A1 (en) |
JP (1) | JP2005534120A (en) |
CN (1) | CN1672128A (en) |
AU (1) | AU2003281792A1 (en) |
WO (1) | WO2004013752A1 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100349122C (en) * | 2005-08-19 | 2007-11-14 | 华为技术有限公司 | Method for realizing data packet sequencing for multi engine paralled processor |
CN100417142C (en) * | 2005-12-22 | 2008-09-03 | 华为技术有限公司 | Method for average distributing interface flow at multi network processor engines |
JP2009527188A (en) | 2006-02-15 | 2009-07-23 | トムソン ライセンシング | Preview film for nonlinear digital editing |
US9021233B2 (en) * | 2011-09-28 | 2015-04-28 | Arm Limited | Interleaving data accesses issued in response to vector access instructions |
CN102930008B (en) * | 2012-10-29 | 2015-10-07 | 无锡江南计算技术研究所 | Vector look-up method |
CN107729990B (en) * | 2017-07-20 | 2021-06-08 | 上海寒武纪信息科技有限公司 | Apparatus and method for performing forward operations in support of discrete data representations |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01265347A (en) * | 1988-04-18 | 1989-10-23 | Matsushita Electric Ind Co Ltd | Address generating device |
JPH0728786A (en) * | 1993-07-15 | 1995-01-31 | Hitachi Ltd | Vector processor |
US6463518B1 (en) * | 2000-06-19 | 2002-10-08 | Philips Electronics No. America Corp. | Generation of memory addresses for accessing a memory utilizing scheme registers |
-
2003
- 2003-07-10 WO PCT/IB2003/003150 patent/WO2004013752A1/en active Application Filing
- 2003-07-10 JP JP2004525660A patent/JP2005534120A/en active Pending
- 2003-07-10 EP EP03741006A patent/EP1527385A1/en not_active Withdrawn
- 2003-07-10 AU AU2003281792A patent/AU2003281792A1/en not_active Abandoned
- 2003-07-10 CN CN 03817860 patent/CN1672128A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
JP2005534120A (en) | 2005-11-10 |
WO2004013752A1 (en) | 2004-02-12 |
CN1672128A (en) | 2005-09-21 |
EP1527385A1 (en) | 2005-05-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK6 | Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase |