EP1523829A4 - Verfahren und einrichtung zur effiziente pipeline verarbeitung von paketen - Google Patents

Verfahren und einrichtung zur effiziente pipeline verarbeitung von paketen

Info

Publication number
EP1523829A4
EP1523829A4 EP03726675A EP03726675A EP1523829A4 EP 1523829 A4 EP1523829 A4 EP 1523829A4 EP 03726675 A EP03726675 A EP 03726675A EP 03726675 A EP03726675 A EP 03726675A EP 1523829 A4 EP1523829 A4 EP 1523829A4
Authority
EP
European Patent Office
Prior art keywords
packages
pipeline processing
efficient pipeline
efficient
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03726675A
Other languages
English (en)
French (fr)
Other versions
EP1523829A2 (de
Inventor
Koen Deforche
Geert Verbruggen
Coster Luc De
Johan Wouters
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Transwitch Corp
Original Assignee
Transwitch Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Transwitch Corp filed Critical Transwitch Corp
Publication of EP1523829A2 publication Critical patent/EP1523829A2/de
Publication of EP1523829A4 publication Critical patent/EP1523829A4/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3072—Packet splitting
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3063—Pipelined operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
EP03726675A 2002-04-26 2003-04-25 Verfahren und einrichtung zur effiziente pipeline verarbeitung von paketen Withdrawn EP1523829A4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GBGB0209670.9A GB0209670D0 (en) 2002-04-26 2002-04-26 Efficient packet processing pipelining device and method
GB0209670 2002-04-26
PCT/US2003/014259 WO2003091857A2 (en) 2002-04-26 2003-04-25 Efficient packet processing pipeline device and method

Publications (2)

Publication Number Publication Date
EP1523829A2 EP1523829A2 (de) 2005-04-20
EP1523829A4 true EP1523829A4 (de) 2007-12-19

Family

ID=9935632

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03726675A Withdrawn EP1523829A4 (de) 2002-04-26 2003-04-25 Verfahren und einrichtung zur effiziente pipeline verarbeitung von paketen

Country Status (5)

Country Link
EP (1) EP1523829A4 (de)
CN (1) CN100450050C (de)
AU (1) AU2003228900A1 (de)
GB (1) GB0209670D0 (de)
WO (1) WO2003091857A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130215897A1 (en) * 2010-07-26 2013-08-22 David Warren Mitigation of detected patterns in a network device
WO2018188738A1 (en) * 2017-04-11 2018-10-18 NEC Laboratories Europe GmbH Packet handling method and apparatus for network service functions
CN113364685B (zh) * 2021-05-17 2023-03-14 中国人民解放军国防科技大学 一种分布式mac表项处理装置和方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755986A (en) * 1985-09-13 1988-07-05 Nec Corporation Packet switching system
US4899333A (en) * 1988-03-31 1990-02-06 American Telephone And Telegraph Company At&T Bell Laboratories Architecture of the control of a high performance packet switching distribution network
US5341369A (en) * 1992-02-11 1994-08-23 Vitesse Semiconductor Corp. Multichannel self-routing packet switching network architecture
WO1999031580A1 (en) * 1997-12-16 1999-06-24 Intel Corporation Processor having multiple program counters and trace buffers outside an execution pipeline
WO2000068780A2 (en) * 1999-05-11 2000-11-16 Sun Microsystems, Inc. Thread switch logic in a multiple-thread processor
WO2001048606A2 (en) * 1999-12-28 2001-07-05 Intel Corporation Allocation of data to threads in multi-threaded network processor
US6286027B1 (en) * 1998-11-30 2001-09-04 Lucent Technologies Inc. Two step thread creation with register renaming
WO2002005499A1 (en) * 2000-01-30 2002-01-17 Celox Networks, Inc. Device and method for packet formatting
JP2002116908A (ja) * 2000-10-05 2002-04-19 Arm Ltd ネイティブおよび非ネイティブの命令集合間相互呼び出し

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755986A (en) * 1985-09-13 1988-07-05 Nec Corporation Packet switching system
US4899333A (en) * 1988-03-31 1990-02-06 American Telephone And Telegraph Company At&T Bell Laboratories Architecture of the control of a high performance packet switching distribution network
US5341369A (en) * 1992-02-11 1994-08-23 Vitesse Semiconductor Corp. Multichannel self-routing packet switching network architecture
WO1999031580A1 (en) * 1997-12-16 1999-06-24 Intel Corporation Processor having multiple program counters and trace buffers outside an execution pipeline
US6286027B1 (en) * 1998-11-30 2001-09-04 Lucent Technologies Inc. Two step thread creation with register renaming
WO2000068780A2 (en) * 1999-05-11 2000-11-16 Sun Microsystems, Inc. Thread switch logic in a multiple-thread processor
WO2001048606A2 (en) * 1999-12-28 2001-07-05 Intel Corporation Allocation of data to threads in multi-threaded network processor
WO2002005499A1 (en) * 2000-01-30 2002-01-17 Celox Networks, Inc. Device and method for packet formatting
JP2002116908A (ja) * 2000-10-05 2002-04-19 Arm Ltd ネイティブおよび非ネイティブの命令集合間相互呼び出し
US20020108103A1 (en) * 2000-10-05 2002-08-08 Nevill Edward Colles Intercalling between native and non-native instruction sets

Also Published As

Publication number Publication date
EP1523829A2 (de) 2005-04-20
CN1663188A (zh) 2005-08-31
WO2003091857A3 (en) 2003-12-11
CN100450050C (zh) 2009-01-07
AU2003228900A1 (en) 2003-11-10
WO2003091857A2 (en) 2003-11-06
WO2003091857A9 (en) 2007-12-13
AU2003228900A8 (en) 2003-11-10
GB0209670D0 (en) 2002-06-05

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Legal Events

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Ipc: H04L 12/56 20060101ALI20070907BHEP

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A4 Supplementary search report drawn up and despatched

Effective date: 20071119

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