WO2002005499A1 - Device and method for packet formatting - Google Patents
Device and method for packet formatting Download PDFInfo
- Publication number
- WO2002005499A1 WO2002005499A1 PCT/US2001/000908 US0100908W WO0205499A1 WO 2002005499 A1 WO2002005499 A1 WO 2002005499A1 US 0100908 W US0100908 W US 0100908W WO 0205499 A1 WO0205499 A1 WO 0205499A1
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- data
- cell
- stream
- reformatting
- packet
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5614—User Network Interface
- H04L2012/5618—Bridges, gateways [GW] or interworking units [IWU]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5665—Interaction of ATM with other protocols
- H04L2012/5667—IP over ATM
Definitions
- the present invention relates to the field of high speed data packet processing for network systems, and in particular, to reformatting data packets for use with different communication protocols.
- the Internet provides a connection of different kinds of networks for communication, each network of which may be comprised of separate computers itself. However, each of these individual networks may communicate using different communication protocols relating to data packet formatting as well as other parameters. As a result, in order to transfer data packets over the Internet, these packets must undergo many transformations to make them compatible with the networks through which they are being transmitted. For example, data packets may undergo fragmentation in order to accommodate the different maximum size requirements of these networks. This fragmentation may include the insertion of headers into each fragmented portion, as well as providing recalculation to ensure the integrity of the data packets (e.g., checksum recalculations) .
- data traffic e.g., a stream of data packets
- ATM Asynchronous Transfer Mode
- TCP Transmission Control Protocol
- IP Internet Protocol
- the present invention provides a device and method for reformatting data packets, independent of any particular protocol, while providing scalability and speed.
- the invention provides packet formatting configured to convert data packets from one communication protocol to another as required by the various networks through which the data packet is communicated.
- the packet formatter provides this conversion by inserting, deleting and replacing specific data bytes in the data packets.
- the ability to convert packets is obtained by creating within the packet formatter a repository of configurable microcode which can be invoked in a programmable sequence by a control data stream. Therefore, the packet formatter can format packets to and from any protocol set presently known or which may be developed in the future, and is not limited to a specific set of protocols. Additionally, the packet formatter provides for rearranging data bytes within data packets . Therefore, the invention provides high speed operation that is not only scalable for even higher speed operation, but that is highly adaptable because of its communication protocol independence .
- the formatter of the present invention receives two data streams, one data cell stream and one control data stream. These data streams provide the information and data needed for the formatter to convert and reformat a data packet .
- the data cell stream is comprised of data packets which arrive as consecutive cells and the control data stream is comprised of control packets and/or data packets, which also arrive as consecutive cells.
- the communication protocol information and associated formatting information is provided at the inputs of the formatter by the control data stream.
- the identification of this information which is needed for converting the data packets is preferably provided by packet identification as described in co-pending U.S. patent application entitled "Device and Method For Packet Inspection" and having serial no. 09/494,235 and a filing date of January 30, 2000, which is incorporated herein by reference.
- any external control stream that provides the necessary information for reformatting can be used by the present invention.
- the formatter inputs and writes data words from both the data cell stream and the control data stream into a set of selectors.
- the formatter then selectively determines which specific data bytes from the selectors are used to form a new data word for assembling with other data words into a reformatted data packet.
- the formatter has flexibility in processing a continuos stream of data having varied communication protocols.
- the formatter extracts appropriate protocol conversion information from the control data stream to determine the specific microcode needed to process and reformat the given data packet. This protocol conversion information is used by a microcode flow controller to reformat specific bytes of the data stream.
- a device for reformatting data cell packets using an external control stream comprising an input configured to receive the data cell packets and the external control stream in parallel, a plurality of selectors for selecting cell bytes of the data cell packets and cell bytes of the control data cell stream for reformatting using machine microcode (the starting address for the specific microcode instructions selected for processing is determined by information from the external control stream) , and an output for providing the reformatted data packets from the selectors .
- the plurality of selectors may be configured in parallel relation to each other. Further, the device may be configured wherein the selector inserts, deletes, replaces or rearranges data bytes for reformatting the data cell packets.
- the device may be further configured wherein the selector comprises at least one storage area configured for writing and reading cell bytes. Further, the device may comprise a packet start indicator for determining the start of a new data packet .
- the external control stream may comprise control information for the data cell packets.
- a packet formatter for reformatting data packets having a stream of data cells using a control stream of data cells comprises an input for receiving the stream of data cells and the stream of control data cells, a plurality of memory units for storing data bytes of the data cells in parallel, a processor operatively connected to the memory units for selecting the data bytes of the data cells for reformatting using the stream of control data cells and merging the selected bytes into a reformatted data packet and an output for providing the reformatted data packets from the processor.
- the packet formatter may be configured wherein the processor further comprises a packet control for inserting, deleting, replacing and rearranging data bytes into data packets for reformatting.
- a method for reformatting data packets in a data stream using an external control stream comprises determining the format of the data packets using reformatting information from the external control stream, storing bytes of the data packets and external control cell stream in parallel, selecting data bytes for reformatting data packets using the reformatting information and reassembling the selected data bytes into the reformatted data packets .
- the method may further provide inserting data bytes for reformatting the data packets, deleting data bytes for reformatting the data packets, replacing data bytes for reformatting the data packets, or rearranging cells for reformatting the data packets.
- a data packet processor comprises a packet identifier for supplying a pair of data streams with one of said data streams being a stream of data cells and the other of said data streams being a stream of control cells, and a packet formatter connected to the packet identifier for receiving the pair of data streams in parallel .
- the packet formatter has at least one selector for reformatting the data cells into one of a plurality of predetermined data protocols .
- the data packet processor may further .comprise a microcode flow control coupled to the selector and to the data streams with the microcode flow control processing appropriate conversion microcode for supplying the appropriate read and write signals to instruct the selector for processing a particular data cell.
- the data packet processor may further comprise an extractor for extracting data cell formatting information from each control stream cell as it arrives from the packet identifier and a memory means connected between the extractor and the microcode flow control with the memory means containing the conversion microcode for access by the microcode flow controller.
- the selector may include a plurality of selectors connected in parallel for parallel processing of the data stream cells and the control stream cells and the data packet processor may further comprise a forward control for receiving the reformatted cells.
- the memory means may include machine code comprising the conversion microcode and wherein the microcode flow control includes a processor for processing the machine code.
- a data packet processor for reformatting a parallel stream of cells comprises a plurality of selectors for parallel processing of both of the streams to thereby reformat the streams .
- the data packet processor may further comprise a cell processor connected to the selectors for providing a plurality of reformatting instructions to the selectors .
- the data packet processor may . still further comprise an input and memory means connected to the cell processor for extracting the incoming cell format and supplying the cell processor with machine code for generating the reformatting instructions.
- the selectors may further receive each of the control and data cells, and wherein the processor supplies each of the selectors with a reformatting instruction identifying which portion of the data or control cell is to be forwarded into a reformatted cell.
- the data packet processor may further comprise a packet identifier connected to the input with the packet identifier providing the parallel streams of cells to the input .
- the data packet processor may also include a plurality of pairs of dual port memories with each pair of the memories being connected to an input to one of the selectors and holding the data and control cells for processing by the selectors, and further comprise a write control connected to the data packet processor input to receive both of the data stream and the control stream, with each of the write controls being connected to each of the .memories.
- a data packet processor for reformatting a plurality of parallel streams of cells wherein the data packet processor comprises a plurality of selectors for parallel processing of the streams to thereby reformat the streams into at least one reformatted stream.
- the data packet processor may further comprise a memory means connected to said plurality of selectors with the memory means containing conversion information for reformatting the plurality of parallel streams of cells into the at least one reformatted stream having a predetermined data protocol .
- Fig. 1 is a schematic block diagram of a packet formatter constructed according to the principles of one embodiment of the present invention
- Fig. 2 is a schematic block diagram of an extractor of the packet formatter in Fig. 1;
- Fig. 3 is a schematic block diagram of a microcode fetch unit of the packet formatter in Fig. 1;
- Fig. 4 is a schematic block diagram of a microcode flow controller of the packet formatter in Fig. 1;
- Fig. 5 is a schematic block diagram of a memory unit in a selector of the packet formatter in Fig. 1;
- Fig. 6 is a schematic block diagram of a write controller of the packet formatter in Fig. 1;
- Fig. 7 is a schematic block diagram of a read controller in a selector of the packet formatter in Fig. 1;
- Fig. 8 is a schematic block diagram of a forward controller of the packet formatter in Fig. 1;
- Fig. 9 is a schematic block diagram of a packet/cell flow controller of the packer formatter in Fig. 1;
- Fig. 10 is a block diagram showing packet formatting requirements of an incoming and outgoing data packet.
- Fig. 11 is a block diagram showing the process of the packet formatter in Fig. 1 when processing and reformatting the data packet of Fig 10;
- Fig. 12 is a block diagram showing the packet reformatting process of the packet formatter in Fig.l.
- a packet formatter according to a preferred embodiment of the present invention is shown in Fig. 1 and is indicated generally by reference character 100. As shown therein, two data streams arrive at the input to the packet formatter 100.
- a data cell stream 102 which is comprised of data packets that are provided as consecutive cells, and a control data stream • 104, which may be comprised of control and/or data packets that are also provided as consecutive cells.
- a control packet For every data packet, there is a corresponding control packet, although each control packet may correspond to more than one data packet . Additionally, multiple control cells may correspond to one data packet.
- the data stream comprises sixty-four byte cells, with each cell including eight words or windows of eight bytes each, which are preferably provided consecutively.
- information needed to process and reformat the data packets is included in the control data stream.
- the control data stream may be provided by other external sources that include information needed for processing and formatting information.
- machine microcode provided within the packet formatter is processed to reformat the data packets.
- the data formatter 100 essentially comprises an extractor unit 106, a microcode (MC) fetch unit 108, a data stream write controller 110, a control stream write controller 112, eight selectors 114 (each of which include a data memory unit 116, a control memory unit 118, and a read controller 120) , a packet/cell flow controller 122 and a microcode (MC) flow controller 124.
- MC microcode
- the write controllers 110 and 112 of the packet formatter 100 write data to each of the selectors 114.
- the extractor unit 106 extracts data packet information from the control data stream 104 for use by the MC fetch unit 108 and MC flow controller 124 to ensure that the proper microcode is provided by the microcode flow controller 120 to process the associated data packets in the data streams.
- the extractor unit 116 preferably includes a first in - first out (FIFO) controller 126, a start of packet monitor 128, a pipeline 130, a prefetch control register 132 and a start of packet active control 134.
- the control data stream 104 is received by the FIFO controller 126 of the extractor 106.
- the words of the control data stream 104 which as illustrated in this disclosure are eight bytes each, are written into the extractor 106 one word at every clock cycle.
- the start of packet monitor 128 determines whether the control data stream 104, and in particular, whether a word or window of that stream includes a start of packet (SOP) indication or flag indicating that the particular data word being transmitted is the start of a data packet.
- the prefetch control register 132 preferably acts as a latch to process the control information for that data packet when an SOP signal is detected. It should be noted that before a data word reaches the last four locations in the FIFO controller
- the prefetch control register 132 for the SOP indication and packet-formatting information is extracted out of it.
- the packet-formatting information of the control data packet is processed by the MC fetch unit 108 for use in determining and forwarding microcode instructions to process the data packets .
- the prefetch operation ensures that the time needed to load a microcode instruction into the MC flow controller 124 before the data at the extractor 104 inputs is to be processed, is met. Also, delay in processing time is reduced, if not eliminated.
- the information extracted is sent to the MC fetch unit 108 and the packet/cell flow controller 122, as signals.
- these signals preferably include the SOP to indicate the start of a new packet, a micro-code instruction pointer (MCIP) which identifies the instructions in a microcode (MC) table 136 to process and reformat the data packet, a new packet length signal for use in calculating when the end of the data packet will occur, and a block control bit signal for use by the write controllers 110 and 122, and the selectors 114 to determine where to read and write in the selector memory.
- MCIP micro-code instruction pointer
- MC microcode
- These signals are specifically provided from the prefetch routine to ensure that the MCIP is extracted from the control data stream 104 with enough time for the MCIP to be used as a lookup index in the MC table 136, with the corresponding microcode instruction loaded into the MC flow controller 124 for processing of the data packets.
- This prefetch feature provides the advantage of speed in processing because the MC flow controller 124 is not waiting for instructions (i.e., control signals) to process and reformat a particular data packet .
- a control word is forwarded to the pipeline 130 once the prefetched information is communicated to the MC fetch unit 108. It should be noted that if one SOP indicator immediately follows another SOP indicator in the extractor 106 before the first SOP indicator reaches the control stream write controller 112, it is stalled or held back to ensure that the SOP signal and other fields in the MC fetch unit 108 are not overwritten. Therefore, once the data word containing the SOP indicator exits the pipeline 130, the extractor 106 is ready to extract another SOP indicator for processing.
- the MC flow controller 124 will de-assert the read control data signal (read Ctrl data) , such that even if the extractor 106 has outputted a control data ready signal to the MC flow controller 124, indicating that control data is ready to process, the logical AND function as shown in Fig. 2 prevents the processing of the new data packet.
- the MC flow controller 124 will not assert the read control data signal until it is ready to process the new data packet .
- the SOP signal is sent to the start of packet monitor 128 to indicate that another start of packet signal cannot be asserted. This also prevents overwriting of previously generated instructions .
- the SOP signal is used to de-assert the start of packet active controller 134, which again activates the start of packet monitor 128 to monitor for SOP indications. Therefore, once the SOP data word has reached the last window in the pipeline 130, the microcode required to process the data streams is already encoded in the MC flow controller 124.
- the prefetch control register 132 and the start of packet active controller 134 provide the control signals to the MC fetch unit 108.
- the MC fetch unit 108 preferably comprises an address controller 138 (e.g., a multiplexer) and logic to provide the control signals.
- the asserted SOP signal selects the address controller 138 input to send the MCIP signal received from the prefetch control register 132 to the MC table 136 only when the packet/cell flow controller 122 asserts its get next instruction pointer (GNIP) , indicating that the MC flow controller 124 is ready to process the new data packet.
- GNIP next instruction pointer
- the MC instruction pointer passes through a microcode address register 140, which processes and provides the specific start address for retrieval from the MC table 136, which is sent to the MC flow controller 124.
- the specific start address points to specific machine microcode in the MC table 136 which provides for reformatting the data packet.
- the MC table 136 includes machine microcode instructions for processing and reformatting between many different communication protocols, including for example, communication protocols necessary for Internet communication.
- the machine microcode in the MC table 136 may include any instructions necessary to reformat data packets as is required, and is not limited to any specific reformatting instructions, but may accommodate new protocols that may be developed.
- the address controller 138 during normal operation, will be incremented by one with the current address +1 signal that is generated with each pass through the MC address register 140 by the adder. However, the MC flow controller 124 may not be ready for the next instruction or may need to jump to a non- consecutive microcode instruction address.
- the MC flow controller 124 can send a stall signal to the address controller 138, which causes the address controller 138 to output the current address signal, thereby maintaining the current microcode address instruction for the clock cycle. This signal also causes the MC active signal to be de-asserted so that any microcode sent to the MC flow controller 124 will be disregarded as not valid.
- the MC flow controller 124 can also assert a jump signal to the address controller 138 which will cause the jump address signal from the MC flow controller 124 to pass through the MC address register 138 and select a non-consecutive microcode instruction address in the MC table 136 (i.e., the current MCIP is updated) . Therefore, only when the MC active signal sent with the microcode (as shown in Figs. 1 and 3) are asserted, does the MC flow controller 124 process the microcode instruction.
- the MC flow controller 124 of the present invention preferably comprises a microcode (MC) cache table 142, a stall controller 144 and a microcode (MC) decoder 146 which provides microcode instructions.
- MC microcode
- Exhibit A is the preferred microcode instruction set for the packet formatter 100.
- the MC cache table 144 passes the microcode to the stall controller 144. In the event that the MC active signal is not asserted, indicating that the information being sent is not valid, the MC flow controller 124 will disregard the microcode. If the MC active signal is asserted, but the stall control 144 issues a stall signal (e.g., the microcode indicates that a data word should be written into a selector 114, but the data word is currently not available for writing) indicating that the MC flow controller 124 is not ready to process another microcode instruction, the MC cache table 142 holds the microcode instruction.
- a stall signal e.g., the microcode indicates that a data word should be written into a selector 114, but the data word is currently not available for writing
- the stall controller 144 will continue to assert the corresponding read control (ctrl) data and read data signals (from the microcode) in an attempt to continue processing the data bytes in the selectors 114. Once, the data is available for reading, the stall signal is de-asserted, the data bytes will be processed, and the packet formatting process resumes .
- the MC cache table 142 is preferably four words wide, which is needed to accommodate a stall operation (e.g., when extra processing time is needed by the MC fetch unit 108 because it is attached to a static read-only-memory (SRAM) and cannot stop processing signals immediately upon receiving the stall signal) .
- EOP end of packet
- the stall controller 144 If the stall controller 144 receives valid microcode (i.e., MC active signal asserted) it will send the read Ctrl data and read data signals to the extractor 106 and data stream 102, respectively, indicating that the data words of the control stream 104 can be forwarded to the control stream write controller 112 and the data words of the data stream 102 can be forwarded to the data stream write controller 110.
- the microcode instruction is also processed in the MC decoder 146 for providing control signals to the selectors 114.
- the microcode decoder 146 provides the control signals to the data stream write controller 110 and the control stream write controller 112 to initiate the write command to the selectors 114. This is provided by the CWriteMC and DWriteMC signals. Each of the write controllers 110 and 112 write their respective data word to all of the selectors 114 in parallel, with the data word stored in the data memory unit 114 and the control word stored in the control memory unit 116.
- the memory units are preferably dual port random access memories (DPRAMS) which allow for simultaneous read and write operation. To further provide added versatility and speed, as well as ensuring that data is not overwritten, each memory unit includes two blocks 148, each preferably eight bytes wide (the size of one word), as shown in Fig. 5.
- Each block is further preferably provided with a buffer area 150 and a loop area 152.
- the provision of multiple blocks provides pipelined operations between data packets (e.g., a new data packet to be written into the memory is received before data from a previous data packet is completely read out of the memory, and thereby avoids bytes from the new data packet being read into and corrupting the previous packet being reformatted) .
- data words can be written and read in parallel from different areas of the memory.
- words can be maintained in the buffer area 150 for a determined number of clock cycles provided by the MC flow controller 124.
- a fixed buffer area may be provided for inserting or replacing data from another source.
- buffer area 150 is provided to store bytes which will be repeated, for example, when used again in a new data packet, while the loop area 152 provides for small scale permutations within a portion of a data packet.
- the selection of the buffer area 150 is particularly useful, for example, in the case of fragmentation, wherein control data may have to be maintained for several data packets.
- data word alignment in the present invention is provided by processing one word in each clock cycle. Additionally, the control signals are clocked each cycle. Further, delays are provided in the various component parts of the packet formatter 100 to ensure proper data processing and integrity of that process.
- the MC flow controller 124 also sends out a block signal to control which memory block in each selector 114 the data word is written.
- the write controllers 110 and 112 are provided with a buffer area pointer control 160 and a loop area pointer control 162 which output the address to which the current data word should be written in the memory units of the selectors 114.
- the buffer area pointer 160 and loop area pointer 162 are reset. The microcode determines to which area data is written.
- the block signal is also provided through the write controllers 110 and 112 to select the block 148 in the memory unit.
- the write signals WriteMC provide the specific address location in the buffer area 150 or the loop area 152 of the memory unit to write the data.
- a write enable signal (WEN) is provided for indicating that the data word should be written into the address of the memory units of the selectors 114 as determined by the pointers 160 and 162.
- the MC flow controller 124 also sends out read control signals ReadMC 0 through ReadMC 7, and corresponding block signals to the read controllers 120 of the selectors, which signals provide for selecting the following: the data memory unit 116 or control memory unit 118, the block 148, the address of the word to be read and the address of the byte to be selected. This addressing is determined by the specific microcode provided by the MC fetch 108 from the MC table 136 to the MC flow controller 124. It should be noted that the read control signals are reset by the microcode flow controller 124 upon receiving an SOP signal.
- the read controller 120 is preferably provided with a read decoder 154 which processes the signals received from the MC flow control 124.
- the read decoder 154 provides a selector D_C output to select between either the data packet or control packet.
- a byte selector is also provided from the read decoder 154 to select the address of the word and byte in the selector 114 memory unit from where data is to be read.
- the decrement signal (deer) is processed through the read decoder 154 to a decrement unit 156 which provides a decrement signal (essentially a time to live (TTL) indication) to prevent the formatted packets from cycling through networks endlessly, for example, if routers to which the data packet is transmitted are busy.
- TTL time to live
- the selected byte is written into an FIFO in the forward control unit 158, as shown in Fig. 8. It should be noted that data words are not always written at each clock cycle. Further, more than one data word may be written at each clock cycle. Therefore, an asynchronous enqueue controller 166 is needed to provide the full eight byte data words, one full word at a time, though the FIFO, and to the synchronous dequeue controller 168 for merging as a reformatted assembled data packet. Therefore, the eight selected bytes are forwarded in parallel through the FIFO to the synchronous dequeue controller 168.
- a header checksum or CRC i.e., outgoing protocol is ATM
- the old checksum control 160, new checksum control 162 and checksum insertion control 164 provide for incremental header checksum calculations to be included with the reformatted data packet if necessary. This may be accomplished by using, for example, the incremental checksum procedure defined in RFC Standard 1624, entitled “Computation of the Internet Checksum via Incremental Update” (May 1994) .
- the packet/cell flow controller 122 of the present invention provides the GNIP signal based on the SOP signal and the length of the data packet, as provided from the new packet length signal of the prefetch control register 132 in the extractor 106.
- the packet/cell flow controller 122 calculates the length of a new data packet (using the new packet length signal from the extractor 106) and the length of the packet header and compares that total length to the maximum data cell size minus the cell header, each time a cell is processed.
- the near end of packet (NearEOP) signal is generated and sent to the MC flow controller 124 (this signal is pre- calculated and the NearEOP signal is generated based on the remaining packet length before the last cell is processed, which provides a Near EOP signal which can be used by the microcode decoder 146 for a conditional near end of packet jump) .
- This provides the MC flow controller 124 with an additional indication in the event that the microcode instructions are to be processed at a later time, for example, when a jump instruction is needed.
- the packet/cell flow controller 122 When an SOP signal is sent to the packet/cell flow controller 122 and the remaining cell size is less than the maximum cell size minus the cell header (i.e., the next cell is a new packet) or when the remaining cell size is less than the maximum cell size minus the cell header, and the WordCounter is equal to zero (decreases from 7 to zero if the cell size is 8 words) , the packet/cell flow controller 122 generates the end of packet (EOP) signal indicating that the cell is the last data cell in a given packet .
- the WordCounter provides for processing of the data stream in eight byte word cells.
- the GNIP signal is generated when the WordCounter is equal to four (i.e., there are 4 remaining words in the cell to process) and the EOP signal is asserted, indicating that the last cell in the data packet is going to be processed. This again accommodates for the possible delay of the MC fetch 108 due to the SRAM to which it is connected.
- the packet formatter 100 takes a data stream 102 and a control stream 104, which represents, for example, an incoming data packet that needs to be reformatted to the outgoing data packet because different protocols are required, and replaces or adds cell headers as needed, as well as inserts new data bytes as required.
- An example of the operation of the packet formatter is illustrated in Figs. 10- 12.
- Fig. 10 illustrates an example of the packet formatting changes required in the packet formatter 100 given the incoming packet and outgoing packet as shown. In this example, the incoming packet needs to be reformatted to the outgoing packet .
- the reformatting that must occur is as follows : the first word must be replaced with the new cell header and new PIE header (which may be proprietary protocol information or other reformatting and/or conversion information from an external source) ; then the PPP header must be attached followed by a new IP header; finally a new cell header must be placed in every eighth word of a cell .
- the new bytes to be inserted come from the control data stream 102.
- Fig. 11 shows the clock cycle and the results of each of the signals in the packet formatter 100 when processing the packets of Fig. 10. An asserted signal is represented by a "1" and a de-asserted signal is represented by a "0". In this example, the read and write operations for the control data are completed in the first three cycles, and the remaining cycles read and write data bytes .
- an eight byte word from each of the data stream 102 and control stream 104 are inputted into the data stream write controller 110 and the control stream write controller 112, respectively, when instructed by the microcode flow controller 124. These write controllers then write in parallel, a data word of each of their respective data cells to their respective memory units in each of the selectors 114.
- the read controllers 120 controlled by the MC flow controller 124 (which obtains its microcode instructions from information in the control stream 104, which was extracted from the control data stream 102 by the extractor 106 and processed in the MC fetch unit 108) then read specific bytes, as instructed by the MC flow controller 124, into the FIFO of the forward controller 158. This process continues until the required data bytes are merged and the data packet reassembled for communication with the new protocol .
- Exhibit B is an example of the C-code preferably used for generating the machine microcode for the MC table 136.
- Exhibit C is another example of a preferably used C-code for generating the machine microcode for the MC table 136.
- the packet formatter 100 may be configured to read in only specific bytes and write out one word at a time, which reduces the hardware complexity and memory requirements, but limits the flexibility of the packet formatter 100. Therefore, depending upon the specific application, the read and write functions may be modified. Additionally, the packet formatter 100 may process and merge more than two data cell streams. These modifications would merely require minor programming changes, including modifications of the microcode, and would not require any significant hardware changes.
- packet formatter 100 of the present invention has been described in detail only in the context of reformatting data packets for use in routing processes, the packet formatter may also be readily configured to accept different external control streams for processing in other non- networking applications and anywhere it is required to reformat data from one protocol to another.
- the present invention is not limited to the specific number of component parts as illustrated.
- the eight selectors 114 for processing the eight byte words, with eight words per data cell was selected because of the Internet application as illustrated. More selectors may be used as required or desired and the cell or word size that is processed also modified (e.g., bits). Additionally, changes to the size of the blocks in the memory units of the selectors 114 is also contemplated. This flexibility provides for the scaleability in speed of the invention.
- the various block representations as described herein represent hardware implementation of the invention, such as in chip architecture. Several of the chips or functions could be incorporated into a custom chip. Although not preferable, one or more of the functions performed in hardware could be implemented in software.
Abstract
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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AU2001229368A AU2001229368A1 (en) | 2000-01-30 | 2001-01-11 | Device and method for packet formatting |
EP01984134A EP1287652A1 (en) | 2000-01-30 | 2001-01-11 | Device and method for packet formatting |
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US49423600A | 2000-01-30 | 2000-01-30 | |
US09/494,236 | 2000-01-30 |
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EP (1) | EP1287652A1 (en) |
AU (1) | AU2001229368A1 (en) |
WO (1) | WO2002005499A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1523829A2 (en) * | 2002-04-26 | 2005-04-20 | Transwitch Corporation | Efficient packet processing pipeline device and method |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2019104688A1 (en) * | 2017-11-30 | 2019-06-06 | 深圳市柔宇科技有限公司 | Input data processing method for handwriting board, electronic device and storage medium |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0680179A1 (en) * | 1994-04-28 | 1995-11-02 | Hewlett-Packard Company | Multicasting apparatus |
EP0719065A1 (en) * | 1994-12-20 | 1996-06-26 | International Business Machines Corporation | Multipurpose packet switching node for a data communication network |
-
2001
- 2001-01-11 AU AU2001229368A patent/AU2001229368A1/en not_active Abandoned
- 2001-01-11 EP EP01984134A patent/EP1287652A1/en not_active Withdrawn
- 2001-01-11 WO PCT/US2001/000908 patent/WO2002005499A1/en not_active Application Discontinuation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0680179A1 (en) * | 1994-04-28 | 1995-11-02 | Hewlett-Packard Company | Multicasting apparatus |
EP0719065A1 (en) * | 1994-12-20 | 1996-06-26 | International Business Machines Corporation | Multipurpose packet switching node for a data communication network |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1523829A2 (en) * | 2002-04-26 | 2005-04-20 | Transwitch Corporation | Efficient packet processing pipeline device and method |
EP1523829A4 (en) * | 2002-04-26 | 2007-12-19 | Transwitch Corp | Efficient packet processing pipeline device and method |
Also Published As
Publication number | Publication date |
---|---|
AU2001229368A1 (en) | 2002-01-21 |
EP1287652A1 (en) | 2003-03-05 |
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