JP2002509412A - ATM cell processor - Google Patents

Abstract

(57) [Abstract] An ATM cell processor (10) has a backplane interface (11), a line interface (15), and various processing functions between both interfaces. The cells going to the line interface (15) are controlled by a queuing function (12) using an external cell memory via a controller (13) and using an external control memory via a controller (14). Cells from the backplane are identified and routed by the mapping function (16).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a processor for handling Asynchronous Transfer Mode (ATM) cells.

[0002]

[Prior art]

ATM technology supports many different services such as voice, frame relay, or circuit emulation. Also, the throughput rate is extremely high, on the order of several hundred thousand cells per second. The general approach is to provide various circuits that handle many of the required cell processing functions. For example, European Patent No. EP 614324 (Nippon) describes a circuit including a cell assembly / disassembly control circuit and a memory access control circuit. Such circuits are limited in their functionality and tend to be complex.

[0003]

[Object of the invention]

It is an object of the present invention to provide efficient handling of cells by a processor. Another object is to provide the processor with the flexibility to operate such that it can be used in different environments in a relatively simple configuration. Yet another object is to provide a cell processor that can be controlled in a comprehensive manner using relatively simple control circuits.

[0004]

[Summary of the Invention]

According to the present invention, there is provided an ATM cell processor comprising a line interface, a backplane interface, and processing means for identifying a cell based on its header and processing the identified cell. You. Thus, the processor can be flexibly integrated into systems having multiple cell streams.

In one embodiment, the line interface and the backplane interface are bidirectional. This provides excellent versatility for cell processing.

[0006] In one embodiment, the processing means has a mapping function. This makes it possible to map the received cell according to VPI / VCI. Preferably, the mapping function comprises means for changing the header of the cell according to the destination of the mapped cell. In one embodiment, the mapping function comprises means for adding an extra header to the cell for internal control signal transmission.

In another embodiment, the processing means further has a policing function for monitoring characteristics of the traffic. This allows for incorporation into systems connected to multiple client systems and is particularly useful for contract monitoring.

[0008] In still another embodiment, the cell processor has a queuing function connected between interfaces for controlling transfer of cells to the line interface. This provides for efficient cell traffic management.

In another embodiment, the queuing function comprises means for interfacing to a cell memory for storing a queue of cells and to a control memory for storing queuing parameter values. Have. This increases the flexibility of how cells are queued. This also provides simple queuing control.

[0010] In one embodiment, the queuing function is connected to a memory controller to interface to cells and control memory. Preferably, the queuing function has means for managing a path descriptor table in the control memory. In another embodiment, the queuing functions each have means for managing a queue descriptor table associated with an individual queue in the control memory.

In one embodiment, the cell processor further comprises a segmentation reassembly (SAR) interface for routing cells to an external segmentation reassembly (SAR) device. This allows an efficient connection between the cell processor and the control processor using cells for transmitting control signals. Preferably, the SAR interface is connected to the queuing function.

[0012] In one embodiment, the cell processor has a control processor interface for connection to a memory controller that allows for an initial setup configuration.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

The invention will be more clearly understood from the following description of several embodiments, which are merely illustrative of the invention, with reference to the accompanying drawings, in which:

FIG. 1 shows a cell processor 10 of the present invention. The processor 10
An integrated circuit for identification (ASIC), the application of which is the processing of ATM cells. Hereinafter, the main components of the ASIC 10 will be briefly described with reference to the overall signal flow in the processor. The cell transfer rate handled is 373K cells per second, which is a bit rate of 155 Mbps or more. ASIC10 is
It has a backplane interface 11 for interfacing via the backplane according to the CUBIT ^™ protocol.

The queuing function 12 performs a wide range of buffering operation using a DRAM or SRAM outside the ASIC 10 and is accessed via a CellRAM controller 13. This queuing function uses the SRAM controller 14 to access another external SRAM. External memory is generally
It is used for an operation link list and the like, and for storing cells waiting for transfer. More specifically, the SRAM accessed by the SRAM controller 14 includes:
It is effectively used as an external register and for storing queue parameters including queue size. On the other hand, a DRAM or SRAM accessed via the CellRAM controller 13 is used to store actual cells. C
When dequeuing from the cell RAM, the SRAM is used to track cells using pointer information.

Cells received in direction A at backplane interface 11 are passed to queuing function 12 and can be routed to CellRAM. The cell then follows path A shown in FIG.
5 is transferred. This is the main interface that supports multiple ports, eight in this embodiment. Again, the UTOPIA protocol is used. Therefore, in pass A, the ASIC 10 does not change the cell, but does not use a queuing mechanism and external memory to manage output to the line.

In the opposite direction, the cell is received at line interface 15 in the direction indicated by arrow B and forwarded to mapping function 16. The mapping function 16 changes the VCI / VPI header according to the destination of the cell, and by doing so, redirects the cell to the correct destination. The mapping function does not "know" what the different cell streams represent, but identifies the streams based on their headers. The cell is passed to a policing function 17 that operates according to an algorithm that evaluates certain policing parameters, such as the cell rate for the identification contract. Various parameters are taken into account, for example, the temporal nature of excessive bandwidth utilization for the identification contract. SRAM
SRAM accessed through controller 14 is used for some of these functions. After the policing function, the cell is transferred to the backplane interface 11.

The ASIC 10 also has a processor interface 20 and a configuration / status function 21. The configuration / status function 21 is connected to the queuing function 12 and the SRAM controller 14. This allows the microprocessor to access the ASIC 10 and perform a limited set of functions including initial setup and configuration and subsequent status monitoring. An important initial setup function is the configuration of the SRAM. After that, the processor
4 and access the location of the SRAM via the interface 20 to monitor parameters such as the number of cells dropped.

An important aspect of ASIC 10 is that it can use control signals communicated in ATM format. To do this, the ASIC 10
It uses a segmentation reassembly (SAR) interface 25 that is connected to a segmentation reassembly (SAR) device that performs AAL5 segmentation and reassembly of TM messages. This interface is used for communication of ATM messages with the SAR device. The SAR device interfaces to another device such as a microprocessor (which may be the same microprocessor connected to interface 20) for comprehensive control communication. The nature of ATM in this communication is transparent to the microprocessor for operation of the SAR device. Thus, a single microprocessor may access ASIC 10 in two different ways. One is direct access for initial setup and parameter monitoring, and the other is access for comprehensive control communication.

Referring again to direction A of FIG. 1, cells received at backplane interface 11 are placed in one of a plurality of queues depending on their VPI / VCI. This queue is serviced based on a predetermined program, and a priority queue system is realized. A queue that has grown too large may have cells discarded based on the configuration. The statistics maintained are the number of cells received, the number of bad cells, and the number of cells discarded due to congestion.

The queuing is started by the microprocessor using the configuration / status function 21. This feature has registers where there is a conceptual division between registers related to queuing and registers related to dequeuing. The queuing function 12 uses a significant number of tables to control the buffering and congestion management functions. One such table is a path descriptor, the starting address of which is provided by a configuration register. To form an offset into this table, the VPI of the incoming cell is used. In addition, for mapping, SA
There are special path descriptors for R and for the processor, the addresses of which are also provided by the configuration registers.

Another table is a queue descriptor, which contains information about individual queues. Although all queues are identical, the queues may appear to have different characteristics depending on the programming of the queue server matrix. The queues are irrevocably tied to the target output ports, and each of the eight line ports has eight queues associated with it. In addition, one queue is maintained for each processor, SAR, and mapping element. The mapping between the cue and the target is identified in two tables, one for each of the aggregation mode and the subordination mode. Each queue has a four-word descriptor, and the offset from the value of the configuration register that holds the starting position is simply four times the number of queues.

The queue server matrix 30 is shown in FIG. The queue server matrix controls the order in which queues are serviced. Its position and maximum size (
1024 elements) are indicated by the configuration register. Each element (31) of the matrix holds 11 used in the field. Each field is associated with a queue. Queues are checked in ascending order. That is, the first queue checked is the most significant byte of the first word. The value of the field indicates the priority of the associated queue.

The storage pool of the queue is called a heap and is composed of a stack of DRAM addresses. 21 heaps are maintained. The heap structure is implemented as a set of pointers maintained internally and also as DRAM addresses stored in SRAM. In heap initialization, a pointer to the top of the stack and the start of the stack is programmed into the SRAM for each of the heaps used, and then the SRAM location between these two pointer values is set to a unique and valid value. DR
Initialize with a set of AM locations. The configuration register is used for programming the heap pointer. These features provide great flexibility in how queues are set up and managed dynamically.

As shown in FIG. 1, the output cell of the queuing function is a line interface 1
5 or the SAR interface 25. In the opposite direction, cells received at line interface 15 are passed to mapping function 16 and policing function 17. The cell is passed to the backplane interface 11, passed to the queuing function 12, or discarded. Again, the configuration register stores the initialization information. The SRAM table is maintained by functions 16 and 17. There are five tables associated with the mapping function 16 as follows. A statistics table for each port; a VCC connection table; a dequeue connection table; and a second mapping descriptor table.

The storage of these tables is set by configuration registers. The per-port statistics table stores information including invalid and disabled VPI / VCIs and the number of cells with unsupported PTIs. This table also has the VPI / VCI of the last disabled state invalid cell.

The VCC connection table has the following information on a connection basis. Mapping descriptors Total number of cells received Total number of dropped cells GCRA words 1-4. The VPC connection tables are identical except that VPI is used instead of VCI. The dequeue connection table has a maximum of 1024 entries and consists of 1024 32-bit mapping descriptors. The second mapping descriptor table is composed of 4096 32-bit entries. Each of the second mapping descriptors is 14 bits long and is shown below.

Field Name Size Bit Position Reserved 18 14-31 map_vpi 1 13 cell_routing 3 10-12 vci-map 100 0-9

Here, the three UTOPIA interfaces 11, schematically shown in FIG.
15 and 25. All interfaces must be in the appropriate Start-
The reception of a cell from an external source is started using an of-Cell (SOC) signal. Each interface counts octets and an error indication is given when the SOC is activated at an unexpected time. This gives a warning about the abnormal cell entering the ASIC and provides a mechanism to recover it at the next cell boundary. Short cells are discarded, and long cells are cut short to continue. Either causes an error indication. The cells are synchronized with the internal common system clock "sys clk" before being transferred internally. Phase locked loop (PLL) 4
0 provides an internal clock signal from the external microprocessor 42. The SAR device 43 is shown connected to the SAR interface 25.
Also, a line device 44 and a backplane device 45 are shown connected to respective interfaces.

It will be appreciated that the present invention provides for very efficient processing of ATM cells between the line and the backplane. Cell rate fluctuations are efficiently handled by the queuing mechanism. The circuit also supports many different services by efficiently routing cell streams. This circuit also makes it possible to implement the policing function very efficiently with little effect on the cell transfer rate.

The present invention is not limited to the above embodiments, but within the scope of the claims,
Its configuration and details can be changed.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a cell processor of the present invention.

FIG. 2 is a diagram illustrating the operation of a queue server matrix.

FIG. 3 is a diagram showing a UTOPIA interface of a cell processor.

──────────────────────────────────────────────────続 き Continuation of front page (81) Designated country EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE ), OA (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, KE, LS, MW, SD, SZ, UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, CN, CU, CZ, DE, DK, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE , KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, UA, UG, US, UZ, VN, YU, ZW Man Charliere Brachet, 73

Claims (14)

[Claims] 1. An ATM cell processor, comprising: a line interface; a backplane interface; and processing means for identifying a cell stream based on a cell header and processing the identified cell. 2. The cell processor according to claim 1, wherein said line interface and said backplane interface are bidirectional. 3. The cell processor according to claim 1, wherein said processing means has a mapping function. 4. The cell processor according to claim 1, wherein said mapping function includes means for changing a cell header according to a destination of the mapped cell. 5. The cell processor according to claim 1, wherein said mapping function includes means for adding an additional header to a cell for transmitting an internal control signal. 6. The cell processor according to claim 1, wherein said processing means has a policing function for monitoring traffic characteristics. 7. The cell processor according to claim 1, wherein the cell processor has a queuing function connected between interfaces for controlling transfer of a cell to the line interface. Cell processor. 8. The queuing function comprises means for interfacing to a cell memory for storing a queue of cells and to a control memory for storing queuing parameter values. The cell processor according to claim 7, wherein 9. The cell processor of claim 8, wherein said queuing function is connected to a memory controller for interfacing to cells and control memory. 10. The queuing function comprises means for managing a path descriptor table in the control memory.
A cell processor according to item 1. 11. The queuing function according to claim 1, wherein the queuing function has means for managing a queue descriptor table associated with each queue in the control memory. Cell processor. 12. The method of claim 11, wherein the cell is external segmentation reassembly (SAR
) Segmentation reassembly (SA) for routing to devices
The cell processor according to claim 1, further comprising: (R) an interface. 13. The SAR interface is connected to the queuing function, and the queuing function includes means for routing a cell to the SAR interface and the line interface according to a header of the cell. The cell processor according to claim 12, wherein 14. The cell processor according to claim 1, wherein the cell processor has a control processor interface for connection to a memory controller enabling an initial setup configuration.