IES80918B2 - An atm cell processor - Google Patents

An atm cell processor

Info

Publication number
IES80918B2
IES80918B2 IES980712A IES80918B2 IE S80918 B2 IES80918 B2 IE S80918B2 IE S980712 A IES980712 A IE S980712A IE S80918 B2 IES80918 B2 IE S80918B2
Authority
IE
Ireland
Prior art keywords
processor
cell
function
cells
memory
Prior art date
Application number
Inventor
Kevin Dewar
Brendan O'dowd
Gavin Brebner
Original Assignee
Tellabs Research Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tellabs Research Limited filed Critical Tellabs Research Limited
Priority to IE980712A priority Critical patent/IES980712A2/en
Priority to AU16804/99A priority patent/AU1680499A/en
Priority to CA002315052A priority patent/CA2315052A1/en
Priority to IE981056A priority patent/IE981056A1/en
Priority to JP2000539674A priority patent/JP2002509412A/en
Priority to PCT/IE1998/000106 priority patent/WO1999031928A2/en
Priority to EP98961336A priority patent/EP1040707A2/en
Publication of IES80918B2 publication Critical patent/IES80918B2/en
Publication of IES980712A2 publication Critical patent/IES980712A2/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/255—Control mechanisms for ATM switching fabrics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H04L2012/5653—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL]
    • H04L2012/5658—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL] using the AAL5
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

An ATM cell processor (10) has a backplane interface (11), a line interface (15), and various processing functions between the interfaces. Cells directed to the line interface (15) are controlled by a queueing function (12) which uses external cell memory via a controller (13) and external control memory via a controller (14). Cells from the backplane are identified and routed by a mapping function (16).

Description

The invention relates to a processor for handling asynchronous transfer mode (ATM) cells. An object of the invention is to provide for efficient handling of cells by a processor. Another object is that the processor has flexibility in the manner in which it operates so that it may be used in different environments with relatively simple configuration.
A still further object is to provide a cell processor which may be controlled in a 10 comprehensive manner with relatively simple control circuits.
According to the invention, there is provided an ATM cell processor comprising at least two interfaces, and a queueing function between the interfaces for controlling transfer of cells. The queueing function allows cell traffic management in a very effective manner.
The interfaces are preferably bi-directional.
Preferably, the queueing function uses a cell memory for storage of cell queues, and a control memory for storing queueing control settings. This is a very effective way of achieving the necessary control in a flexible manner.
In one embodiment, the memory is at least partly external to the processor and is accessed via a controller. This allows easy expansion and flexibility for different applications generally.
In another embodiment, the processor further comprises a mapping function for mapping received cells from a line according to the VPI/VCI. This allows integration of the processor into a system having multiple internal destinations for received cells.
Preferably, the mapping function comprises means for adding an additional header for internal control signalling. This further enhances effectiveness of internal routing of signals.

Claims (5)

1. An ATM cell processor comprising at least two interfaces, and a queuing function between the interfaces for controlling transfer of cells.
2. A cell processor as claimed in claim 1, wherein the interfaces are bi-directional, and wherein the queuing function uses a cell memory for storage of cell queues, and a control memory for storing queueing control settings, and wherein the memory is at least partly external to the processor and is accessed via a controller, and wherein the processor further comprises a mapping function for mapping received cells from a line according to the VPI/VCl, and wherein the mapping function comprises means for adding an additional header for internal control signalling.
3. A cell processor as claimed in claims 1 or 2, further comprising a policing function for monitoring traffic characteristics of cells received from the line.
4. A cell processor as claimed in any preceding claim, further comprising a segmentation and reassembly (SAR) interface for handling ATM cell control signals, and wherein the SAR interface is connected to the queueing function, and wherein the processor further comprises a control processor interface connected to a memory controller to allow initial setup configuration and on-going monitoring.
5. A cell processor substantially as described with reference to the drawings. 1/3 ίο LINE MICROPROCESSOR SRAM «5 Fig.l
IE980712A 1997-12-15 1998-08-31 An ATM cell processor IES980712A2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
IE980712A IES980712A2 (en) 1997-12-15 1998-08-31 An ATM cell processor
AU16804/99A AU1680499A (en) 1997-12-15 1998-12-15 An atm cell processor
CA002315052A CA2315052A1 (en) 1997-12-15 1998-12-15 An atm cell processor
IE981056A IE981056A1 (en) 1997-12-15 1998-12-15 An ATM Cell Processor
JP2000539674A JP2002509412A (en) 1997-12-15 1998-12-15 ATM cell processor
PCT/IE1998/000106 WO1999031928A2 (en) 1997-12-15 1998-12-15 An atm cell processor
EP98961336A EP1040707A2 (en) 1997-12-15 1998-12-15 An atm cell processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IE970888 1997-12-15
IE980712A IES980712A2 (en) 1997-12-15 1998-08-31 An ATM cell processor

Publications (2)

Publication Number Publication Date
IES80918B2 true IES80918B2 (en) 1999-06-30
IES980712A2 IES980712A2 (en) 1999-06-30

Family

ID=26320137

Family Applications (1)

Application Number Title Priority Date Filing Date
IE980712A IES980712A2 (en) 1997-12-15 1998-08-31 An ATM cell processor

Country Status (6)

Country Link
EP (1) EP1040707A2 (en)
JP (1) JP2002509412A (en)
AU (1) AU1680499A (en)
CA (1) CA2315052A1 (en)
IE (1) IES980712A2 (en)
WO (1) WO1999031928A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030067874A1 (en) * 2001-10-10 2003-04-10 See Michael B. Central policy based traffic management

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3599392B2 (en) * 1994-12-15 2004-12-08 富士通株式会社 switch
EP0719065A1 (en) * 1994-12-20 1996-06-26 International Business Machines Corporation Multipurpose packet switching node for a data communication network
US5664116A (en) * 1995-07-07 1997-09-02 Sun Microsystems, Inc. Buffering of data for transmission in a computer communication system interface
US6128303A (en) * 1996-05-09 2000-10-03 Maker Communications, Inc. Asynchronous transfer mode cell processing system with scoreboard scheduling

Also Published As

Publication number Publication date
WO1999031928A3 (en) 1999-10-28
JP2002509412A (en) 2002-03-26
WO1999031928A2 (en) 1999-06-24
IES980712A2 (en) 1999-06-30
EP1040707A2 (en) 2000-10-04
CA2315052A1 (en) 1999-06-24
AU1680499A (en) 1999-07-05

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MM4A Patent lapsed