WO2003091857A3 - Efficient packet processing pipeline device and method - Google Patents

Efficient packet processing pipeline device and method Download PDF

Info

Publication number
WO2003091857A3
WO2003091857A3 PCT/US2003/014259 US0314259W WO03091857A3 WO 2003091857 A3 WO2003091857 A3 WO 2003091857A3 US 0314259 W US0314259 W US 0314259W WO 03091857 A3 WO03091857 A3 WO 03091857A3
Authority
WO
WIPO (PCT)
Prior art keywords
data portion
processing unit
packet
administrative information
packet processing
Prior art date
Application number
PCT/US2003/014259
Other languages
French (fr)
Other versions
WO2003091857A2 (en
WO2003091857A9 (en
Inventor
Koen Deforche
Geert Verbruggen
Coster Luc De
Johan Wouters
Original Assignee
Transwitch Corp
Koen Deforche
Geert Verbruggen
Coster Luc De
Johan Wouters
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Transwitch Corp, Koen Deforche, Geert Verbruggen, Coster Luc De, Johan Wouters filed Critical Transwitch Corp
Priority to AU2003228900A priority Critical patent/AU2003228900A1/en
Priority to EP03726675A priority patent/EP1523829A4/en
Priority to US10/512,334 priority patent/US20050232303A1/en
Publication of WO2003091857A2 publication Critical patent/WO2003091857A2/en
Publication of WO2003091857A3 publication Critical patent/WO2003091857A3/en
Publication of WO2003091857A9 publication Critical patent/WO2003091857A9/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3072—Packet splitting
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3063—Pipelined operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

A packet processing apparatus (10) for processing data packets for use in a packet switched network includes means for receiving a packet, means for adding administrative information to a first data portion of the packet, the administrative information includes at least an indication of at least one process to be applied to the first data portion, and a plurality of parallel pipelines, each pipeline comprising at least one processing unit (4), wherein the processing unit carries out the process on the first data portion indicated by the administrative information to provide a modified first data portion. According to a method, the tasks performed by each processing unit are organized into a plurality of functions such that there are substantially only function calls and no interfunction calls and that at the termination of each function called by the function call for one processing unit, the only context is a first data portion.
PCT/US2003/014259 2002-04-26 2003-04-25 Efficient packet processing pipeline device and method WO2003091857A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU2003228900A AU2003228900A1 (en) 2002-04-26 2003-04-25 Efficient packet processing pipeline device and method
EP03726675A EP1523829A4 (en) 2002-04-26 2003-04-25 Efficient packet processing pipeline device and method
US10/512,334 US20050232303A1 (en) 2002-04-26 2003-04-25 Efficient packet processing pipeline device and method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0209670.9A GB0209670D0 (en) 2002-04-26 2002-04-26 Efficient packet processing pipelining device and method
GB0209670.9 2002-04-26

Publications (3)

Publication Number Publication Date
WO2003091857A2 WO2003091857A2 (en) 2003-11-06
WO2003091857A3 true WO2003091857A3 (en) 2003-12-11
WO2003091857A9 WO2003091857A9 (en) 2007-12-13

Family

ID=9935632

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/014259 WO2003091857A2 (en) 2002-04-26 2003-04-25 Efficient packet processing pipeline device and method

Country Status (5)

Country Link
EP (1) EP1523829A4 (en)
CN (1) CN100450050C (en)
AU (1) AU2003228900A1 (en)
GB (1) GB0209670D0 (en)
WO (1) WO2003091857A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012015388A1 (en) * 2010-07-26 2012-02-02 Hewlett-Packard Development Company, L. P. Mitigation of detected patterns in a network device
WO2018188738A1 (en) * 2017-04-11 2018-10-18 NEC Laboratories Europe GmbH Packet handling method and apparatus for network service functions
CN113364685B (en) * 2021-05-17 2023-03-14 中国人民解放军国防科技大学 Distributed MAC table item processing device and method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755986A (en) * 1985-09-13 1988-07-05 Nec Corporation Packet switching system

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4899333A (en) * 1988-03-31 1990-02-06 American Telephone And Telegraph Company At&T Bell Laboratories Architecture of the control of a high performance packet switching distribution network
US5341369A (en) * 1992-02-11 1994-08-23 Vitesse Semiconductor Corp. Multichannel self-routing packet switching network architecture
US6182210B1 (en) * 1997-12-16 2001-01-30 Intel Corporation Processor having multiple program counters and trace buffers outside an execution pipeline
US6286027B1 (en) * 1998-11-30 2001-09-04 Lucent Technologies Inc. Two step thread creation with register renaming
US6341347B1 (en) * 1999-05-11 2002-01-22 Sun Microsystems, Inc. Thread switch logic in a multiple-thread processor
US6625654B1 (en) * 1999-12-28 2003-09-23 Intel Corporation Thread signaling in multi-threaded network processor
EP1287652A1 (en) * 2000-01-30 2003-03-05 Celox Networks, Inc. Device and method for packet formatting
US20020069402A1 (en) * 2000-10-05 2002-06-06 Nevill Edward Colles Scheduling control within a system having mixed hardware and software based instruction execution

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755986A (en) * 1985-09-13 1988-07-05 Nec Corporation Packet switching system

Also Published As

Publication number Publication date
EP1523829A4 (en) 2007-12-19
CN100450050C (en) 2009-01-07
GB0209670D0 (en) 2002-06-05
AU2003228900A8 (en) 2003-11-10
CN1663188A (en) 2005-08-31
EP1523829A2 (en) 2005-04-20
AU2003228900A1 (en) 2003-11-10
WO2003091857A2 (en) 2003-11-06
WO2003091857A9 (en) 2007-12-13

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