EP1460680A3 - Komplementäre Implantationen der Vermeidung der Ausweitung des Übergangs für die Herstellung ultraflacher Übergänge - Google Patents
Komplementäre Implantationen der Vermeidung der Ausweitung des Übergangs für die Herstellung ultraflacher Übergänge Download PDFInfo
- Publication number
- EP1460680A3 EP1460680A3 EP04101123A EP04101123A EP1460680A3 EP 1460680 A3 EP1460680 A3 EP 1460680A3 EP 04101123 A EP04101123 A EP 04101123A EP 04101123 A EP04101123 A EP 04101123A EP 1460680 A3 EP1460680 A3 EP 1460680A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- implantation
- shallow junctions
- implants
- narrowing
- ultra
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 230000000295 complement effect Effects 0.000 title 1
- 239000007943 implant Substances 0.000 title 1
- 239000002019 doping agent Substances 0.000 abstract 4
- 238000002513 implantation Methods 0.000 abstract 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 abstract 2
- 238000005468 ion implantation Methods 0.000 abstract 2
- 229910052787 antimony Inorganic materials 0.000 abstract 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 abstract 1
- 229910052796 boron Inorganic materials 0.000 abstract 1
- 230000005465 channeling Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 229910052731 fluorine Inorganic materials 0.000 abstract 1
- 239000011737 fluorine Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US393749 | 1989-08-15 | ||
US10/393,749 US6808997B2 (en) | 2003-03-21 | 2003-03-21 | Complementary junction-narrowing implants for ultra-shallow junctions |
Publications (3)
Publication Number | Publication Date |
---|---|
EP1460680A2 EP1460680A2 (de) | 2004-09-22 |
EP1460680A3 true EP1460680A3 (de) | 2005-08-17 |
EP1460680B1 EP1460680B1 (de) | 2011-01-19 |
Family
ID=32824912
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP04101123A Expired - Lifetime EP1460680B1 (de) | 2003-03-21 | 2004-03-18 | Komplementäre Implantationen zur Vermeidung der Ausweitung des Übergangs für die Herstellung ultraflacher Übergänge |
Country Status (4)
Country | Link |
---|---|
US (2) | US6808997B2 (de) |
EP (1) | EP1460680B1 (de) |
JP (1) | JP2004289154A (de) |
DE (1) | DE602004031065D1 (de) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003096397A1 (en) * | 2002-05-10 | 2003-11-20 | Varian Semiconductor Equipment Associates, Inc. | Methods and systems for dopant profiling |
US6767809B2 (en) * | 2002-11-19 | 2004-07-27 | Silterra Malayisa Sdn. Bhd. | Method of forming ultra shallow junctions |
CN1253929C (zh) * | 2003-03-04 | 2006-04-26 | 松下电器产业株式会社 | 半导体装置及其制造方法 |
US20060017079A1 (en) * | 2004-07-21 | 2006-01-26 | Srinivasan Chakravarthi | N-type transistor with antimony-doped ultra shallow source and drain |
US7482255B2 (en) * | 2004-12-17 | 2009-01-27 | Houda Graoui | Method of ion implantation to reduce transient enhanced diffusion |
CN101207020B (zh) * | 2006-12-22 | 2010-09-29 | 中芯国际集成电路制造(上海)有限公司 | 形成超浅结的方法 |
US7888223B2 (en) * | 2007-03-28 | 2011-02-15 | United Microelectronics Corp. | Method for fabricating P-channel field-effect transistor (FET) |
US8664073B2 (en) | 2007-03-28 | 2014-03-04 | United Microelectronics Corp. | Method for fabricating field-effect transistor |
US20090065820A1 (en) * | 2007-09-06 | 2009-03-12 | Lu-Yang Kao | Method and structure for simultaneously fabricating selective film and spacer |
US8232605B2 (en) * | 2008-12-17 | 2012-07-31 | United Microelectronics Corp. | Method for gate leakage reduction and Vt shift control and complementary metal-oxide-semiconductor device |
JP2012099510A (ja) * | 2009-03-09 | 2012-05-24 | Toshiba Corp | 半導体装置およびその製造方法 |
US8178430B2 (en) * | 2009-04-08 | 2012-05-15 | International Business Machines Corporation | N-type carrier enhancement in semiconductors |
US8269275B2 (en) * | 2009-10-21 | 2012-09-18 | Broadcom Corporation | Method for fabricating a MOS transistor with reduced channel length variation and related structure |
US8564063B2 (en) | 2010-12-07 | 2013-10-22 | United Microelectronics Corp. | Semiconductor device having metal gate and manufacturing method thereof |
CN102637646B (zh) * | 2011-02-10 | 2014-04-23 | 上海宏力半导体制造有限公司 | 存储器制备方法 |
US8772118B2 (en) | 2011-07-08 | 2014-07-08 | Texas Instruments Incorporated | Offset screen for shallow source/drain extension implants, and processes and integrated circuits |
US9455321B1 (en) | 2015-05-06 | 2016-09-27 | United Microelectronics Corp. | Method for fabricating semiconductor device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6069062A (en) * | 1997-09-16 | 2000-05-30 | Varian Semiconductor Equipment Associates, Inc. | Methods for forming shallow junctions in semiconductor wafers |
EP1455386A2 (de) * | 2003-03-04 | 2004-09-08 | Matsushita Electric Industrial Co., Ltd. | Halbleitervorrichtung und Herstellungsverfahren |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1079506A (ja) * | 1996-02-07 | 1998-03-24 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
KR0183645B1 (ko) | 1996-03-26 | 1999-03-20 | 이대원 | 다층 구조의 도금층을 구비한 반도체 리드 프레임 |
KR100527207B1 (ko) | 1996-05-08 | 2005-11-09 | 어드밴스드 마이크로 디바이시즈, 인코포레이티드 | 도펀트 확산을 가로막도록 생성된 격자간 변화도를 이용한접합 깊이 및 채널 길이의 제어 |
US5793090A (en) | 1997-01-10 | 1998-08-11 | Advanced Micro Devices, Inc. | Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance |
US6037640A (en) * | 1997-11-12 | 2000-03-14 | International Business Machines Corporation | Ultra-shallow semiconductor junction formation |
US6087247A (en) | 1998-01-29 | 2000-07-11 | Varian Semiconductor Equipment Associates, Inc. | Method for forming shallow junctions in semiconductor wafers using controlled, low level oxygen ambients during annealing |
US6355543B1 (en) | 1998-09-29 | 2002-03-12 | Advanced Micro Devices, Inc. | Laser annealing for forming shallow source/drain extension for MOS transistor |
US6180476B1 (en) | 1998-11-06 | 2001-01-30 | Advanced Micro Devices, Inc. | Dual amorphization implant process for ultra-shallow drain and source extensions |
KR100318459B1 (ko) | 1998-12-22 | 2002-02-19 | 박종섭 | 티타늄폴리사이드게이트전극형성방법 |
WO2001055752A1 (en) * | 2000-01-26 | 2001-08-02 | Sola International Holdings Limited | Anti-static, anti-reflection coating |
US6265255B1 (en) | 2000-03-17 | 2001-07-24 | United Microelectronics Corp. | Ultra-shallow junction formation for deep sub-micron complementary metal-oxide-semiconductor |
US6358823B1 (en) | 2000-04-12 | 2002-03-19 | Institut Fuer Halbleiterphysik Frankfurt (Oder) Gmbh. | Method of fabricating ion implanted doping layers in semiconductor materials and integrated circuits made therefrom |
JP2002076332A (ja) * | 2000-08-24 | 2002-03-15 | Hitachi Ltd | 絶縁ゲート型電界効果トランジスタ及びその製造方法 |
US6534373B1 (en) * | 2001-03-26 | 2003-03-18 | Advanced Micro Devices, Inc. | MOS transistor with reduced floating body effect |
US6458643B1 (en) * | 2001-07-03 | 2002-10-01 | Macronix International Co. Ltd. | Method of fabricating a MOS device with an ultra-shallow junction |
-
2003
- 2003-03-21 US US10/393,749 patent/US6808997B2/en not_active Expired - Lifetime
-
2004
- 2004-03-18 EP EP04101123A patent/EP1460680B1/de not_active Expired - Lifetime
- 2004-03-18 DE DE602004031065T patent/DE602004031065D1/de not_active Expired - Lifetime
- 2004-03-19 JP JP2004079351A patent/JP2004289154A/ja not_active Abandoned
- 2004-09-15 US US10/942,607 patent/US7345355B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6069062A (en) * | 1997-09-16 | 2000-05-30 | Varian Semiconductor Equipment Associates, Inc. | Methods for forming shallow junctions in semiconductor wafers |
EP1455386A2 (de) * | 2003-03-04 | 2004-09-08 | Matsushita Electric Industrial Co., Ltd. | Halbleitervorrichtung und Herstellungsverfahren |
Non-Patent Citations (1)
Title |
---|
SOLMI SANDRO: "Counterdoped very shallow p+/n junctions obtained by B and Sb implantation and codiffusion in Si", JOURNAL OF APPLIED PHYSICS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 83, no. 3, 1 February 1998 (1998-02-01), pages 1742 - 1747, XP012044639, ISSN: 0021-8979 * |
Also Published As
Publication number | Publication date |
---|---|
EP1460680A2 (de) | 2004-09-22 |
DE602004031065D1 (de) | 2011-03-03 |
JP2004289154A (ja) | 2004-10-14 |
US20050042848A1 (en) | 2005-02-24 |
US6808997B2 (en) | 2004-10-26 |
US7345355B2 (en) | 2008-03-18 |
US20040185633A1 (en) | 2004-09-23 |
EP1460680B1 (de) | 2011-01-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1460680A3 (de) | Komplementäre Implantationen der Vermeidung der Ausweitung des Übergangs für die Herstellung ultraflacher Übergänge | |
US7400018B2 (en) | End of range (EOR) secondary defect engineering using chemical vapor deposition (CVD) substitutional carbon doping | |
WO2007027798A3 (en) | Boron ion implantation using alternative fluorinated boron precursors, and formation of large boron hydrides for implantation | |
US7741699B2 (en) | Semiconductor device having ultra-shallow and highly activated source/drain extensions | |
WO2006064282B1 (en) | A method of ion implantation to reduce transient enhanced diffusion | |
EP0768715A3 (de) | Halbleiteranordnung mit gradiertem Kanal und Verfahren zur Herstellung | |
AU6670898A (en) | Hot pressed silicon carbide wafer and method of using it as a dummy wafer | |
CA2333579A1 (en) | Self-aligned methods of fabricating silicon carbide power devices by implantation and lateral diffusions | |
EP0945899A3 (de) | Halbleiterbauelement mit einem halbisolierenden Gebiet und Verfahren zu dessen Herstellung. | |
WO2006062536A3 (en) | Formation of ultra-shallow junctions by gas-cluster ion irridation | |
EP2400530A3 (de) | Diamanthalbleiterbauelement und Herstellungsverfahren dafür | |
EP1365447A3 (de) | Herstellungsverfahren eines Halbleitersubstrats | |
WO2006086644A8 (en) | Back-illuminated imaging device and method of fabricating same | |
WO2009050871A1 (ja) | 半導体装置およびその製造方法 | |
TW345691B (en) | Integrated circuit fabrication | |
WO2006047061A3 (en) | Use of defined compounds for the manufacture of a medicament for preventing/ treating diseases resulting from somatic mutation | |
WO2006053241A3 (en) | Ultra-shallow arsenic junction formation in silicon germanium | |
Cristiano et al. | Thermal stability of boron electrical activation in preamorphised ultra-shallow junctions | |
WO2004095516A3 (en) | Apparatus and method for polishing semiconductor wafers using one or more polishing surfaces | |
EP1291905A3 (de) | Verfahren zur Herstellung einer Halbleitervorrichtung | |
TW200507117A (en) | Formation of junctions and silicides with reduced thermal budget | |
EP0746018A3 (de) | Verfahren zum Ausbilden einer hochschmelzenden Metallsilizidschicht mit gleissmässiger Dicke | |
EP1282172A3 (de) | Bipolares Halbleiterbauelement und dessen Herstellungsverfahren | |
TW360915B (en) | Dopant profile spreading for arsenic source/drain | |
WO2006039677A3 (en) | Semiconductor doping using substrate tilting |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR |
|
AX | Request for extension of the european patent |
Extension state: AL LT LV MK |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PL PT RO SE SI SK TR |
|
AX | Request for extension of the european patent |
Extension state: AL LT LV MK |
|
17P | Request for examination filed |
Effective date: 20060217 |
|
AKX | Designation fees paid |
Designated state(s): DE FR GB |
|
17Q | First examination report despatched |
Effective date: 20070207 |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D |
|
REF | Corresponds to: |
Ref document number: 602004031065 Country of ref document: DE Date of ref document: 20110303 Kind code of ref document: P |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R096 Ref document number: 602004031065 Country of ref document: DE Effective date: 20110303 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed |
Effective date: 20111020 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R097 Ref document number: 602004031065 Country of ref document: DE Effective date: 20111020 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 13 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 14 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 15 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20190215 Year of fee payment: 16 Ref country code: GB Payment date: 20190227 Year of fee payment: 16 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20190220 Year of fee payment: 16 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R119 Ref document number: 602004031065 Country of ref document: DE |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20201001 Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20200331 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20200318 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20200318 |