Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/14—Error detection or correction of the data by redundancy in operation
  • G06F11/1402—Saving, restoring, recovering or retrying
  • G06F11/1415—Saving, restoring, recovering or retrying at system level
  • G06F11/1441—Resetting or repowering

Definitions

• This invention pertains to error recovery in a device connected to a USB interface and, more particularly, to a method for recovering from a SUSPEND state on a USB bus induced by a transient impulse, noise, etc.
• USB Universal Serial Bus
• POS point-of-sale
• serial interface has long been considered desirable for attachment of remote devices such as POS printers to their central controller. Unlike many other interconnection methods, serial interfaces traditionally have required fewer conductors in interconnection cables. Also, greater cable lengths are typically available than are with other interface methods. For many years, the serial interfaces were defined by the RS-232 "standard". Unfortunately, according to at least one industry expert, "the only thing standard about RS- 232 is the name.” Indeed, very little could be assumed about a device advertising an RS-232 interface. Pinouts on connecters varied, voltage levels varied and signal-timing requirements were rarely standard.
• USB eliminates most of the problems inherent in RS-232, RS-422, and other "standard" prior art serial interconnection strategies while maintaining a small conductor count in the interconnection cables.
• up to 127 different USB- equipped devices can be plugged together using one or more USB hubs with no manual configuration required.
• the electrical signaling method and protocol chosen for its implementation is inherently less immune to electrical disturbances (i.e., electrical noise) than were its precursors.
• electrical disturbances i.e., electrical noise
• the ubiquitous RS-232 interface was often implemented using voltage swings in the range of between ⁇ 10 and ⁇ 15 volts.
• the USB standard recites signal voltage swings of only 0 - 3.3 volts.
• the USB uses differential techniques for purposes of speed, the noise immunity of a 0 - 3.3-volt signal is inherently worse than the ⁇ 10 to ⁇ 15 volt (i.e., 20 - 30 volt swings) that the RS-232 interfaces utilize.
• H0085620.1 2 RS-232 drivers typically can withstand a 2KV or higher electrostatic discharge (ESD) "hit" directly input the port.
• ESD electrostatic discharge
• the single-chip design of typical USB transceivers contains both line driver and logic circuitry for the serial interface engine, and FIFO buffers, etc. in close proximity. This means that there is little or no physical isolation between the line drivers, which must absorb and dissipate a noise spike such as an ESD hit, and the far more sensitive logic circuitry.
• Such circuitry by virtue of its placement, is far more vulnerable to ESD and other similar spurious signals than older designs wherein the line driver circuitry was typically physically isolated from more sensitive logic circuitry.
• each attached device must process a periodic Start Of Frame (e.g., a 1 ms SOF) packet. This is necessary to maintain contact with downstream devices attached to the host via hubs, etc. To stay attached to the bus, each attached device must almost continuously process these SOF packets. Older, more robust interfaces (e.g., RS-232) could remain quiescent until data transmission or reception was required.
• the USB remains almost continuously sensitive to noise, whereas the older interfaces are generally insensitive to noise during their quiescent periods.
• the USB incorporates a very good error recovery mechanism buried in its hardware layer.
• Each data packet transmitted over the USB contains a cyclic redundancy check (CRC) number. This allows the receiver to test each data packet for errors and request a re-transmission when an error occurs. This is accomplished by "NACKing" (i.e., No-Acknowledge) data packets in which errors are detected. Because of this error recovery strategy, the effect of noise on the bus results in an overall slowdown of data transmission because of the many NACKed
• USB standard fails to adequately address the problems associated with ESD sensitivity or the overall network sensitivity caused by the need for almost continuous SOF processing, at least for high reliability applications such as POS printing. While the USB standard requires that each USB device meet CE mark (i.e., the requirements of the European Community European Directive 93/68/EEC) , few marked USB products have been found to meet the minimum electromagnetic compatibility (EMC) immunity requirements satisfactorily. Included under the EMC umbrella are electrostatic discharge (ESD) , electrical fast transients (EFT) , radiated RF interference (RFI) , and conducted RF interference (CRFI) . When an interfering noise condition or event persists over several SOF packets, the host is often prevented from receiving replies to its status requests.
• ESD electrostatic discharge
• EFT electrical fast transients
• RFID radiated RF interference
• CRFI conducted RF interference
• EOP End-Of-Packet
• a condition called "babble" EOP may cause the host to terminate its connection with the device.
• the host will make no attempt to re-connect a still connected node.
• RS-232 has no provision for built-in CRC or status poling, these types of problems do not occur unless detected by application firmware, software, or driver.
• USB driver stack Because the USB driver stack provides no automatic recovery of a suspended device, it is left to the operator to either re-boot or physically re-connect the device. However, to require that the entire POS system be re-booted to recover from a single device becoming non-communicative is impractical .
• USB While the USB topography is generally good at self- healing, there are certain circumstances peculiar to the POS environment, which are not well handled in typical systems using USB communication to peripherals.
• the USB facilitates a constant stream of two-way traffic (i.e., transactions) between the host and each peripheral device, even when no substantive data is being transmitted.
• a strong noise spike or other perturbation on the interface may cause the host, or sometimes a hub downstream from the host, to stop communicating.
• a remote POS terminal has heretofore had no way to attempt to restart the host and/or hub.
• USB is better suited to the "home" computer environment than to the commercial and retail environments.
• noise spike in the home computer environment are typically less severe and system re-boot or device re-attachments have become a commonplace and acceptable part of home computer usage. Nonetheless, there is growing demand for the ease of use features of USB in the POS and other commercial and industrial environments.
• Devices such as POS printers using a USB interface must be designed and built to meet more stringent immunity requirements. Discussion of the Related Art: Automatic recovery of interface errors and/or remotely restarting a computer or host after an error is not new.
• United States Patent No. 4,072,852 for DIGITAL COMPUTER MONITORING AND RESTART CIRCUIT issued February 7, 1978 to James A. Hogan, et al . , teaches a missing pulse detector for monitoring for the periodic occurrence of an output signal
• H0085620.1 5 from a digital computer. If, after a predetermined amount of time, an output pulse is not detected, a reset signal is generated to restart the computer.
• the method of the present invention relies on an algorithm embedded in the firmware of a remotely located peripheral device, not in a hardware circuit located at the computer or host .
• the method of the present invention uses no hardware circuit directly connected to the processor.
• the inventive algorithm operating on each of a large number of peripheral devices remotely located from the host or processor can initiate a reset of the communications interface.
• the processor itself does not reset.
• the inventive method uses an algorithm in the firmware of the peripheral devices to instigate the interface reset.
• United States Patent No. 4,618,953 for WATCHDOG CIRCUIT issued October 21, 1986 to Edward P. Daniels, et al . , teaches a circuit arrangement for improving the possibility of recovery from failures caused by static discharge, RF interference and similar conditions.
• a main processor periodically sends an inquiry to a secondary processor chip, which handles I/O. If status is not returned by the secondary processor chip within a predetermined amount of time, the DANIELS, et al . circuit initiates a reset of the main processor.
• the inventive method does not rely on a hardware circuit but rather is an algorithm forming a part of the firmware
• H0085620.1 6 operating a POS printer remote from the processor (i.e., host) .
• the remote device not the main processor, institutes a reset. The initiation of the inventive reset process does not rely on receiving status information.
• the inventive method restarts the master (i.e., host), not the slave circuit, using an algorithm in the remote device firmware, not by a hardware circuit at the master.
• H0085620.1 V on the other hand, does not lose the data and, if a recovery is possible, allows the printing operation to pick up where it left off before the printer was placed in a suspend state.
• the suspend recovery of the present invention is distinguished from the reset strategies of the aforementioned prior art.
• a method for attempting to reset a host or hub connected via a USB bus to a remote device A routine in the firmware of the remote device monitors the USB bus to detect an unannounced and unanticipated SUSPEND state on the bus. Such an unintended SUSPEND state may be caused by problems such as noise on the bus.
• a firmware routine forces a disconnect of the peripheral device from the USB bus by dropping the D+ signal. After a predetermined time, D+ is again presented to the bus and the host reconnects the remote device and reestablishes communication with the device. Because typically no permanent hardware failure has occurred, the re-attachment process initiated by the remote device again presenting D+ usually resets the host or hub.
• an object of the invention to provide a method to recover from an unintended SUSPEND state on a USB bus . It is another object of the invention to provide a method to recover from an unintended SUSPEND state on a USB bus wherein a remote device initiates the resetting activity. It is a further object of the invention to provide a method to recover from an unintended SUSPEND state on a USB bus wherein a remote device initiates a disconnect then reconnect operation.
• H0085620.1 8 It is a still further object of the invention to provide a method to recover from an unintended SUSPEND state on a USB bus wherein a remote device reconnects to the USB bus by automatically raising its D+ or D- signal.
• FIGURE 1 is a simplified schematic block diagram of a typical USB interface
• FIGURE 2 is a simplified flow chart of the method of the invention.
• the present invention provides a method for initiating a reset of the interface of a host or a hub upstream by a remote device connected to the host or hub by a USB connection.
• a Serial Interface Engine (SIE) 102 forms the heart of USB interface 100.
• SIE 102 contains circuitry within which the entire USB protocol layer is hardwired.
• a hardwired implementation provides maximum speed and eliminates the need for firmware to accomplish the essential USB interface functions. These functions include synchronization pattern recognition, parallel/serial conversion, bit stuffing/de-stuffing, cyclic redundancy check (CRC) generation and verification, address recognition and handshake evaluation and generation.
• CRC cyclic redundancy check
• SIE 102 is connected to bit clock recovery circuit 104, which is connected to phase locked loop (PLL) 106.
• PLL phase locked loop
• PLL 106 is implemented as a 6 MHz to 48 MHz multiplier which allows the
• RAM 108 is connected to SIE 102 by memory manager 110.
• RAM 108 is provided to store both commands and data as required by SIE 102.
• RAM 108 also serves as a buffer between the USB bus, typically operating in burst mode at approximately 12 MBits per second, and the slower DMA/parallel interface 112. This allows the microcontroller or the processor (not shown) to which the USB interface 100 is attached by interface 112, to read and write USB data packets at its own speed.
• DMA/parallel interface 112 provides a generic parallel interface bus for connection either to a data bus (not shown) or to a DMA controller (not shown) within the microcontroller to which USB interface 100 is connected. Interface 112 typically makes USB controller 100 appear as a memory device having an 8 -bit data bus and one address bit memory device.
• Receive data (RxD) and transmit data (TxD) lines 114 and 116, respectively, from SIE 102 are connected to analog transceiver 118.
• the D+ output 120 and the D- output 122 lines from analog transceiver 118 are connected to a standard USB connector 124, which in turn, is mated with a compatible USB connector 126.
• Analog transceiver 118 contains termination resistors (not shown) to properly match its input and output lines to the normal USB bus.
• resistor 128 Connected to the D+ output 120 of analog transceiver 118 is a pull-up resistor 128, which is in turn connected to a positive DC voltage source 130.
• resistor 128 has a resistance of approximately 1500 ohms and DC voltage 130 is typically approximately 3.3 volts. While these values are considered industry standard values, it should be obvious that other voltage/resistor combinations could be used in alternate embodiments to accomplish a similar result.
• SIE 102 is a Phillips USB Interface Device with Parallel Bus, Model No. PDIUSBD12 which contains several functions in addition to SIE 102 (e.g., transceiver 118) within a single package.
• SIE 102 e.g., transceiver 118
• Many other similar USB integrated interface devices are well known to those skilled in the art and other devices could readily be substituted for the Philips PDIUSBD12 device.
• a host transmits start of frame (SOF) packets at predetermined intervals, typically about one every millisecond. Under normal circumstances, these SOF packets are ignored, in fact not even seen by the microcontroller (not shown) . If no bus activity including the SOF packets is detected within a nominal time period, say perhaps 3 ms, the USB bus may be assumed to have been placed in SUSPEND state. The SUSPEND state of the USB bus may be directly checked by monitoring the SUSPEND output (typically pin 12) of the Philips PDIUSBD12 device.
• SOF start of frame
• the SUSPEND status of the USB bus may be verified indirectly by monitoring in firmware the Suspend Change interrupts, step 202, which indicate that the bus is either going in or going out of SUSPEND mode. Because it is impossible to tell from a single Suspend Change interrupt whether the bus is going in or out of SUSPEND mode, a timer is set, step 204, to define a window during which the bus will be monitored for the presence of any data, step 206. If data is observed before the timeout of the timer, step 207, control is returned to block 202. If additional data is received before timeout, step 208, it may be assumed that the bus is not in SUSPEND mode. If, however, additional data is not received before timeout, step 208, the configuration of the USB device may be changed, step 210, so that SOF packets are no longer
• step 212 Another timer period is begun, step 212, and the USB bus is again monitored for data including SOF packets, step 214. If no data is received during this secondary time period, the assumption is made that the bus is in SUSPEND mode. The interface is then disconnected from the USB bus by forcing the D+ signal low, step 218.
• the firmware is typically running on the microcontroller to which USB interface 100 is attached. Alternatively, if the SUSPEND output of the USB device could be monitored directly, the system could proceed from step 202, above, to step 218, accomplishing the same result. Likewise, under certain situations, step 204 - 208 could be omitted.
• the interface 100 is logically removed from the bus by lowering the D+ signal, step 218.
• circuitry under software control of the firmware is used to virtually unplug the interface 100 from the USB bus.
• the host or hub must then reconfigure itself to a state absent the peripheral. After a predetermined amount of time, D+ may again be raised, step 220, thereby virtually plugging interface 100 back into the bus.
• the host/hub upstream must again reconfigure to add the peripheral device attached to interface 100. This action results in resetting at least the port on the host to which interface 100 is connected. Generally speaking, this action is sufficient to recover from an interface stoppage cause by a noise spike or other such spurious signal on the USB bus.
• the pull-up resistor 128 is implemented on the chip but is not permanently connected to a positive DC voltage 130.
• the connection is made upon execution of the command from the external microcontroller. This feature is known as SoftConnectTM in the

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• 2002
  • 2002-03-13 EP EP02725146A patent/EP1425674A1/de not_active Withdrawn
  • 2002-03-13 CA CA002459179A patent/CA2459179A1/en not_active Abandoned
  • 2002-03-13 WO PCT/US2002/007707 patent/WO2003023629A1/en not_active Application Discontinuation

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