EP1390941A1 - Controleurs graphiques et afficheurs a cristaux cholesteriques reflechissants bistables adresses par matrice active et modalites de mise en oeuvre - Google Patents

Controleurs graphiques et afficheurs a cristaux cholesteriques reflechissants bistables adresses par matrice active et modalites de mise en oeuvre

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Publication number
EP1390941A1
EP1390941A1 EP01968048A EP01968048A EP1390941A1 EP 1390941 A1 EP1390941 A1 EP 1390941A1 EP 01968048 A EP01968048 A EP 01968048A EP 01968048 A EP01968048 A EP 01968048A EP 1390941 A1 EP1390941 A1 EP 1390941A1
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EP
European Patent Office
Prior art keywords
data
status bits
pixels
pixel
ofthe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01968048A
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German (de)
English (en)
Inventor
Xaio-Yang Huang
Nick Martin Miller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kent Displays Inc
Original Assignee
Kent Displays Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/836,329 external-priority patent/US6850217B2/en
Priority claimed from US09/836,640 external-priority patent/US6816138B2/en
Priority claimed from US09/836,319 external-priority patent/US6819310B2/en
Application filed by Kent Displays Inc filed Critical Kent Displays Inc
Publication of EP1390941A1 publication Critical patent/EP1390941A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3651—Control of matrices with row and column drivers using an active matrix using multistable liquid crystals, e.g. ferroelectric liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0469—Details of the physics of pixel operation
    • G09G2300/0478—Details of the physics of pixel operation related to liquid crystal pixels
    • G09G2300/0482—Use of memory effects in nematic liquid crystals
    • G09G2300/0486—Cholesteric liquid crystals, including chiral-nematic liquid crystals, with transitions between focal conic, planar, and homeotropic states
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/04—Partial updating of the display screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/041—Temperature compensation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/10—Special adaptations of display systems for operation with variable images
    • G09G2320/103—Detection of image changes, e.g. determination of an index representative of the image change
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/022—Power management, e.g. power saving in absence of operation, e.g. no data being entered during a predetermined time

Definitions

  • the present invention relates generally to bistable, reflective Cholesteric displays. More specifically, the present invention relates to active matrix addressed bistable, reflective Cholesteric displays. Advantageously, a corresponding system and method of operation for driving the bistable, reflective Cholesteric displays are also disclosed.
  • LCD ' s Liquid crystal displays
  • LCD' s have been widely adapted for use in a number of products such as digital watches and clocks, laptop computers, and information and advertising display signs.
  • LCD' s are generally classified according to their drive scheme, e.g., passive matrix LCD' s and active matrix LCD's.
  • the display includes a thin layer of liquid crystal material sandwiched between two transparent panels.
  • An electrode array comprising a first set or plurality of parallel oriented electrode segments (row electrode segments) disposed on an inwardly facing side of one panel and a second set or plurality of parallel oriented electrode segments (column electrode segments) which are perpendicular to the row electrode segments disposed on an inwardly facing side of the other panel is provided.
  • the row and column electrode segments are spaced apart by spacer material and the liquid crystal material is filled in the spaced apart region between the panels.
  • Display picture elements or pixels are defined by regions of liquid crystal material adjacent the intersections of aligned electrodes of the horizontal and vertical electrode segments of the electrode array.
  • a pixel in a reflective display Upon application of a suitable electric field, a pixel in a reflective display will assume either a reflective or a non-reflective state.
  • a pixel, pij, formed at the overlapping or intersection of the ith row electrode and the jth column electrode is subject to an electric field resulting from the potential difference between a voltage applied to the ith row electrode segment and a voltage applied to the jth column electrode segment.
  • a pixel with a low reflectance will appear as a black area to the viewer. If the liquid crystal material has a light color appearance (such as yellow) in its highly reflective state, a pixel in a high reflectance state will appear to the viewer as an iridescent colored area on a black background.
  • a light color appearance such as yellow
  • Ch-LCD Bistable Cholesteric liquid crystal displays
  • display driver circuitry is coupled to the vertical and horizontal electrodes of the electrode array. Operating under the control of a logic and control unit, the display driver circuitry energizes the row and column electrodes with appropriate voltage waveforms such that an appropriate voltage across each pixel is generated. The voltage across a pixel will either cause it to remain in its present state of reflectance or change its state of reflectance.
  • the image generated by the display pixels may be modified by changing the state of selected pixels. In this way, text or image data can be presented for viewing.
  • FIGS, la and lb The dynamic and electro-optical responses of a typical, bistable reflective Ch-LCD are illustrated in FIGS, la and lb. As shown in FIG. la, an AC voltage in the form of pulses varying from 0V to 50V is applied to the display and the reflectance is plotted; in FIG. lb, reflectance is plotted as a function of time.
  • the reflectance is initially high, i.e., before any voltage is applied.
  • the display Upon the application of the voltage pulse, the display is switched into the Homeotropic State and the reflectance becomes very low. Once the voltage pulse is switched off, the reflectance gradually increases to the maximum.
  • the rise time of the display is about 250 ms, as illustrated in FIG. lb. It will be appreciated that in video applications, this long rise time will cause unpleasant image ghosting.
  • FIG. la More specifically, there are two initial (stable) states: the planar (higher reflectance) state and the focal conic (lower reflectance) state. It will also be noted that there are several threshold voltages.
  • the display When the applied voltage is below VI, the display will stay in either of its initial states after the pulse.
  • the reflectance of the initially ON display When the voltage increases from VI to V2, the reflectance of the initially ON display will decrease to a minimal value.
  • the reflectance of the initially OFF display begins to increase when the voltage is above V3 ' and the reflectance reaches the maximum when the voltage is above V4.
  • the reflectance of the initially ON display begins to increase its reflectance when the voltage is above V3 and the reflectance reaches the maximum when the voltage is above V4'. Therefore, for voltage between V2 and V3, the display is switched to the low Reflectance State regardless of its initial state; for voltage above V4, the display is switched to the high reflective state regardless of its initial state. Note that there are regions in the voltage response diagram, such as between VI and V2, where there exists stable partially reflecting states providing the opportunity for gray scale addressing.
  • Patent No. 5,748,277 and in the paper by X.Y. Huang et al. in the SID '95 Technical Digest, p. 347 (1995).
  • an active matrix addressed Cholesteric display is achieved by careful design of the drive scheme, implemented via the driver and controller, to thereby allow the Cholesteric display to maintain its superior optical performance, e.g., high brightness, high contrast, flicker-free viewing, and the low power bistability, i.e., only the pixels that need to be changed are updated.
  • the improved active matrix addressed bistable, reflective Cholesteric display according to the present invention advantageously provides a video rate compatible, scan-line free update capability.
  • the present invention provides a color display system, which includes a bistable liquid crystal display (LCD) for displaying a plurality of pixels arranged in a matrix, and circuitry which generates data corresponding to the pixels based on color data and status bits for each of the pixels.
  • the circuitry has a first mode of operation in which the data corresponding to the pixels is generated for each corresponding pixel and a second mode of operation in which no data is generated; the circuitry switches from the first operating mode to the second operating mode when all of the status bits for all of the pixels are zeros.
  • the present invention provides a low power color display system, including a bistable liquid crystal display (LCD) comprising a plurality of cells arranged in a matrix, each cell corresponding to a pixel, a memory which stores color data and status bits corresponding to all of the pixels, and circuitry which generates data corresponding to the pixels based on the color data and the status bits for each of the pixels.
  • a bistable liquid crystal display comprising a Cholesteric LCD.
  • the present invention provides a low power color display system, which includes a memory which stores color data and status bits corresponding to a plurality of pixels, status logic which generates the status bits responsive to receipt of color data for a respective one of the pixels, a data generator which generates voltage data corresponding to the pixels based on the color data and the status bits for each of the pixels, driver circuitry which generates voltage signals responsive to receipt of the voltage data for each of the pixels, and a bistable liquid crystal display (LCD) having multiple cells arranged in a matrix, each cell corresponding to a pixel, the LCD being responsive to the voltage signals.
  • LCD bistable liquid crystal display
  • the low power color display system also includes a power supply which provides power to the driver circuitry, and a power manager, the latter turning the power supply ON when the data generator is in the first operating mode and turning the power supply OFF when the data generator is in the second operating mode.
  • the low power color display system also includes status logic which decrements the status bits of a corresponding one of the pixels each time the voltage data for that corresponding pixel is generated by the data generator, and replaces the status bits with decremented status bits after the voltage data is output by the data generator.
  • the data generator generates the voltage data for a corresponding pixel N times to thereby permit application of the voltage signal corresponding to the pixel data to the LCD N time, where N is an integer established by the status bits.
  • the present invention provides graphics controller for a color display system having a bistable liquid crystal display (LCD) for displaying a plurality of pixels arranged in a matrix, the graphics controller including a memory device for storing color data and status bits corresponding to each of the pixels, and a generating device for generating voltage data corresponding to the pixels based on the color data and the status bits for each of the pixels.
  • the bistable LCD is a Cholesteric LCD.
  • the generating device has a first mode of operation in which the data corresponding to the pixels is generated for each corresponding pixel and a second mode of operation in which no data is generated; the generating device switches from the first operating mode to the second operating mode when all of the status bits for all of the pixels are zeros.
  • the present invention provides a graphics controller for a low power color display having a bistable liquid crystal display (LCD) including a plurality of cells arranged in a matrix, each cell corresponding to a pixel, including a memory which stores color data and status bits corresponding to all of the pixels, and circuitry which generates voltage data corresponding to the pixels based on the color data and the status bits for each of the pixels.
  • the circuitry Preferably, the circuitry generates the voltage data for a corresponding pixel when the status bits correspond to a non-zero binary number.
  • the circuitry has a first mode of operation in which the voltage data corresponding to the pixels is generated for each corresponding pixel and a second mode of operation in which no voltage data is generated, the circuitry switching from the first operating mode to the second operating mode when all of the status bits for all of the pixels are zeros.
  • the circuitry generates the data for a corresponding pixel N times to thereby permit application of the generated pixel data to the LCD N time, where N is an integer established by the status bits.
  • the present invention provides a graphics controller for a low power color display including a bistable liquid crystal display (LCD) having multiple cells arranged in a matrix, each cell corresponding to a pixel.
  • the graphics controller includes a memory which stores color data and status bits corresponding to a plurality of pixels, status logic which generates the status bits responsive to receipt of color data for a respective one of the pixels, a data generator which generates voltage data corresponding to the pixels based on the color data and the status bits for each of the pixels, and driver circuitry which generates voltage signals responsive to receipt of the voltage data for each of the pixels, wherein the LCD is responsive to the voltage signals produced by the driver circuitry.
  • the bistable LCD comprises a Cholesteric LCD.
  • the graphics controller includes a power supply which provides power to the driver circuitry, and a power manager which turns the power supply ON when the data generator is in a first operating mode and which turns the power supply OFF when the data generator is in a second operating mode.
  • the data generator cycles between the first and second operating modes based on the integer value of the status bits.
  • the graphics controller includes status logic which decrements the status bits of a corresponding one of the pixels each time the voltage data for that corresponding pixel is generated by the data generator, and replaces the status bits with decremented status bits after the voltage data is output by the data generator, permitting the data generator to generate the voltage data for a corresponding pixel N times and thereby permit application of the voltage signal corresponding to the pixel data to the LCD N time, where N is an integer established by the status bits.
  • the present invention provides an operating method for a color display system including an active matrix bistable liquid crystal display (LCD) having a plurality of pixels arranged in a matrix based on color data and status bits corresponding to each of the pixels stored in a memory.
  • the method includes steps for generating voltage data corresponding to the pixels based on the color data and the status bits stored for each of the pixels, converting the voltage data to drive signals suitable for driving the active matrix bistable LCD, and applying the drive signals to the active matrix bistable LCD.
  • the active matrix bistable LCD is a Cholesteric LCD.
  • the generating, converting, and applying steps are repeated for a corresponding pixel N times, where N is an integer established by the status bits.
  • the present invention provides an operating method for a color display system including an active matrix bistable liquid crystal display (LCD) having a plurality of pixels arranged in a matrix.
  • the method beneficially includes steps for storing color data and status bits corresponding to each of the pixels, generating voltage data corresponding to the pixels based on the color data and the status bits stored for each of the pixels, converting the voltage data to drive signals suitable for driving the active matrix bistable LCD, and applying the drive signals to the active matrix bistable LCD.
  • the active matrix bistable LCD is a Cholesteric LCD.
  • the generating, converting, and applying steps are repeated for a corresponding pixel N times, where N is an integer established by the status bits.
  • the present invention provides a method for operating a graphics controller including a memory, which stores color data and status bits corresponding to a plurality of pixels, coupled to a low power color display, which includes an active matrix bistable liquid crystal display (LCD) having a plurality of cells arranged in a matrix, each cell corresponding to respective one of the pixels, via driver circuitry, the LCD receiving drive signals suitable for driving the active matrix bistable LCD from the driver circuitry responsive to voltage data.
  • LCD active matrix bistable liquid crystal display
  • the method includes steps for generating the voltage data for each respective one of the pixels based on the color data and the status bits for that pixel, decrementing the status bits by 1 to thereby produce decremented status bits for that pixel, overwriting the status bits for that pixel with the decremented status bits, and repeating the generating, the decrementing, and the overwriting steps until the status bits stored in the memory for that pixel represent a zero value.
  • the method includes a step for setting the status bits to a predetermined value when the corresponding color data for a respective one of the pixels stored in the memory is replaced by new color data.
  • the present invention provides a method for operating a graphics controller including a memory, which stores color data and status bits corresponding to a plurality of pixels, coupled to a low power color display, which includes an active matrix bistable liquid crystal display (LCD) having a plurality of cells arranged in a matrix, each cell corresponding to respective one of the pixels, via driver circuitry, the LCD receiving drive signals suitable for driving the active matrix bistable LCD from the driver circuitry responsive to voltage data.
  • LCD active matrix bistable liquid crystal display
  • the method includes steps for generating the voltage data for each respective one of the pixels based on the color data and the status bits for each pixel having non- zero status bits, decrementing the status bits by 1 to thereby produce decremented status bits for each pixel having the non-zero status bits, overwriting the status bits with the decremented status bits for each pixel having the non-zero status bits, and repeating the generating, the decrementing, and the overwriting steps until the status bits stored in the memory for all of the pixels represent a zero value.
  • the method can include a step for generating a sleep signal when all of the status bits for all of the pixels represent zero values, where the driver circuitry has on and off states to thereby permit the driver circuitry to be switched from the on state to the off state responsive to the sleep signal.
  • the method can include a further step for step of setting the status bits to a predetermined value when corresponding color data for a respective one of the pixels is stored in the memory. It will be appreciated that, since the color data for all of the pixels need not be received during a single period, a first value represented by the status bits corresponding to a first one of the pixels need not be equal to a second value represented by the status bits corresponding to a second one of the pixels.
  • the method advantageously can include a step for examining the status bits stored in the memory.
  • the examining step is performed either prior to or concurrent with the generating step, and the generating step is modified to permit generating the voltage data for each respective one of the pixels having non-zero status bits based on the color data and the status bits for that pixel.
  • FIGS. 1 a and lb illustrate the dynamic and electro-optical response of a surface stabilized Cholesteric display with respect to variations in applied voltage and relaxation time, respectively;
  • FIG.2 illustrates the pixel waveforms of the pulses employed in driving the active matrix addressed Cholesteric display between its various states;
  • FIG.3 is a representational diagram illustrating the storage of both status and image data in a single frame buffer
  • FIG. 4 illustrates the row, column, and back plane (BP) voltage combination employed by the method according to the present invention
  • FIG.5 a illustrates the row, column and backplane waveforms corresponding to the pixels illustrated in FIG. 5b;
  • FIG. 6 illustrates circuitry employed in driving the active matrix addressed Cholesteric display according to the present invention
  • FIGS. 7a and 7b illustrate the dynamic and electro-optical response of a polymer stabilized finger-print cholesteric texture (PSFPCT) display with respect to variations in applied voltage and relaxation time, respectively; and
  • PSFPCT polymer stabilized finger-print cholesteric texture
  • FIGS.8a and 8b illustrate the dynamic and electro-optical response of a surface stabilized bistable cholesteric display with respect to variations in applied voltage and relaxation time, respectively.
  • the present invention provides an active matrix addressed Cholesteric display, e.g., the Ch-LCD.
  • Careful design of the drive scheme, implemented via the driver and controller, permits the Cholesteric display to maintain its superior optical performance, e.g., high brightness, high contrast, flicker-free viewing, and the low power bistability, i.e., only the pixels that need to be changed are updated.
  • the improved active matrix addressed bistable, reflective Ch-LCD according to the present invention advantageously provides a video rate compatible, scan-line free update capability.
  • the planar state exhibits high reflectivity and is commonly referred to as the ON state.
  • the focal conic state has low reflectivity and is, in contrast, referred to as the OFF state.
  • the planar state appears in some pre-selected color, e.g., yellow, while the focal conic state appears to be black.
  • the amount of light reflected from the planar state can be adjusted to achieve different shades of a particular reflected color or gray levels.
  • This feature makes possible a full-color display as described in publication "Full color (4096) reflective cholesteric liquid crystal display" by Huang et.al. Asia Display '98 Technical Digest, p883.
  • a full-color display is made by stacking three display cells, each of a different primary color, red, green and blue with the black background painted on the back substrate ofthe bottom cell.
  • the display could be switched from the planar state to the focal conic state directly by application of a suitable pulse having a proper magnitude as characterized by voltage level and time duration or pulse width.
  • a suitable pulse having a proper magnitude as characterized by voltage level and time duration or pulse width.
  • the display cannot be switched from the focal conic state to the planar state directly. Instead, a large magnitude pulse is first applied to the cells ofthe display in the focal conic state to thereby align the liquid crystal in the selected cells to the Homeotropic State, which is then switched OFF quickly. It will be appreciated that the liquid crystal material first relaxes into the transient planar state in about 1 ms, and then more slowly to the planar state.
  • a typical voltage pulse would be about 10 ms in duration, which would permit the Cholesteric liquid crystal to relax into the planar state approximately 100-300 ms after the pulse has been terminated.
  • each effected pixel in the Ch-LCD changes from black to a state with a predetermined reflectivity.
  • the data voltage difference between the ON and OFF states is limited. Therefore, all the pixels in a row are selected, independent of their previous image state, and the voltage pulse with suitable magnitude is applied according to the desired final state ofthe pixel, i.e., a relatively low magnitude for the focal conic state and a relatively high magnitude for the planar state.
  • the relatively low magnitude immediately drives each pixel in the row to the focal conic state and the pixel appears black.
  • the relatively high magnitude drives the pixel to the Homeotropic State in which each pixel also appears to be black. Therefore, the whole selected row appears black.
  • the maximum drive speed for this one-line-at-a-time drive scheme is approximately 5 ms/row.
  • the users can actually see a black line scan down the screen.
  • the average row selection time can be reduced to about 1 ms/row.
  • the user will still see a black band; the black line is just sweeping down the screen at a faster rate.
  • the cumulative drive scheme is able to remove the black scan line by scanning the screen, or at least a selected portion ofthe screen, repetitively at a high refresh rate, i.e., greaterthan40 scans/second. Due to image retention characteristic ofthe human eye, the black scanning line disappears.
  • the maximum driver voltage, maximum data voltage and the material response time limits the row selection time to about 2 ms/row, which is equivalent to eight rows at a 60Hz scanning rate.
  • the limited number of rows that advantageously can be driven while avoiding the characteristic black scan line of Ch-LCD' s implies that this passive matrix drive scheme can only be of benefit in a limited number of specific applications.
  • an active matrix display can be conceptualized as a matrix display in which each pixel ofthe display advantageously can be switched ON and OFF independently. Examples of active matrix displays are disclosed in U.S. Patent Nos. 4,042,854, 4,062,626, 4,404,555, and 4,717,244, to name but a few.
  • a voltage is always applied to maintain the pixels at the selected ON or OFF state.
  • the Ch-LCD according to the present invention implements a three-state drive method for an active matrix display. The three states are:
  • the high or low pulse is applied repetitively with a time interval depending on the frame rate. If the frame rate is 60Hz, the interval is 16.7 ms. If the frame rate is
  • the interval is 33.3 ms. 2.
  • the width and the number ofthe pulses depend on the material response time. The goal is for the pixels that need to be switched from OFF to ON, during the last pulse the whole pixel should be switched to the homeotropic state; for the pixels that need to be switched from ON to OFF, during the last pulse, the whole pixel should be switched to the focal conic state.
  • the pixel voltages are turned OFF at the end of each frame to reduce the operation voltage of driver cost in the frame inversion scheme.
  • the voltage difference between the ON and OFF waveform is not as limited as that ofthe passive matrix drive. 5.
  • the cumulative effect of the display is also used so that the pixel can be completely switched in several frames. However, once the destination state is achieved, the voltage applied to the pixel is zero. This can significantly reduce the power consumption.
  • the use ofthe active matrix enables the whole display to be updated almost at the same time.
  • the pixel voltage level is changed inside a frame time. Therefore, modifications in the drive control circuitry are needed.
  • the row driver there are two states in the row driver, i.e., select and non-select, for an active matrix display.
  • the row data only needs to be 1 bit.
  • the column drive needs to have three states: ON, OFF, and NC (no change).
  • the column driver requires two data bits in order to select between the three states.
  • the column driver advantageously receives both pixel image data and pixel status data.
  • An exemplary image array block representing storage of these data bits is shown in FIG. 3.
  • the frame buffer data includes both 24 bits of image data, permitting display in excess of one million colors in the resultant image, and 3 bits of status data.
  • colors are represent by three groups each having 8 bits representing 256 gray levels for each color, which requirement dictates that the column driver are amplitude modulated.
  • the 3 bits of status data allow as many as 8 frames to update an image. In other words, for every frame advance the status bits are decrement by 1 bit; once the status bits are cleared, NC state is assumed, and no further updates occur to the pixel. Moreover, once the pixel has been changed, all status bits are set to l's.
  • the status bits advantageously can be employed in connection with erase cycles to enhance the contrast and the gray scale accuracy.
  • FIG.4 shows the row, column and back plane (BP) voltage combination, assuming 40V for ON and 30V for OFF, provided by the drive circuitry according to the present invention, which drive circuitry will be discussed in greater detail below.
  • the row voltage for selection is preferably about 5 V and, most preferably, at least 5 V higher than column voltage.
  • the row, column and backplane voltages need to be arranged as shown in FIG.5a to drive the pixel pattern illustrated in FIG. 5b.
  • pixel 11 is switched from OFF to ON and Pixel 22 is switched from ON to OFF.
  • Pixel 12 and Pixel 21 are maintained in their previous state, i.e., no change.
  • each row is selected twice. More specifically, the first selection, i.e., pulse, advantageously can be employed to charge the pixel according to the image data and pixel status while the second selection is used to discharge the pixel to zero voltage with respect to the back plane voltage. Therefore, the column voltage during the first selection should reflect the pixel image data and pixel status, and the column voltage during the second selection should be set as NC (no change) so as to discharge the pixel.
  • the first selection i.e., pulse
  • NC no change
  • the time difference between the two selection pulses defines the pulse width.
  • the pulse width should be kept as short as possible so that the Cholesteric material can have time to relax to the desired state.
  • One preferred embodiment ofthe drive circuitry according to the present invention will now be described in detail with reference to FIG. 6. However, before the discussion of the embodiment is presented, it would be helpful to provide some additional general discussion. In particular, it should be mentioned that combining an active matrix-addressing scheme with a bistable reflective Cholesteric liquid crystal display (Ch-LCD) could significantly improve the response speed ofthe display. Moreover, active matrix addressing ofthe Ch-LCD advantageously maintains the lower power advantage offered by its bistability and reflective viewing characteristic ofthe Ch-LCD.
  • controller design is predicated on the concept that, unlike existing active matrix displays, the drive circuitry for the active matrix Ch-LCD can be completely shut down when the image does not need to be changed. It will be appreciated that the power consumption of the active matrix Ch-LCD is extremely low with respect to other LCD's currently available in the market.
  • FIG. 6 is a high-level block diagram of an active matrix Ch-LCD system 1 according to the present invention.
  • the display system 1 includes an active matrix Ch-LCD 100, row (gate) and column (data) drivers 200, a back plane driver 300, a power supply 400 for the above- mentioned drivers, and the controller 500.
  • the controller 500 receives both commands and image data from a processor 600, which processor will be discussed in greater detail below.
  • the power supply 400 powering the drivers 200, 300 is controlled by the controller 500 for the efficient power management.
  • the power supplied to the drivers 200, 300 by the power supply 400 is active; during the sleep mode, the power provided to the drivers 200, 300 is removed completely.
  • An exemplary embodiment of the controller 500 according to the present invention includes a memory 502, which advantageously can be partitioned into image memory 502a and status memory 502b.
  • the memory 502 is a static random access memory; alternatively, other types of non-volatile memory, e.g., ferromagnetic random access memory (FRAM), advantageously can be employed. It will be appreciated that a non- volatile memory is preferred, since this type of memory complements the low power characteristic ofthe Ch-LCD 100.
  • the controller 500 includes a status manager 504, which receives commands via the control / status input/output (I/O) port 506 and which receives data via the data I/O port 508 and a buffer 510.
  • I/O input/output
  • buffer 510 facilitates the writing of data into memory 502a under control of a memory arbiter 512 driving address counter 514.
  • the commands received via I/O port 506 are also applied to command decoder 516.
  • the controller includes a power manager 518, which commands the startup and/or shutdown ofthe power supply 400.
  • the image data is read out of memory 502 by column data generator 520 and row data generator 522 in accordance with timing signals produced by the display timing circuit 524.
  • the display timing is influenced by the temperature ofthe display 100, as discussed in greater detail below.
  • the preferred embodiment ofthe controller 500 advantageously can be constructed from several ICs, such as an SRAM, an Altera programmable logic, and a National Semiconductor COP8, a power supply chip set, and some other discrete components.
  • FIG. 6 is a functional block diagram, i.e., FIG. 6 illustrates functions, not discrete components, which functions are discussed in greater detail below. A detailed description of each of these functions is provided below.
  • the Power Manager (function block) 518 advantageously oversees the power supply to the active matrix Ch-LCD system 1.
  • a "wake up" generated by the host 600 will toggle at least the controller 500 ofthe active matrix Ch-LCD system 1 into the high power awake mode.
  • the signal from the Status Manger 504 can determine whether to continue operation in the power consuming awake mode or to power down to the power conserving sleep mode.
  • the I/O port 506 permits receipt of commands from the host 600 to the controller 500.
  • the status if the controller i.e., Sleep mode, Busy mode, and Awake mode, advantageously can be sensed by the host 600 via this port.
  • the controller status can be detected by the host from this port.
  • the I/O port 508 and buffer 510 receives and buffers the data or commands provided on lines
  • the command decoder 516 which advantageously could be a section of logic in a larger logic device, decodes commands received from the host 600, which commands control the overall operation ofthe active matrix Ch-LCD system 1, e.g., brightness control, frame rate adjustment, image SRAM allocation, etc.
  • the display timing circuit 524 which again may be a section of a larger device, provides all necessary timing signals for controller 500 and display 100 operation, e.g., column shift clock, row shift clock, frame, data latch, SRAM clock, etc.
  • the address counter 514 access the SRAM memory 502a in response to timing signal from the display timing circuit 524.
  • some ofthe clock frequencies are temperature dependent.
  • access to/from the SRAM memory 502a necessitates the presence of a memory arbitrator 512.
  • This section of logic accommodates memory access priority and resolves any possible conflicts between the host 600 and display driver 200, 300 demand for memory 502 access. It will be appreciated that, in any active matrix addressing scheme, display scanning can not be stopped while the host 600 accesses (read from or writes to) memory 502; the host 600 can only access the memory 502 while the drivers 200, 300 are not demanding data.
  • the memory 502 advantageously includes both an image SRAM 502a and a status SRAM 502b.
  • the image SRAM 502a provides the memory required for storing the display image, pixel by pixel.
  • the display 100 displays 16 level of gray scale for each layer in a three-layer full color display. Therefore, each pixel corresponds to 12 data bits.
  • the memory 502a advantageously provides a low power standby mode so that the display image can be stored in the low power sleep mode.
  • the status SRAM 50b advantageously can be employed to the pixel status information needed for the active matrix-addressing scheme according to the present invention.
  • a complete update of a pixel will take 16 frames, which can be represented by 4 data bits.
  • all of its corresponding status bits preferably are set to Al ". For every frame in which image data is provided to the active matrix Ch-LCD 100, the status bits are decremented by 1.
  • the status manager 504 provides logic functions with respect to: setting status bits to l's in the status SRAM 502b when a pixel is changed by the host 600; decrementing the status bits by 1 and storing the decremented status bits back into the status SRAM 502b after every frame update; monitoring the status SRAM 502b to determined whether there is any pixel in the memory needing to be updated further; and issuing the power down signal to the power manager 518.
  • the controller 500 advantageously includes both a column data generator 520 and a row data generator 522.
  • the logic incorporated into the column data generator 520 takes image data, frame, and the status bits and forms the column voltage data which is to be applied to the row /column driver 200. If the status bits are zero, the column voltage should be the same as the back plane voltage. If the status bits are not zero, this logic device, i.e., the column data generator 520, will form the voltage data needed to update each pixel.
  • the data generator 520 advantageously can include a lookup table (LUT) or comparable device for using the values stored in memories 520a, 502b as addresses to predetermined values which are to be output by data generator 520.
  • LUT lookup table
  • the data generator 520 provides the capability to implement more complicated multistage drive schemes by, for example, varying the values stored in the LUT.
  • the row data generator 522 permits row voltage data to be generated according to the frame and drive progress of each frame.
  • Ch-LCD Ch-LCD 's are very sensitive to the temperature, especially in gray scale implementation, hi the exemplary embodiment ofthe present invention illustrated in FIG. 6, it will be appreciated that temperature data derived from the substrate of the controller 500 advantageously can be employed to determine the drive voltage, pulse width, and even updating frequency ofthe controller 500, providing the display and the controller are in thermal contact and their temperatures are very close to one another.
  • nRes 0 to reset the complete controller to its default state.
  • 0 D/nC Indicates the D0 ⁇ D7 is data or command from host.
  • the essential functionality provided by the controller 500 illustrated in FIG. 6 is summarized immediately below. 5 1.
  • the controller 500 advantageously can be in the Sleep Mode. 2.
  • Minimal power is drained in maintaining the image data in the SRAM 502a and in monitoring the interface activity, i.e., I/O ports 506 and 508.
  • the host e.g., central processing unit (CPU)
  • the power manager circuitry 518 advantageously will wake up the controller 500 by driving the nWk line low.
  • the controller 500 advantageously can start to respond to commands and accept the new image data from host 600.
  • the controller 500 starts to update the display 100.
  • the controller 500 powers down and returns to the Sleep Mode. 7.
  • the controller 600 will stay in the Sleep Mode until the host 600, e.g., a computer, again wakes up the controller, i.e., until the host computer applies a predetermined "wake up" signal to the controller.
  • the drive- when-changed operating method ofthe controller requires status bits associated with every displayed pixel in addition to the data corresponding to that pixel.
  • the controller must employ "Status Manger" logic to direct the controller with respect to the employment ofthe status bits.
  • a pixel when a pixel is changed in image memory, i.e., image SRAM, 502a, that pixel's related status bits are all set to a predetermined value, e.g., all 1 's, by the status manager 504. For each frame in which the pixel is driven, the status bits is decremented by 1 and written back to the status SRAM 502b. Once the status bits corresponding to a particular pixel in the image data are counted down to zero, the related pixel will not be driven any more, i.e., zero voltage will be applied to that pixel with respect to the back plane.
  • the status manager 504 advantageously can monitor whether or not any particular pixel needs to be updated, i.e., the status manager 504 simply checks to determine if there are any non-zero status bits after each frame has been updated. If there is no pixel requiring an update, the status manager 504 informs the power manager 518 of the controller 500, which power manager cycles controller 500into the Sleep mode of operation.
  • the three state active matrix drive scheme or method can significantly improve the update speed of Ch-LCD while maintaining the bistability for low power operation. This drive method can be also extended to full color gray scale application. With the removal of cross talk voltage afforded by the active matrix driving scheme, the power consumption advantageously can be even lower than the passive matrix display in the page update mode.
  • the operating characteristic ofthe Ch-LCD 100 advantageously can be tailored to permit operation ofthe Ch- LCD 100 with a reduced VI threshold.
  • the display 100 can be a Polymer stabilized finger-print cholesteric texture (PSFPCT) display or a Ch-LCD having a strong homeotropic alignment layer with a lower V 1 threshold of the display.
  • PSFPCT Polymer stabilized finger-print cholesteric texture
  • PSFPCT polymer stabilized finger-print cholesteric texture
  • U.S. Patent No. 5,570,216 and described in a paper entitled “Bistable Reflective Cholesteric Liquid Crystal Display” (J. Appl. Phys. 81(3), (1 February 1997)), by Min-Hua Lu.
  • This display can be fabricated by mixing a predetermined percentage of monomer with the cholesteric liquid crystal mixture. After vacuum filling the display, the display is heated to the isotropic state, and is then slowly cooled down to the room temperature. In this manner, a large domain focal conic fan texture is formed during the cooling with the assistance of a side chain polyimide alignment layer. UV curing is facilitated without any external electric field.
  • the polymer networks are locked into the large domain fan texture. With proper polymer selection and concentration, the display exhibits fast homeotropic to planar transition, e.g., on the order of 10 ms.
  • Several test displays fabricated according to the procedure set forth above have been characterized as have a repeatable rise time of approximately 10 ms.
  • Figs 7a and 7b illustrate the dynamic response and the switching response, respectively, of a typical PSFPCT cell. It will be noticed that this display also has very good black state. It will also be noted that the VI threshold for this cell is so low that the driving of such a display using a passive matrix drive scheme is not possible.
  • a typical surface stabilized bistable cholesteric display can be made according to method described in U.S. Patent No. 5,453,863 by Yang and West.
  • the alignment layer has too strong of a homeotropic alignment effect, the display will exhibit a low VI threshold value, meaning that the device can not be driven by the passive matrix method.
  • this kind of device also exhibits a very fast homeotropic-to-planar (H-P) transition.
  • the dynamic response and the electro-optical response, respectively, are shown in FIGS. 8a and 8b. It will be appreciated from their figures that the rise time in the H-P transition is about 10 ms and the hysteresis between V3 and V3', V4 and V4' is very small. It should be mentioned that the advantage of this device is that it does not require a polymer network. This can significantly simplify the manufacturing process and improve the display reliability.
  • the active matrix driving method according to the present invention can fundamentally resolve any limitation on the V 1 value relative to the ON and OFF voltage values .
  • the drive voltage on the selected rows are not seen by any ofthe non-selected rows.
  • the state ofthe non-selected rows is not effected by the driving the pixels in the selected row.
  • This enables the selection of materials, display process parameters, surface treatment, etc., without regard to cell crosstalk.
  • the very attractive features of a Ch-LCD with low VI threshold while not particularly suitable for existing passive matrix driving methods, provides a display with a fast H-P transition, which satisfies a key requirement for displays employed in video rate applications.
  • the active matrix Ch-LCD system 1 advantageously can be employed as the display of such a devices as personal digital assistants (PDAs), electronic books (e-books), advertising displays, etc.
  • PDAs personal digital assistants
  • e-books electronic books
  • the active matrix Ch-LCD system can be adapted to accept inputs from devices such as desktop and laptop computers, particularly the latter.
  • the graphics subsystem ofthe typical computer generates data sufficient to update the display at 30 or more frames per second. Since much of this data does not vary from frame to frame, providing such repetitive pixel data to the active matrix Ch-LCD system according to the present invention would be counter productive.
  • the logic provided by the status manager 504 can be augmented with comparison logic. In that case, data provided to the status manager can be compared with the data already stored in image SRAM 502a; only new color data would be written to memory 502a and, consequently, only the status bits corresponding to the new color data would be changed.
  • the active matrix Ch-LCD system 1 is not limited to the specific embodiments discussed above.
  • multiple ones of row /column drivers 200 advantageously can be included so that rows 1-50 are driven by row / column driver 200a, rows 51-100 are driven by row / column driver 200b, etc.

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  • Crystallography & Structural Chemistry (AREA)
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Abstract

La présente invention concerne un système d'afficheur couleur basse énergie (1) équipé d'une mémoire (502) conservant des données de couleur et des bits d'état correspondant à une pluralité de pixels, d'une logique d'états (504) qui positionne les bits d'état à la réception des données de couleurs des différents pixels, d'un générateur de données (520, 522) produisant des données de tension correspondant aux pixels sur la base des données de couleur et des bits d'états des différents pixels, d'une logique de pilote (200) qui produit des signaux en tension en réaction à la réception des données de tension de chacun des pixels, et un afficheur à cristaux liquides bistables (100) dont les différentes cellules sont agencées en une matrice à raison d'une cellule pour chaque pixel, l'afficheur à cristaux liquides réagissant aux signaux en tension. Le système comprend également de préférence une alimentation électrique (400) qui fournit l'énergie à la logique de pilote (200) et un gestionnaire d'alimentation (518) mettant en fonction l'alimentation lorsque le générateur de données est dans le premier mode de fonctionnement, et arrêtant l'alimentation lorsque le générateur de données est dans le second mode de fonctionnement. Le générateur de données (520, 522) produit les données de tension N fois pour un même pixel de façon à permettre l'application N fois à l'afficheur cristaux liquides du signal en tension correspondant aux données de pixel, N étant un entier défini par les bits d'état.
EP01968048A 2001-04-18 2001-09-12 Controleurs graphiques et afficheurs a cristaux cholesteriques reflechissants bistables adresses par matrice active et modalites de mise en oeuvre Withdrawn EP1390941A1 (fr)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US836640 1992-02-18
US836329 2001-04-18
US09/836,329 US6850217B2 (en) 2000-04-27 2001-04-18 Operating method for active matrix addressed bistable reflective cholesteric displays
US09/836,640 US6816138B2 (en) 2000-04-27 2001-04-18 Graphic controller for active matrix addressed bistable reflective cholesteric displays
US09/836,319 US6819310B2 (en) 2000-04-27 2001-04-18 Active matrix addressed bistable reflective cholesteric displays
PCT/US2001/026017 WO2002086855A1 (fr) 2001-04-18 2001-09-12 Controleurs graphiques et afficheurs a cristaux cholesteriques reflechissants bistables adresses par matrice active et modalites de mise en oeuvre
US836319 2004-04-30

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WO2006051273A1 (fr) 2004-11-10 2006-05-18 Magink Display Tecnologies Ltd. Schema d'excitation pour un ecran a cristaux liquides cholesteriques
GB0520763D0 (en) * 2005-10-12 2005-11-23 Magink Display Technologies Cholesteric liquid crystal display device
EP1785982A1 (fr) * 2005-11-14 2007-05-16 Texas Instruments Incorporated Gestion d'alimentation de l'affichage
ATE528377T1 (de) 2008-03-05 2011-10-15 Merck Patent Gmbh Flüssigkristallines medium und flüssigkristallanzeige mit verdrehtem garn
US8436847B2 (en) 2009-12-02 2013-05-07 Kent Displays Incorporated Video rate ChLCD driving with active matrix backplanes
ES2373702B1 (es) * 2010-04-28 2012-12-28 Javier Espinosa Campoy Sistema electrónico de cambio de color para complementos de moda y accesorios.
EP2399972B1 (fr) 2010-06-25 2015-11-25 Merck Patent GmbH Support à base de cristaux liquides et affichage à base de cristaux liquides disposant d'une haute torsion
WO2012174681A1 (fr) * 2011-06-24 2012-12-27 Intel Corporation Techniques de contrôle de consommation d'énergie d'un système

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ES2040258T3 (es) * 1986-09-20 1993-10-16 Thorn Emi Plc Dispositivo de pantalla.
EP0591683B1 (fr) * 1992-09-04 1998-12-16 Canon Kabushiki Kaisha Dispositif et méthode de commande d'affichage
US6078304A (en) * 1994-10-24 2000-06-20 Miyazawa; Kuniaki Panel type color display device and system for processing image information
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