EP1383050A1 - Procédé et appareil de détection d'entrées doubles dans une table à consulter - Google Patents
Procédé et appareil de détection d'entrées doubles dans une table à consulter Download PDFInfo
- Publication number
- EP1383050A1 EP1383050A1 EP03019505A EP03019505A EP1383050A1 EP 1383050 A1 EP1383050 A1 EP 1383050A1 EP 03019505 A EP03019505 A EP 03019505A EP 03019505 A EP03019505 A EP 03019505A EP 1383050 A1 EP1383050 A1 EP 1383050A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- code
- equal
- logical sum
- bits
- column
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/1016—Error in accessing a memory location, i.e. addressing error
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5002—Characteristic
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Detection And Correction Of Errors (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/488,816 US5652580A (en) | 1995-06-09 | 1995-06-09 | Method and apparatus for detecting duplicate entries in a look-up table |
US488816 | 1995-06-09 | ||
EP96918285A EP0843852B1 (fr) | 1995-06-09 | 1996-06-07 | Procede et appareil de detection d'entrees doubles dans une table a consulter |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP96918285A Division EP0843852B1 (fr) | 1995-06-09 | 1996-06-07 | Procede et appareil de detection d'entrees doubles dans une table a consulter |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1383050A1 true EP1383050A1 (fr) | 2004-01-21 |
EP1383050B1 EP1383050B1 (fr) | 2008-02-06 |
Family
ID=23941242
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP03019505A Expired - Lifetime EP1383050B1 (fr) | 1995-06-09 | 1996-06-07 | Procédé et appareil de détection d'entrées doubles dans une table à consulter |
EP96918285A Expired - Lifetime EP0843852B1 (fr) | 1995-06-09 | 1996-06-07 | Procede et appareil de detection d'entrees doubles dans une table a consulter |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP96918285A Expired - Lifetime EP0843852B1 (fr) | 1995-06-09 | 1996-06-07 | Procede et appareil de detection d'entrees doubles dans une table a consulter |
Country Status (5)
Country | Link |
---|---|
US (1) | US5652580A (fr) |
EP (2) | EP1383050B1 (fr) |
JP (2) | JP3920336B2 (fr) |
DE (2) | DE69629823T2 (fr) |
WO (1) | WO1996042052A1 (fr) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7328203B2 (en) * | 2004-12-16 | 2008-02-05 | International Business Machines Corporation | System and method for executing complex if-then clauses |
US7761774B2 (en) * | 2005-10-28 | 2010-07-20 | Qualcomm Incorporated | High speed CAM lookup using stored encoded key |
US8001432B2 (en) * | 2008-11-20 | 2011-08-16 | Lsi Corporation | Uninitialized memory detection using error correction codes and built-in self test |
JP4945618B2 (ja) * | 2009-09-18 | 2012-06-06 | 株式会社東芝 | A/dコンバータ |
US8787059B1 (en) * | 2011-12-05 | 2014-07-22 | Netlogic Microsystems, Inc. | Cascaded content addressable memory array having multiple row segment activation |
US10037190B2 (en) | 2016-03-24 | 2018-07-31 | International Business Machines Corporation | Transformation on input operands to reduce hardware overhead for implementing addition |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3963908A (en) * | 1975-02-24 | 1976-06-15 | North Electric Company | Encoding scheme for failure detection in random access memories |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4547882A (en) * | 1983-03-01 | 1985-10-15 | The Board Of Trustees Of The Leland Stanford Jr. University | Error detecting and correcting memories |
JPS6476596A (en) * | 1987-09-18 | 1989-03-22 | Oki Electric Ind Co Ltd | Error of eeprom detecting device |
US5220526A (en) * | 1991-03-01 | 1993-06-15 | Motorola, Inc. | Method and apparatus for indicating a duplication of entries in a content addressable storage device |
-
1995
- 1995-06-09 US US08/488,816 patent/US5652580A/en not_active Expired - Lifetime
-
1996
- 1996-06-07 JP JP50317797A patent/JP3920336B2/ja not_active Expired - Fee Related
- 1996-06-07 EP EP03019505A patent/EP1383050B1/fr not_active Expired - Lifetime
- 1996-06-07 WO PCT/US1996/009369 patent/WO1996042052A1/fr active IP Right Grant
- 1996-06-07 EP EP96918285A patent/EP0843852B1/fr not_active Expired - Lifetime
- 1996-06-07 DE DE69629823T patent/DE69629823T2/de not_active Expired - Lifetime
- 1996-06-07 DE DE69637427T patent/DE69637427T2/de not_active Expired - Lifetime
-
2006
- 2006-11-13 JP JP2006306907A patent/JP3996623B2/ja not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3963908A (en) * | 1975-02-24 | 1976-06-15 | North Electric Company | Encoding scheme for failure detection in random access memories |
Also Published As
Publication number | Publication date |
---|---|
US5652580A (en) | 1997-07-29 |
JP3920336B2 (ja) | 2007-05-30 |
DE69637427T2 (de) | 2009-01-29 |
DE69629823D1 (de) | 2003-10-09 |
WO1996042052A1 (fr) | 1996-12-27 |
JP3996623B2 (ja) | 2007-10-24 |
EP1383050B1 (fr) | 2008-02-06 |
JP2007087413A (ja) | 2007-04-05 |
DE69629823T2 (de) | 2004-05-13 |
DE69637427D1 (de) | 2008-03-20 |
JPH11515118A (ja) | 1999-12-21 |
EP0843852B1 (fr) | 2003-09-03 |
EP0843852A1 (fr) | 1998-05-27 |
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