EP1383050A1 - Procédé et appareil de détection d'entrées doubles dans une table à consulter - Google Patents

Procédé et appareil de détection d'entrées doubles dans une table à consulter Download PDF

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Publication number
EP1383050A1
EP1383050A1 EP03019505A EP03019505A EP1383050A1 EP 1383050 A1 EP1383050 A1 EP 1383050A1 EP 03019505 A EP03019505 A EP 03019505A EP 03019505 A EP03019505 A EP 03019505A EP 1383050 A1 EP1383050 A1 EP 1383050A1
Authority
EP
European Patent Office
Prior art keywords
code
equal
logical sum
bits
column
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP03019505A
Other languages
German (de)
English (en)
Other versions
EP1383050B1 (fr
Inventor
Nirmal R. Saxena
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP1383050A1 publication Critical patent/EP1383050A1/fr
Application granted granted Critical
Publication of EP1383050B1 publication Critical patent/EP1383050B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016Error in accessing a memory location, i.e. addressing error
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C15/00Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5002Characteristic

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Detection And Correction Of Errors (AREA)
EP03019505A 1995-06-09 1996-06-07 Procédé et appareil de détection d'entrées doubles dans une table à consulter Expired - Lifetime EP1383050B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/488,816 US5652580A (en) 1995-06-09 1995-06-09 Method and apparatus for detecting duplicate entries in a look-up table
US488816 1995-06-09
EP96918285A EP0843852B1 (fr) 1995-06-09 1996-06-07 Procede et appareil de detection d'entrees doubles dans une table a consulter

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
EP96918285A Division EP0843852B1 (fr) 1995-06-09 1996-06-07 Procede et appareil de detection d'entrees doubles dans une table a consulter

Publications (2)

Publication Number Publication Date
EP1383050A1 true EP1383050A1 (fr) 2004-01-21
EP1383050B1 EP1383050B1 (fr) 2008-02-06

Family

ID=23941242

Family Applications (2)

Application Number Title Priority Date Filing Date
EP03019505A Expired - Lifetime EP1383050B1 (fr) 1995-06-09 1996-06-07 Procédé et appareil de détection d'entrées doubles dans une table à consulter
EP96918285A Expired - Lifetime EP0843852B1 (fr) 1995-06-09 1996-06-07 Procede et appareil de detection d'entrees doubles dans une table a consulter

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP96918285A Expired - Lifetime EP0843852B1 (fr) 1995-06-09 1996-06-07 Procede et appareil de detection d'entrees doubles dans une table a consulter

Country Status (5)

Country Link
US (1) US5652580A (fr)
EP (2) EP1383050B1 (fr)
JP (2) JP3920336B2 (fr)
DE (2) DE69629823T2 (fr)
WO (1) WO1996042052A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7328203B2 (en) * 2004-12-16 2008-02-05 International Business Machines Corporation System and method for executing complex if-then clauses
US7761774B2 (en) * 2005-10-28 2010-07-20 Qualcomm Incorporated High speed CAM lookup using stored encoded key
US8001432B2 (en) * 2008-11-20 2011-08-16 Lsi Corporation Uninitialized memory detection using error correction codes and built-in self test
JP4945618B2 (ja) * 2009-09-18 2012-06-06 株式会社東芝 A/dコンバータ
US8787059B1 (en) * 2011-12-05 2014-07-22 Netlogic Microsystems, Inc. Cascaded content addressable memory array having multiple row segment activation
US10037190B2 (en) 2016-03-24 2018-07-31 International Business Machines Corporation Transformation on input operands to reduce hardware overhead for implementing addition

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3963908A (en) * 1975-02-24 1976-06-15 North Electric Company Encoding scheme for failure detection in random access memories

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4547882A (en) * 1983-03-01 1985-10-15 The Board Of Trustees Of The Leland Stanford Jr. University Error detecting and correcting memories
JPS6476596A (en) * 1987-09-18 1989-03-22 Oki Electric Ind Co Ltd Error of eeprom detecting device
US5220526A (en) * 1991-03-01 1993-06-15 Motorola, Inc. Method and apparatus for indicating a duplication of entries in a content addressable storage device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3963908A (en) * 1975-02-24 1976-06-15 North Electric Company Encoding scheme for failure detection in random access memories

Also Published As

Publication number Publication date
US5652580A (en) 1997-07-29
JP3920336B2 (ja) 2007-05-30
DE69637427T2 (de) 2009-01-29
DE69629823D1 (de) 2003-10-09
WO1996042052A1 (fr) 1996-12-27
JP3996623B2 (ja) 2007-10-24
EP1383050B1 (fr) 2008-02-06
JP2007087413A (ja) 2007-04-05
DE69629823T2 (de) 2004-05-13
DE69637427D1 (de) 2008-03-20
JPH11515118A (ja) 1999-12-21
EP0843852B1 (fr) 2003-09-03
EP0843852A1 (fr) 1998-05-27

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