Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
  • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
  • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
  • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
  • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
  • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
  • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
  • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
  • G09G3/293—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for address discharge

Definitions

• the present invention relates to plasma screens and more particularly to the control of the cells of a plasma screen.
• a plasma screen is a matrix type screen, formed of cells arranged at the intersections of rows and columns.
• a cell comprises a cavity filled with a rare gas, and at least two control electrodes.
• the cell is selected by applying a potential difference between the control electrodes, then an ionization of the gas in the cell is triggered, generally by means of a third control electrode. This ionization is accompanied by an emission of ultraviolet rays.
• the creation of the light point is obtained by excitation of a red, green or blue luminescent material by ultraviolet rays.
• FIG. 1 represents a conventional plasma screen structure formed by cells 2. Each cell 2 has two control electrodes (not shown) respectively connected to a line 4 and to a column 6. Each cell 2 is represented by its equivalent capacity .
• a line control circuit 8 comprises, for each line 4, a line activation / inactivation block 10, one output of which is connected to the line considered.
• a column control circuit 12 comprises, for each column 6, a column control block 14 of which an output terminal O is connected to the column 6 considered.
• Each block 14 includes an input terminal E.
• the circuit 12 also includes a storage register 16 connected to receive column control signals (COL) from means not shown.
• the register 16 includes as many outputs Q as there are blocks 14. Each output Q is coupled to the input terminal E of a block 14 by means of a logic switch 18. All the logic switches 18
• the circuits 8 and 12 are conventionally integrated on the same semiconductor chip of a control circuit.
• the cells of a plasma screen are activated line by line. Unactivated lines are subject to a resting potential (for example 150 V).
• the activated line is brought to an activation potential (for example 0 V), the columns being to an inactivation potential GD (0 V).
• the respective columns are brought potential inactivation GND to a potential VPP 1 activation (e.g. 80 V) for a predetermined time.
• VPP 1 activation e.g. 80 V
• the columns corresponding to the non-selected cells of the activated line are kept at GND potential.
• the cells which must be activated are subjected, during the voltage window, to a column-line voltage equal to VPP - GND (80 V) and the cells which must not be activated are subjected to an equal column-line voltage to GND - GND (0 V). All lines not activated are at rest potential (150 V).
• the column potential being either 0 V or 80 V, the cells of the non-activated lines are reverse biased and are not subjected to a potential capable of triggering ionization. some gas.
• FIG. 2 represents a conventional column control block 14.
• a MOS transistor Tl of type N, has its drain connected to the potential VPP and its source connected to the output terminal O.
• a MOS transistor T2, of type N has its drain connected to the output terminal O, and its source linked to GND potential.
• a Zener diode 20 is connected by its cathode to the gate of transistor Tl and by its anode to the source of transistor Tl.
• An MOS transistor T3, of type P has its source connected to potential VPP and its drain connected to gate of transistor Tl.
• An MOS transistor T4, of type N has its drain connected to the gate of transistor Tl and its source connected to ground (GND).
• MOS transistors T5, T6, type P have their sources connected to the VPP potential.
• the gate of transistor T5 is connected to the drain of transistor T6 and the gate of transistor T6 is connected to the drain of transistor T5.
• An MOS transistor T7, of type N has its source connected to ground and its drain connected to the drain of transistor T5.
• An MOS transistor T8, of type N has its source connected to ground and its drain connected to the drain of transistor T6.
• the gate of transistor T3 is connected to the drain of transistor T6.
• the gates of the transistors T2, T4 and T7 are connected to the input terminal E via an inverter 22.
• the gate of the transistor T8 is connected to the output of the inverter 22 via a inverter 24.
• the output terminal O is connected to a column 6.
• a capacitor C2 connects the column 6 and the ground.
• the capacity C2 is the equivalent capacity of column 6. It mainly consists of a first component corresponding to the capacity between the selected column and the rows of the screen, and a second component corresponding to the capacity between the column selected and its neighboring columns.
• the capacity C2 does not have a constant value, as will be seen later.
• Block 14 is designed to subject column 6 to a voltage slot when its input E receives a logic "1" (for example a VDD potential equal to 5V), then a logic "0" (0V).
• a logic "1” for example a VDD potential equal to 5V
• block 14 charges the capacity C2 at a potential substantially equal to VPP (which is called VPP for simplicity).
• VPP which is called VPP for simplicity.
• the block 14 discharges the capacitor C2 and the potential of the column 6 passes from VPP to GND.
• the value of the capacity C2 of a column 6 depends on the potentials to which the neighboring columns situated on either side of this column are subjected.
• the capacity C2 of this column has a maximum value if neither of the two neighboring columns is subjected to a voltage slot.
• the capacitance C2 has a minimum value if the two neighboring columns are subjected to a voltage slot, and a value substantially equal to half the sum of the maximum and minimum values, which will be called hereafter the median value, if l 'only one of the neighboring columns is also subject to a voltage gap.
• the maximum duration of the rise in the voltage slot may be different from the maximum duration of the fall in the voltage slot. For reasons of simplicity, we will consider that they are equal.
• the maximum admissible duration of rise / fall of the voltage slot, as well as the different values of the capacitance C2, are characteristics of each type of plasma display.
• the blocks 14 are provided to each supply (and receive) a predetermined current making it possible to charge (and discharge) the maximum capacity C2 of the type of screen considered in a time less than the maximum admissible duration. rise / fall of the voltage slot for this type of screen.
• the transistors T1 and T2 are dimensioned to be crossed by this predetermined current when they are conducting.
• the block 14 supplies or absorbs the preceding predetermined current for a variable duration depending on the selection of the neighboring columns.
• each block 14 introduces, when the capacitance C2 has its minimum value, intense variations in the current consumption for very short periods, which are capable of creating electromagnetic interference on the supply and the ground of the circuit of command, which is not desirable.
• a control circuit whose blocks 14 are dimensioned to control a screen of a particular type, may not be usable for controlling another type of screen.
• An object of the present invention is to provide a plasma screen cell control circuit whose operation is unlikely to create electromagnetic interference.
• Another object of the present invention is to provide such a control circuit which can easily be adapted to various types of plasma display.
• the present invention provides a control circuit for a plasma screen consisting of cells arranged at the intersections of rows and columns, comprising, for each column of the screen, a column control block allowing the selection of the column associated with it by applying to said column a voltage window during which said column is brought to a first potential substantially equal to a first predetermined potential and then to a second potential substantially equal to a second predetermined potential, said column having a different capacity depending on whether the neighboring columns are selected or not, each column control block including a first means suitable for charging the capacitor of said column a first predetermined time when said column is brought to said first potential, 'and second means suitable for discharging the capacity of said column in a second predetermined period when said column is brought to said second potential, the second means being controlled by control means as a function of an estimate of the capacity of said column obtained from information indicating the selection or the non-selection of the neighboring columns of said column.
• FIG. 1, previously described schematically represents a plasma screen provided with a control circuit
• FIG. 2, previously described schematically represents a conventional column control block of a control circuit
• FIG. 3 schematically represents a first embodiment of a column control block according to the present invention
• Figure 4 schematically shows an element of the control unit of Figure 3
• Figure 5 schematically illustrates the operation of the control means of Figure 3
• Figure 6 shows in more detail an embodiment of the control unit of Figure 3;
• FIG. 7 schematically represents a second embodiment of a column control block according to the present invention
• FIG. 8 schematically represents the variable current source of FIG. 7.
• each column control block comprises means so that the rise and / or fall time of the voltage slot supplied to each column has the same predetermined value which whatever the value of the capacity of said column.
• FIG. 3 represents a column control block 14 ′ according to a first embodiment of the present invention.
• Block 14 ′ has an output terminal O connected to a column 6.
• Column 6 is connected to ground via a capacitor C2.
• Block 14 ′ includes transistors Tl, T2, T3, T4, T5, T6, T7 and T8 and inverters 22 and 24 connected substantially as in FIG. 2.
• a capacitor C is connected between the gate of transistor Tl and the mass.
• a constant current source CS1 has a first terminal connected to the potential VPP and a second terminal connected to the source of the transistor T3.
• the gate of transistor T2 is connected to an output terminal 028 of a control means 28.
• the control means 28 has an input terminal E28 connected to the output of the inverter 22.
• the transistors T7, T6 and T4 are blocked, the transistors T8, T5 and T3 become conductive and the current II supplied by the constant current source CSl charges the capacitor C. It is assumed that at the start the capacitor C is discharged. The capacitor C is charged at constant current and the potential of the gate of transistor Tl goes from 0 to a maximum value (substantially VPP) in a constant duration.
• the transistor T1 is connected as a voltage follower.
• the potential of the output terminal O increases with the potential of the gate of the transistor Tl, in a constant duration whatever the value of the capacitor C2 of the column 6. The rise time of the voltage pulse is thus constant.
• FIG. 4 schematically represents an embodiment of the current source CSl of FIG. 3.
• the current source CSl comprises an MOS transistor T9, of type P, whose source is connected to the potential VPP and whose drain is connected to the source of transistor T3.
• a MOS transistor T10, of type P has its source connected to the potential VPP and its drain connected to its gate.
• the gate of transistor T9 is connected to the gate of transistor T10 so that the current passing through transistor T9 is proportional (for simplicity, we consider that it is equal) to the current passing through transistor T10.
• a constant current source CS2 has a first terminal connected to the drain of transistor T10 and a second terminal connected to ground.
• the constant current 12 passing through the current source CS2 is reproduced in the transistor T9, and fixes the value of the current II produced by the current source CS1.
• Current 12 determines the rise time of the voltage segment to which column 6 is subjected.
• the current source CS2 can be adjustable so as to supply different constant currents 12 and to adjust the rise time of the voltage segment to the characteristics of different types of plasma screens.
• the transistor T10 and the current source CS2 can be common to all the current sources CS1 of all the column control blocks 14 ′ of a control circuit. In this case, each block 14 ′ will only comprise a transistor T9 whose gate is connected to the gate of the common transistor T10.
• a switch for example an N-type MOS transistor, between the current source CS2 and the transistor T10.
• a switch for example an N-type MOS transistor, between the current source CS2 and the transistor T10.
• Such a switch would make it possible to inactivate the current source CS1 when one does not wish to use the block 14 ', for example during a phase of maintenance of the ionization of the cells of the screen, and thus to limit the consumption of the control circuit.
• the control means 28 is activated and it subjects the gate of the transistor T2 to an activation potential chosen from three predetermined activation potentials.
• the activation potential provided by the means 28 is different depending on whether the value of the capacitor C2 is maximum, median or minimum, so that the transistor T2 is crossed respectively by a maximum, median or minimum current and that the duration of the discharge of the capacitor C2 is constant.
• the control means 28 comprises three control terminals Q, Q ⁇ -, Qi + i-
• the terminal Q is connected to the output Q of the register 16 which is coupled to the input E of the control block 14 'of column 6 considered, called rank i.
• the terminal 0_i_ ⁇ is connected to the output Q of the register 16 which is coupled to the control block 14 'of the preceding column, of row i-1.
• the terminal ⁇ 2i + 1 is connected to the output Q of the register 16 which is coupled to the control block 14 ′ of the next column, of rank i + 1.
• FIG. 5 illustrates the operation of the control means 28 of FIG. 3.
• the block 14 When the input terminal E28 receives a logic "0”, the block 14 'controls the rise of the voltage slot, and the output terminal 028 is set to ground so as to block transistor T2.
• the input terminal E28 receives a logic "1” and when the terminal Qj_ receives a logic "0”, the column 6 coupled to the control block 14 'is not selected.
• the output terminal 028 then takes a logic value "1”, the transistor T2 is turned on and connects the capacitor C2 to ground.
• the control block 14 When the input terminal E28 receives a logic "1” and the terminal Q ⁇ a logic "1”, the control block 14 'controls the descent of the voltage slot.
• the output 028 is brought to a potential V m i n .
• the potentials v max ' v med and v min' lower than the potential VDD, are chosen so as to control the transistor T2 so that it is crossed respectively by currents Imax ' ⁇ med and ⁇ -min Proper to discharge the capacitance C2 of the voltage VPP to ground in a constant time, when the capacitance C2 has its maximum, median and minimum value respectively.
• FIG. 6 shows in more detail an embodiment of the control block 14 '.
• the means 28 is produced using inverters, NAND, OR-exclusive gates and transistors mounted as switches, but the person skilled in the art will easily produce a means 28 having the same functions. using other elements.
• the gate of transistor T4 is connected at the output of the inverter 22 by means of two inverters 23, 25 connected in series.
• FIG. 7 schematically represents a column control block 14 "according to a second embodiment of the present invention.
• the block 14" comprises an input terminal E and an output terminal 0.
• the block 14 “comprises a MOS transistor Tll, of type P, the source of which is connected to the potential VPP and the drain of which is connected to the terminal O.
• a MOS transistor T2, of type N has its source connected to ground and its drain connected to the drain of the transistor Tll
• the gate of transistor T2 is connected to output 028 of a control means 28 having three control terminals Q- ⁇ , Q ⁇ - ⁇ , Qi + i-
• the terminals Q ⁇ , Q ⁇ - ⁇ , Qi + l are connected to the register 16 in the manner described in relation to FIG. 3.
• the means 28 has an input terminal E28 connected to the terminal E via an inverter 22.
• a MOS transistor T12 of type P, has its source connected to the potential VPP and its drain connected to the gate of the transistor T11.
• the transistor T12 forms a current mirror with a transistor MOS T13, type P, the source is connected to the VPP potential and whose drain and grid are connected together.
• the drain of transistor T13 is connected to the drain of a transistor T7, of type N, the source of which is connected to ground and the gate of which is connected to the output of inverter 5 22.
• a MOS transistor T14 of type P, has its source connected to the potential VPP and its drain connected to its gate as well as to the gate of the transistor T11.
• the drain of transistor T14 is connected to the drain of a MOS transistor T15, of type N, the gate of which is connected via an inverter 24 to the output of
• a variable current source CS3 has a first terminal connected to the source of transistor T15 and a second terminal connected to ground.
• the current source CS3 has three control terminals connected to the terminals Q ⁇ , Q ⁇ -i and Qi +1 - the current source CS3 is designed to provide a
• current 13 can take three values ISmax, I3 me d and I3 min different according to the values of the signals received on the terminals Qi, Qi_ ⁇ and Qi + ⁇ .
• control means 28 is controlled as a function of the outputs Q of the register 16 and it subjects the gate of the transistor T2 to an activation potential chosen from three predetermined potentials so that the duration of the discharge of the capacitor C2 is constant.
• FIG. 8 schematically represents an embodiment of the current source CS3 of FIG. 7.
• the current source CS3 comprises a first terminal ⁇ 3 connected to the source of the transistor T15.
• An MOS transistor T16 of type N, has its drain connected to the terminal E3.
• the transistor T16 is mounted as a switch.
• the gate of transistor T16 is connected to the output of a buffer circuit 56.
• An MOS transistor T18, of type N, has its drain connected to the source of transistor T16 and its source connected to ground.
• An MOS transistor T20, of type N has its drain connected to the terminal E3.
• the transistor T20 is mounted as a switch.
• the gate of transistor T20 is connected to the output of a buffer circuit 58.
• An MOS transistor T22 of type N, has its drain connected to the source of transistor T20 and its source connected to ground.
• An MOS transistor T24, of type N has its drain connected to the terminal E3.
• the transistor T24 is mounted as a switch.
• the gate of transistor T24 is connected to the output of a buffer circuit 60.
• An MOS transistor T26, of type N has its drain connected to the source of transistor T24 and its source connected to ground.
• T28 of type N, has its source connected to ground and its drain connected to potential, supplying VDD via a constant current source CS4.
• the gate and the drain of transistor T28 are connected together.
• the gates of transistors T26, T22 and T18 are connected to the gate of transistor T28.
• the transistors T26, T22 and T18 each behave like a constant current source.
• a decoder 64 has three outputs D1, D2 and D3 connected respectively so as to control the buffer circuits 56, 58 and 60.
• the decoder 64 has three input terminals corresponding to the control terminals Q ⁇ - ⁇ , Q ⁇ and Q ⁇ + ⁇ from the current source
• the operation of the decoder 64 is as follows.
• the transistor T24 is on and the transistors T20 and T16 are blocked when the capacitor C2 has a maximum value.
• the transistor T20 is on and the transistors T24 and T16 are blocked when the capacitor C2 has a median value.
• the transistor T16 is on and the transistors T24 and T20 are blocked when the capacitor C2 has a minimum value.
• the width and length of the channel of the transistors T26, T22, and T18 are produced so that these transistors are respectively crossed by the currents I3 max , I3 me ⁇ : and I3 mn .
• the current source CS4 can be fixed, or be adjustable to adjust the rise time of the voltage window to different types of plasma screens.
• the present invention is susceptible to various variants and modifications which will appear to a person skilled in the art.
• the MOS transistors could be replaced by bipolar transistors.
• the column control blocks 14 ′ and 14 ′′ provide voltage slots having constant rise and fall times on the one hand.
• these two aspects are separable from each other and it is possible to provide a column control unit providing voltage slots of which only the rise time is constant or only the fall time is constant, without leaving of the field of the invention.

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• Plasma & Fusion (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Control Of Indicators Other Than Cathode Ray Tubes (AREA)

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• 2000
  • 2000-11-14 FR FR0014600A patent/FR2816746A1/fr active Pending
• 2001
  • 2001-11-14 EP EP01996850A patent/EP1342228A1/de not_active Withdrawn
  • 2001-11-14 US US10/169,895 patent/US7122968B2/en not_active Expired - Lifetime
  • 2001-11-14 JP JP2002543418A patent/JP2004514177A/ja active Pending
  • 2001-11-14 WO PCT/FR2001/003574 patent/WO2002041292A1/fr active Application Filing

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