EP1331623A1 - Anzeige und ihr ansteuerverfahren - Google Patents

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Publication number
EP1331623A1
EP1331623A1 EP01963523A EP01963523A EP1331623A1 EP 1331623 A1 EP1331623 A1 EP 1331623A1 EP 01963523 A EP01963523 A EP 01963523A EP 01963523 A EP01963523 A EP 01963523A EP 1331623 A1 EP1331623 A1 EP 1331623A1
Authority
EP
European Patent Office
Prior art keywords
recovery
resonance
lighting rate
time
discharge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01963523A
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English (en)
French (fr)
Other versions
EP1331623A4 (de
Inventor
Shigeo Kigo
Mitsuhiro Kasahara
Mitsuhiro Mori
Jumpei Hashiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
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Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of EP1331623A1 publication Critical patent/EP1331623A1/de
Publication of EP1331623A4 publication Critical patent/EP1331623A4/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G09G3/2965—Driving circuits for producing the waveforms applied to the driving electrodes using inductors for energy recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/16—Calculation or use of calculated indices related to luminance levels in display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/294—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge

Definitions

  • the present invention relates to a display device that selectively discharges a plurality of discharge cells to display an image and a method of driving such a display device.
  • Plasma display devices using PDPs have the advantage capable of being thinner and having larger screens.
  • Such plasma display devices display images by utilizing light emission which occurs in the discharge of discharge cells constituting pixels.
  • Fig. 47 is a circuit diagram showing the structure of a sustain driver in a conventional plasma display device.
  • a sustain driver 600 includes a recovery capacitor C11, a recovery coil L11, switches SW11, SW12, SW21 and SW22, and diodes D11 and D12.
  • the switch SW11 is connected between a power supply terminal V11 and a node N11, and the switch SW12 is connected between the node N11 and a ground terminal.
  • the power supply terminal V11 is supplied with a sustain voltage V sus .
  • the node N11 is connected to, e.g., 480 sustain electrodes.
  • a panel capacitance Cp corresponding to all capacitances among the plurality of sustain electrodes and the ground terminal is illustrated in Fig. 47.
  • the recovery capacitor C11 is connected between a node N13 and the ground terminal.
  • the switch SW21 and the diode D11 are connected in series between the node N13 and a node N12, and the diode 12 and the switch SW22 are connected in series between the nodes N12 and N13.
  • the recovery coil L11 is connected between the nodes N11 and N12.
  • Fig. 48 is a timing chart showing the operation in a sustain time period of the sustain driver 600 shown in Fig. 47.
  • Fig. 48 shows a voltage at the node N11 and the operation of the switches SW21, SW11, SW22 and SW12.
  • the switch SW21 turns on, while the switch SW12 turns off.
  • the switches SW11 and SW22 are off. Accordingly, LC resonance caused by the recovery coil L11 and the panel capacitance Cp makes the voltage at the node N11 rise to a peak voltage Vp, so that the charges stored in the recovery capacitor C11 are supplied to the panel capacitance Cp.
  • sustain discharge is started.
  • the switch SW21 turns off, while the switch SW11 turns on. Accordingly, the node N11 is connected to the power supply terminal V11, so that the voltage at the node N11 rises sharply.
  • the voltage at the node N11 is fixed to the sustain voltage Vsus in a time period Tc.
  • the switch SW11 turns off, while the switch SW22 turns on. Accordingly, the LC resonance caused by the recovery coil L11 and the panel capacitance Cp makes the voltage at the node N11 gently drop, so that the charges are recovered from the panel capacitance Cp to the recovery capacitor C11.
  • the peak voltage Vp in the recovery time decreases, thereby failing to sufficiently reduce the reactive power and the power consumption in the case of a low lighting rate.
  • An object of the present invention is to provide a display device that enables stable discharge even if a lighting rate varies as well as enabling reduced reactive power and reduced power consumption, and provide a method of driving such a display device.
  • a display device is a display device that displays an image by causing a plurality of discharge cells to selectively discharge, including: recovery means for recovering charges stored in the discharge cells to drive a drive pulse by using the recovered charges; and detection means for detecting a lighting rate of any of the plurality of discharge cells, which are to be turned on at the same time, wherein the plurality of discharge cells includes a capacitive load; and the recovery means includes inductance means having at least one inductance element that has one end connected to the capacitive load, and resonance driving means for driving the drive pulse by LC resonance of the capacitive load and the inductance element.
  • the display device further includes control means for controlling the recovery means so as to vary a recovery time in which the drive pulse is driven by the recovery means and a resonance time of the LC resonance, depending on the lighting rate detected by the detection means.
  • the drive pulse is driven by the LC resonance of the capacitive load and the inductance element, while the lighting rate of any of the plurality of discharge cells, which are to be turned on at the same time, is detected, and the recovery time, in which the drive pulse is driven, and the resonance time of the LC resonance are varied depending on the lighting rate.
  • This allows the drive pulse to be driven in an optimum recovery time and in an optimum resonance time of the LC resonance depending on the lighting rate. Accordingly, when the lighting rate is larger, the recovery time is made shorter to enable stable discharge, and the resonance time is also made shorter to enable reduced reactive power. Conversely, when the lighting rate is smaller, the recovery time is made longer to enable reduced reactive power. Consequently, even though the lighting rate varies, the stable discharge can be carried out with achievement of the reduced reactive power and the reduced power consumption.
  • the display device may further includes conversion means for converting image data in one field into image data in each of a plurality of subfields divided from the one field in order to carry out a gray scale display by causing discharge of any of the discharge cells selected for each subfield;
  • the detection means includes subfield lighting rate detection means for detecting a lighitng rate for each subfield;
  • the control means may control the recovery means so as to vary the recovery time and the resonance time of LC resonance depending on the lighting rate for each subfield detected by the subfield lighting rate detection means.
  • the control means may control the recovery means so that the recovery time becomes longer as the lighting rate detected by the detection means becomes smaller.
  • the recovery time is set longer as the detected lighting rate is smaller, the recovery time is set longer to enable decreased reactive power in the case of a smaller lighting rate, while the recovery time is set shorter to enable stable discharge in the case of a larger lighting rate.
  • the control means may control the recovery means so that the resonance time of LC resonance becomes longer as the lighting rate detected by the detection means becomes smaller.
  • the resonance time of LC resonance is set longer as the detected lighting rate becomes smaller, the recovery time is set longer to enable decreased reactive power in the case of a smaller lighting rate, while the resonance time of LC resonance is set shorter to enable stable discharge and more decreased reactive power in the case of a larger lighting rate.
  • the control means may control the recovery means so as to vary a discharge recovery time of the recovery time, in which discharge cells discharge depending on the lighting rate detected by the detection means, and so as not to vary a non-discharge recovery time of the recovery time, in which the discharge cells do not discharge is not varied.
  • the discharge recovery time of the recovery time in which discharge cells discharge, is varied depending on the detected lighting rate, it is possible to optimize the discharge recovery time depending on the detected lighting rate and reduce reactive power as well as achieve stable discharge. Further, since the non-discharge recovery time of the recovery time, in which the discharge cells do not discharge, is not varied, it is possible to simplify the control of a drive waveform in this period and thus simplify circuit configurations.
  • the control means may control the recovery means so that the non-discharge recovery time of the recovery time, in which the discharge cells do not discharge, becomes longer than the discharge recovery time, in which the discharge cells discharge, depending on the lighting rate detected by the detection means.
  • the non-discharge recovery time is set longer than the discharge recovery time depending on the detected lighting rate, the non-discharge recovery time that requires no consideration of discharge stability is set still longer to enable more reduced reactive power.
  • a display device is a display device that displays an image by causing a plurality of discharge cells to selectively discharge, including: recovery means for recovering charges stored in the discharge cells to drive a drive pulse by using the stored charges; and detection means for detecting a lighting rate of any of the plurality of discharge cells, which are to be turned on at the same time, wherein the plurality of discharge cells include a capacitive load; and the recovery means includes inductance means having at least one inductance element that has one end connected to the capacitive load, and resonance driving means for driving the drive pulse by LC resonance caused by the capacitive load and the inductance element.
  • the display device further includes control means for controlling the recovery means so as to vary a resonance time of the LC resonance depending on the lighting rate detected by the detection means.
  • the drive pulse is driven by the LC resonance of the capacitive load and the inductance element, and also the resonance time of the LC resonance is varied depending on the detected lighting rate, it is possible to set the resonance time of the LC resonance to an optimum value depending on the detected lighting rate. Accordingly, it is possible to make a stable discharge voltage constant by increasing an inductance value of the inductance element to set the resonance time longer in the case of a smaller lighting rate, while decreasing the inductance value of the inductance element to set the resonance time shorter in the case of a larger lighting rate. In the case of a larger lighting rate, in particular, the resonance time is set shorter to enable stable discharge, and recovery efficiency is increased to enable decreased reactive power. In addition, it is possible to increase discharge stability by setting a recovery time constant. Consequently, even though the lighting rate varies, it is possible to carry out stable discharge and reduce reactive power and thus power consumption.
  • the inductance means includes variable inductance means capable of varying an inductance value.
  • the control means may vary the inductance value of the variable inductance means depending on the lighting rate detected by the detection means.
  • variable inductance means may include a plurality of inductance elements connected in parallel and selection means controlled by the control means for selecting a given inductance element of the plurality of inductance elements.
  • variable inductance means may include a plurality of inductance elements connected in series and selection means controlled by the control means for selecting a given inductance element of the plurality of inductance elements.
  • the recovery means further includes a capacitive element for recovering charges from the capacitive load;
  • the variable inductance means includes a first inductance element;
  • the resonance driving means includes first switch means connected to the first inductance means between the capacitive load and the capacitive element;
  • the variable inductance means further includes a second inductance element and second switch means connected in series to opposite ends of the first inductance element.
  • the control means may control the on/off states of the first and second switch means.
  • the second inductance element can be connected in parallel to the first inductance element depending on the lighting rate, it is possible to set an optimum inductance value depending on the lighting rate by using a composite inductance value of the first and second inductance elements and an inductance value of the first inductance element.
  • the recovery means further includes a capacitive element for recovering charges from the capacitive load;
  • the variable inductance means includes a first inductance element;
  • the resonance driving means includes first switch means connected in series to the first inductance element between the capacitive load and the capacitive element;
  • the variable inductance means further includes a second inductance element and second switch means connected in series between the capacitive load and the capacitive element.
  • the control means may control the on/off states of the first and second switch means.
  • the on/off states of the first and second switch means are controlled depending on the lighting rate, it is possible to set an optimum inductance value depending on the lighting rate by using a composite inductance value of the first and second inductance elements as well as inductance values of the first and second inductance elements. Moreover, since only one switch means is provided between the capacitive load and the capacitive element, it is possible to reduce a loss caused by the switch means to a required minimum and further decrease reactive power.
  • the resonance driving means further includes a third inductance element and third switch means connected in series between the capacitive load and the capacitive element.
  • the control means may turn on at least one of the first switch means and the second switch means in a discharge recovery time of a recovery time, in which discharge cells discharge, while the control means may turn on the third switch means in a non-discharge recovery time of the recovery time, in which said discharge cells do not discharge.
  • the on/off states of the first and second switch means are controlled so that at least one of the first and second inductance elements is connected between the capacitive load and the capacitive element in the discharge recovery time, it is possible to set an optimum inductance value in the discharge recovery time depending on the lighting rate by using the composite inductance value of the first and second inductance elements as well as the inductance values of the first and second inductance elements.
  • the on/off states of the third switch means are controlled so that the third inductance element is connected between the capacitive load and the capacitive element in the non-discharge recovery time, it is possible to set an inductance value of the third inductance element and more decrease the reactive power in view of only the decrease of reactive power, not in view of the discharge stability of discharge cells in the non-discharge recovery time.
  • the resonance driving means further includes third switch means connected in parallel to the first switch means; and the variable inductance means further includes fourth switch means connected in parallel to the second switch means.
  • the control means may control the on/off states of the first to fourth switch means.
  • the control means may control the on/off states of the first and second switch means so that the second switch means is turned on after the first switch means is turned on.
  • the first and second inductance elements are connected in parallel after the connection of the capacitive element and the first inductance element, it is made possible to vary the inductance value into various values and set an optimum inductance value depending on the lighting rate, by changing a ratio of a time period that only the inductance value of the first inductance element is employed and a time period that the composite inductance value of the first and second inductance elements is employed.
  • the display device further includes conversion means for converting image data in one field into image data in each of a plurality of subfields divided from one field in order to carry out a gray scale display by causing discharge of any of discharge cells selected for each subfield.
  • the detection means includes subfield lighting rate detection means for detecting a lighting rate for each subfield.
  • the control means may control a time period that the second switch means is turned on, depending on the lighting rate for each subfield detected by the subfield lighting rate detection means.
  • the time period in which the second switch means is turned on is controlled depending on the lighting rate detected for each subfield, it is possible to vary the inductance value depending on the lighting rate for each subfield and optimize the inductance value depending on the lighting rate even in the case of the gray scale display.
  • the first and second switch means may be any one of a set of field-effect transistor and a diode connected in series, a set of two field-effect transistors connected in series, and an insulated-gate bipolar transistor.
  • the first and second switch means are formed of any one of the set of series-connected field-effect transistor and diode, the set of the series-connected two field-effect transistors, and the insulated-gate bipolar transistor, a switching operation can be carried out by each of those elements.
  • the use of the series-connected two field-effect transistors can especially reduce a loss in the switch means.
  • the control means may control the recovery means so that the resonance time of LC resonance becomes longer as the lighting rate detected by the detection means becomes smaller.
  • the resonance time of LC resonance is set longer as the detected lighting rate becomes smaller, it is made possible to make the stable discharge voltage constant by increasing the resonance time in the case of a smaller lighting rate, while decreasing the resonance time in the case of a larger lighting rate.
  • the resonance time is set shorter to enable stable discharge, and the reactive power may be reduced by improving the recovery efficiency.
  • the control means may vary the period of the drive pulse depending on the lighting rate detected by the detection means.
  • a method of driving a display device is a method of driving a display device that displays an image by causing a plurality of discharge cells to selectively discharge, wherein the plurality of discharge cells include a capacitive load; and the display device includes inductance means having at least one inductance element that has one end connected to the capacitive load, the method including the steps of: recovering charges stored in the discharge cells to drive a drive pulse by LC resonance of the capacitive load and the inductance element by using the recovered charges; detecting a lighting rate of any of the plurality of discharge cells, which are to be turned on at the same time; and varying a recovery time in which the drive pulse is driven in the recovery step and a resonance time of LC resonance, depending on the lighting rate detected by the detection step.
  • the drive pulse is driven by the LC resonance of the capacitive load and the inductance element, and also, the lighting rate of any of the plurality of discharge cells, which are to be turned on at the same time, is detected, so that the recovery time, in which the drive pulse is driven, and the resonance time of LC resonance are varied depending on the lighting rate.
  • This enables the drive pulse to be driven in an optimum recovery time and in an optimum resonance time of LC resonance corresponding to the lighting rate. Therefore, when the lighting rate is larger, the recovery time is set shorter to enable stable discharge, and also, the resonance time is set shorter to enable decreased reactive power. Conversely, when the lighting rate is smaller, the recovery time is set longer to enable the decreased reactive power. Consequently, even though the lighting rate varies, it is possible to carry out the stable discharge and decrease the reactive power and thus power consumption.
  • a method of driving a display device is a method of driving a display device that displays an image by causing a plurality of discharge cells to selectively discharge, wherein the plurality of discharge cells include a capacitive load; and the display device includes inductance means having at least one inductance element that has one end connected to the capacitive load, the method including the steps of: recovering charges stored in the discharge cells to drive a drive pulse by LC resonance of the capacitive load and the inductance element by using the recovered charges; detecting a lighting rate of any of the plurality of discharge cells which are to be turned on at the same time; and varying a resonance time of the LC resonance depending on the lighting rate detected by the detection step.
  • the resonance time of the LC resonance is varied depending on the detected lighting rate. Accordingly, it is made possible to make a stable discharge voltage constant by increasing an inductance value of the inductance element to set the resonance time longer in the case of a smaller lighting rate, while decreasing the inductance value to set the resonance time shorter in the case of a larger lighting rate.
  • the resonance time is set shorter to enable stable discharge, and recovery efficiency is improved to enable decreased reactive power. Further, discharge stability can be enhanced by making a recovery time constant. Consequently, even though the lighting rate is varied, it is possible to carry out the stable discharge and reduce the reactive power and thus power consumption.
  • a display device is a display device that displays an image by causing a plurality of discharge cells to selectively discharge, including: a recovery circuit that recovers charges stored in the discharge cells to drive a drive pulse by using the recovered charges; and a detection circuit that detects a lighting rate of any of the plurality of discharge cells, which are to be turned on at the same time, wherein the plurality of discharge cells include a capacitive load; and the recovery circuit includes an inductance circuit having at least one inductance element that has one end connected to the capacitive load, and a resonance driving circuit that drives the drive pulses by LC resonance of the capacitive load and the inductance element.
  • the display device further includes a control circuit that controls the recovery circuit so as to vary a recovery time in which the drive pulse is driven by the recovery circuit and a resonance time of the LC resonance depending on the lighting rate detected by the detection circuit.
  • the drive pulse is driven by the LC resonance of the capacitive load and the inductance element; the lighting rate of any of the plurality of discharge cells, which are to be turned on at the same time, is detected; and the recovery time in which the drive pulse is driven and the resonance time of the LC resonance are varied depending on the lighting rate.
  • This makes it possible to drive the drive pulse in an optimum recovery time and an optimum resonance time of the LC resonance corresponding to the lighting rate. Therefore, when the lighting rate is larger, the recovery time is set shorter to enable the stable discharge; and the resonance time is set shorter to enable the decreased reactive power. Conversely, when the lighting rate is smaller, the recovery time is set longer to enable the decreased reactive power. Consequently, even though the lighting rate is varied, it is possible to carry out the stable discharge and reduce the reactive power and power consumption.
  • a display device is a display device that displays an image by causing a plurality of discharge cells to selectively discharge, including: a recovery circuit that recovers charges stored in the discharge cells to drive a drive pulse by using the recovered charges; and a detection circuit that detects a lighting rate of any of the plurality of discharge cells, which are to be turned on at the same time, wherein the plurality of discharge cells include a capacitive load; and the recovery circuit includes an inductance circuit having at least one inductance element that has one end connected to the capacitive load, and a resonance driving circuit that drives the drive pulse by LC resonance of the capacitive load and the inductance element.
  • the display device further includes a control circuit that controls the recovery circuit so as to vary a resonance time of the LC resonance depending on the lighting rate detected by the detection circuit.
  • the drive pulse is driven by the LC resonance of the capacitive load and the inductance element, and also the resonance time of the LC resonance is varied depending on the detected lighting rate, it is possible to set the resonance time of the LC resonance to an optimum time depending on the detected lighting rate. Accordingly, it is made possible to make a stable discharge voltage constant by increasing an inductance value of the inductance element to set the resonance time longer in the case of a smaller lighting rate, while decreasing the inductance value to set the resonance time shorter in the case of a larger lighting rate. In the case of a larger lighting rate, in particular, the resonance time is set shorter to enable stable discharge, and recovery efficiency is improved to enable decreased reactive power. Further, discharge stability can be enhanced by making a recovery time constant. Consequently, even though the lighting rate is varied, it is possible to carry out the stable discharge and reduce the reactive power and thus power consumption.
  • FIG. 1 is a block diagram showing the structure of a plasma display device according to a first embodiment of the present invention.
  • the plasma display of Fig. 1 includes an A/D converter (analog-to-digital converter) 1, a video signal/subfield corresponder 2, a subfield processor 3, a data driver 4, a scan driver 5, a sustain driver 6, a PDP (plasma display panel) 7 and a subfield lighting rate measuring unit 8.
  • the A/D converter 1 is supplied with a video signal VD.
  • the A/D converter 1 converts an analog video signal VD into digital image data to output the image data to the video signal/subfield corresponder 2.
  • the video signal/subfield corresponder 2 produces image data SP for each subfield from image data in one field to output the produced image data SP to the subfield processor 3 and the subfield lighting rate measuring unit 8.
  • the subfield lighting rate measuring unit 8 detects a lighting rate of discharge cells 14 that are simultaneously driven on the PDP 7, from the image data SP for each subfield, so as to output the result of the detection as a subfield lighting rate signal SL to the subfield processor 3.
  • the subfield lighting rate measuring unit 8 separately calculates the respective lighting rates of all subfields by using video signal information decomposed into one-bit information representing the lighting/non-lighting of the discharge cells for each of subfields that are generated by the video signal/subfield corresponder 2. The measuring unit 8 then outputs the results of the calculation as the subfield lighting rate signal SL to the subfield processor 3.
  • the subfield lighting rate measuring unit 8 includes a counter therein.
  • the measuring unit 8 finds the total number of discharge cells that are turned on for each subfield by increasing the value of the counter one at a time when the video signal information, which are decomposed into the one-bit information representing lighting/non-lighting, represents lighting, and divides the found total number by the number of all discharge cells on the PDP 7, so as to find the lighting rate.
  • the subfield processor 3 produces a data driver driving control signal DS, a scan driver driving control signal CS and a sustain driver driving control signal US from the image data SP for each subfield, the subfield lighting rate signal SL and the like and outputs those signals DS, CS and US to the data driver 4, the scan driver 5 and the sustain driver 6, respectively.
  • the PDP 7 includes a plurality of address electrodes (data electrodes) 11, a plurality of scan electrodes 12 and a plurality of sustain electrodes 13.
  • the plurality of address electrodes 11 are arranged in the vertical direction of a screen, while the plurality of scan electrodes 12 and the plurality of sustain electrodes 13 are arranged in the horizontal direction of the screen.
  • the plurality of sustain electrodes 13 are connected in common.
  • the discharge cells are formed at respective crossing points of the address electrodes 11, the scan electrodes 12 and the sustain electrodes 13.
  • Discharge cells 14 each constitute pixels on the screen.
  • the data driver 4 is connected to the plurality of address electrodes 11 in the PDP 7.
  • the scan driver 5 includes driving circuits therein each provided for each scan electrode 12. Each of the driving circuits is connected to its corresponding scan electrode 12 in the PDP 7.
  • the sustain driver 6 is connected to the plurality of sustain electrodes 13 in the PDP 7.
  • the data driver 4 applies write pulses to corresponding address electrodes 11 in the PDP 7 in response to the image data SP in a write time period on the basis of the data driver driving control signal DS.
  • the scan driver 5 applies write pulses in turn to the plurality of scan electrodes 12 in the PDP 7 while shifting shift pulses in a vertical scanning direction in the write time period on the basis of the scan driver driving control signal CS. Consequently, address discharges are carried out in corresponding discharge cells 14.
  • the scan driver 5 applies periodical sustain pulses to the plurality of scan electrodes 12 in the PDP 7 in a sustain time period on the basis of the scan driver driving control signal CS.
  • the sustain driver 6 simultaneously applies sustain pulses which are shifted in phase by 180° from the sustain pulses of the scan electrodes 12, to the plurality of sustain electrodes 13 in the PDP 7 in the sustain time period on the basis of the sustain driver driving control signal US. Consequently, sustain discharges are carried out in the corresponding discharge cell 14.
  • the scan driver 5 and the sustain driver 6 vary the waveform and the period of sustain pulses in response to the subfield lighting rate signal SL on the basis of the scan driver driving control signal CS and the sustain driver driving control signal US, as will be described later.
  • an ADS (Address Display-Period Separation) method is adopted as a gray scale display driving method.
  • ADS Address Display-Period Separation
  • one field is divided into 8 subfields SF1 to SF8.
  • the respective subfields SF1 to SF8 are weighted with respective brightness values of 1, 2, 4, 8, 16, 32, 64 and 128. Combination of those subfields SF1 to SF8 makes it possible to adjust the level of brightness on 256 gray scales from 0 to 255, thereby enabling the gray scale display.
  • the number of subfields to be divided, the values of subfields to be weighted and the like are not particularly limited to those in the above example but can be subject to various alterations.
  • the subfield SF8 may be divided into two subfields, to set the value with which these divided two subfields are weighted to 64.
  • Fig. 2 is a timing chart showing one example of a driving voltage of the scan electrodes 12 and the sustain electrodes 13 in the PDP 7 of Fig. 1.
  • initialization pulses (setup pulses) Pset are simultaneously applied to the plurality of scan electrodes 12. After that, write pulses Pw are applied in turn to the plurality of scan electrodes 12. This causes address discharges in corresponding discharge cells in the PDP 7.
  • sustain pulses Psc are periodically applied to the plurality of scan electrodes 12, while sustain pulses Psu are periodically applied to the plurality of sustain electrodes 13.
  • the phase of the sustain pulses Psu is shifted by 180° from that of sustain pulses Psc. This causes sustain discharges subsequent to the address discharges.
  • Fig. 3 is a circuit diagram showing the structure of the sustain driver shown in Fig. 1. Since the scan driver 5 is structured and operates similarly to the sustain driver 6, a detailed description on the scan driver 5 will not be given. A detailed description will be made only on the sustain driver 6.
  • the sustain driver 6 shown in Fig. 3 includes FETs (field-effect transistors; hereinafter referred to as transistors ) Q1 to Q4, a recovery capacitor Cr, a recovery coil L and diodes D1 and D2.
  • FETs field-effect transistors; hereinafter referred to as transistors
  • recovery capacitor Cr recovery capacitor
  • diodes D1 and D2 diodes
  • the transistor Q1 has its one end connected to a power supply terminal V1, the other end connected to a node N1 and its gate supplied with a control signal S1.
  • a sustain voltage Vsus is applied to the power supply terminal V1.
  • the transistor Q2 has its one end connected the node N1. the other end connected to a ground terminal and its gate supplied with a control signal S2.
  • a panel capacitance Cp corresponding to all capacitances provided between the plurality of sustain electrodes 13 and the ground terminal is illustrated in Fig. 3. This respect is similarly applied to sustain drivers presented in other embodiments in the following.
  • the recovery capacitor Cr is connected between a node N3 and the ground terminal.
  • the transistor Q3 and the diode D1 are connected in series between the node N3 and a node N2.
  • the diode D2 and the transistor Q4 are connected in series between the nodes N2 and N3.
  • the transistor Q3 has its gate provided with a control signal S3, while the transistor Q4 has its gate provided with a control signal S4.
  • the recovery coil L is connected between the nodes N2 and N1.
  • Fig. 4 is a block diagram showing the structure of the subfield processor 3 of Fig. 1.
  • the subfield processor 3 shown in Fig. 4 includes a lighting rate/recovery time LUT (Look-up Table) 31, a recovery time determining unit 32, a lighting rate/sustain period LUT 33, a sustain period determining unit 34 and a discharge control signal generator 35.
  • the lighting rate/recovery time LUT 31 is connected to the recovery time determining unit 32 and stores therein in a table format the relationship between a lighting rate and a recovery time based on experimental data. For example, 1300 ns is stored as the recovery time with respect to the lighting rate of 0 to 10 %, 1100 ns as the recovery time with respect to the lighting rate of 0 to 50 %, 900 ns as the recovery time with respect to the lighting rate of 50 to 80 %, 700 ns as the recovery time with respect to the lighting rate of 80 to 90 %, and 600 ns with respect to the lighting rate of 90 to 100 %.
  • the recovery time means a time period in which each sustain pulse Psu is driven by LC resonance caused by the recovery coil L and the panel capacitance Cp.
  • the recovery time determining unit 32 is connected to the discharge control signal generator 35 and reads a corresponding recovery time from the lighting rate/recovery time LUT 31 in response to the subfield lighting rate signal SL output from the subfield lighting rate measuring unit 8, so as to output the read recovery time to the discharge control signal generator 35. Determination of the recovery time is not particularly limited to the above example that the relationship between the lighting rate and the recovery time based on experimental data is stored in a table format, but the recovery time corresponding to the lighting rate may be evaluated by an approximate expression representing the relationship between the lighting rate and the recovery time.
  • the lighting rate/sustain period LUT 33 is connected to the sustain period determining unit 34 and stores in a table format the relationship between the lighting rate and a sustain period based on experimental data. For example, 8 ⁇ s is stored as the sustain period with respect to the lighting rate of 0 to 50 %, 7 ⁇ s as the sustain period with respect to the lighting rate of 50 to 80 %, and 6 ⁇ s as the sustain period with respect to the lighting rate of 80 to 100 %.
  • the sustain period means the period of each sustain pulse Psu.
  • the sustain period determining unit 34 is connected to the discharge control signal generator 35 and reads from the lighting rate/sustain period LUT 33 a corresponding sustain period in response to the subfield lighting rate signal SL output from the subfield lighting rate measuring unit 8, so as to output the read sustain period to the discharge control signal generator 35.
  • Determination of the sustain period is not particularly limited to the above example that the relationship between the lighting rate and the sustain period based on experimental data is stored in the table format, but an approximate expression and the like representing the relationship between the lighting rate and the sustain period may be employed.
  • the discharge control signal generator 35 outputs control signals S1 to S4 as the sustain driver driving control signal US so that the sustain driver 6 outputs sustain pulses Psu in the recovery time determined by the recovery time determining unit 32 and in the sustain period determined by the sustain period determining unit 34.
  • the scan driver 5 is also controlled by the subfield processor 3 similarly to the above, and the waveform and the period of sustain pulses to be applied to the scan electrodes 12 are likewise controlled on the basis of the lighting rate of subfields.
  • the transistors Q3, Q4, the recovery capacitor Cr, the recovery coil L and the diodes D1, D2 correspond to recovery means;
  • the subfield lighting rate measuring unit 8 corresponds to detection means and subfield lighting rate detection means;
  • the subfield processor 3 corresponds to control means; and
  • the video signal/subfield corresponder 2 corresponds to conversion means.
  • the recovery coil L corresponds to inductance means and an inductance element; and the transistors Q3, Q4, the recovery capacitor Cr and the diodes D1, D2 correspond to resonance driving means.
  • Fig. 5 is a timing chart showing one example of the operation of the sustain driver of Fig. 3 in the sustain time period.
  • Fig. 5 illustrates the voltage at the node N1 and control signals S1 to S4 input to the transistors Q1 to Q4 shown in Fig. 3.
  • the control signal S2 attains a low level to turn the transistor Q2 off, while the control signal S3 attains a high level to turn the transistor Q3 on.
  • the control signal S1 is at a low level and the transistor Q1 is off, while the control signal S4 is at a low level and the transistor Q4 is off.
  • the recovery capacitor Cr is connected to the recovery coil L via the transistor Q3 and the diode D1 and the LC resonance caused by the recovery coil L and the panel capacitance Cp causes the voltage at the node N1 to rise from a ground potential to a peak voltage Vp.
  • the control signal S1 attains a high level to turn the transistor Q1 on, while the control signal S3 attains a low level to turn the transistor Q3 off. Accordingly, the node N1 is connected to the power supply terminal V1, and the voltage at the node N1 increases and is then fixed to the sustain voltage Vsus.
  • the control signal S1 attains a low level to turn the transistor Q1 off, while the control signal S4 attains a high level to turn the transistor Q4 on.
  • the recovery capacitor Cr is connected to the recovery coil L via the diode 2 and the transistor Q4.
  • the LC resonance caused by the recovery coil L and the panel capacitance Cp causes a gradual decrease of the voltage at the node N1.
  • the charges stored in the panel capacitance Cp are stored in the recovery capacitor Cr via the recovery coil L, the diode D2 and the transistor Q4, so that the charges are recovered.
  • the control signal S2 attains a high level to turn the transistor Q2 on, while the control signal S4 attains a low level to turn the transistor Q4 off. Accordingly, the node N1 is connected to the ground terminal, and the voltage at the node N1 falls and is then fixed to a ground potential.
  • the time periods TA and TC are recovery times: the time period TA is a discharge recovery time in which discharge cells discharge, while the time period TC is a non-discharge recovery time in which discharge cells do not discharge.
  • the time period TA is also the resonance time.
  • Such periodical sustain pulses Psu that cause the discharge of the discharge cells 14 when the pulses rise from the ground potential to the sustain voltage Vsus can be applied to the plurality of sustain electrodes 13 by repetition of the above-described operation in the sustain time period.
  • the sustain pulses Psc that have the same waveform as that of the above sustain pulses Psu and are shifted in phase by 180° are periodically applied also to the scan electrodes 12 by the scan driver 5.
  • Fig. 6 is a waveform diagram for use in explaining the recovery time and the resonance time.
  • CL represents timing at which the node N1 of Fig. 3 is clamped to a power supply voltage (sustain voltage Vsus).
  • the recovery time is a time period required from the time when recovery starts until the time when the node N1 is clamped to the power supply voltage.
  • the resonance time is a time period required from the time when recovery starts until the time when the node N1 reaches an inherent peak voltage with the waveform caused by the LC resonance.
  • Fig. 7 is a waveform diagram for use in explaining variable control of the recovery time.
  • the resonance time is fixed and the recovery time is varied, there is a variation in the increased amount of the voltage at the node N1 from the time when the node N1 is connected to the power supply terminal V1 with the transistor Q1 turning on, until the time when the voltage at the node N1 reaches the power supply voltage.
  • Fig. 8 is a waveform diagram for use in explaining variable control of the resonance time.
  • the recovery time is fixed and the resonance time is varied, there is a variation in the increased amount of the voltage at the node N1 from the time when the node N1 is connected to the power supply terminal V1 with the transistor Q1 turning on, until the time when the voltage at the node N1 reaches the power supply voltage.
  • Fig. 9 is a diagram showing an example of the relationship between the recovery time and the reactive power loss, which exhibits data representing measurements of the reactive power loss per pulse obtained when the resonance time is fixed to 1300 ns and the recovery time is varied. It is found that the reactive power loss per pulse becomes smaller as the recovery time becomes longer, as shown in Fig. 9.
  • Fig. 10 is a diagram showing an example of the relationship between lighting rates provided in respective recovery times and a stable discharge voltage at which stable discharge can be carried out. It is understood that the stable discharge voltage becomes higher as the recovery time becomes longer even in the case of the same lighting rate, as shown in Fig. 10. In the case where the recovery time is 1300 ns, for example, it is understood that stable discharge can be carried out at or below the sustain voltage Vsus of sustain pulses when the lighting rate is in the range of 0 to 10 %, whereas stable discharge cannot be carried out at the sustain voltage Vsus at the time when the lighting rate exceeds approximately 25 %.
  • the recovery time is set longer in the case of a smaller lighting rate, whereas the recovery time is set shorter in the case of a larger lighting rate, so that the reactive power is reduced in the case of a smaller lighting rate while stable discharge is carried out in both cases of smaller and larger lighting rates.
  • the recovery time is set to 1300 ns in the range of the lighting rate from 0 to 10 %, 1100 ns in the lighting rate range of from 10 to 50 %, 900 ns in the range of from 50 to 80 %, 700 ns in the range of from 80 to 90 %, and 600 ns in the range of from 90 to 100 %, by using the solid lines shown in Fig. 10.
  • the subfield processor 3 generates control signals S1 to S4 so that the time period TA may be 1300 ns in the case of the lighting rate being 0 to 10 %, generates the signals S1 to S4 so that the time period TA may be 1100 ns in the case of the lighting rate being 10 to 50 %, generates the same so that the time period TA may be 900 ns in the case of the lighting rate being 50 to 80 %, generates the same so that the time period TA may be 700 ns in the case of the lighting rate being 80 to 90 %, and generates the same so that the time period TA may be 600 ns in the case of the lighting rate being 90 to 100 %.
  • the subfield processor 3 generates control signals S1 to S4 so that the sustain period may be 8 ⁇ s in the case of the lighting rate being 0 to 10 %, generates the same so that the sustain period may be 7 ⁇ s in the case of the lighting rate being 10 to 50 %, and generates the same so that the sustain period may be 6 ⁇ s in the case of the lighting rate being 80 to 100 %. This makes it possible to ensure the sufficient recovery time with the period of drive pulses set longer in the case of a smaller lighting rate.
  • the lighting rate for each subfield is detected, and the recovery time and the sustain period of sustain pulses are set longer as the detected lighting rate for each subfield becomes smaller. Accordingly, stable discharge can be carried out with the recovery time set shorter in the case of a larger lighting rate, while the reactive power can be reduced with the recovery time set longer in the case of a smaller lighting rate. Consequently, even though the lighting rate is variable, the stable discharge can be carried out with the decreased reactive power and the decreased power consumption.
  • the plasma display device in this embodiment can be realized with a simple circuit configuration.
  • Fig. 11 is a block diagram showing the structure of the plasma display device according to the second embodiment of the present invention.
  • the plasma display device of Fig. 11 differs from that of Fig. 1 in that an inductance control circuit 9 is added that varies an inductance value of a scan driver 5a and that of a sustain driver 6a depending on the lighting rate for each subfield. Since the plasma display device of Fig. 11 is the same as that of Fig. 1 with respect to the remaining parts, identical parts are denoted with identical symbols, and only the control of the resonance time depending on the lighting rate will be described in detail as a different part. Like the first embodiment, the recovery time and the sustain period are controlled depending on the lighting rate also in this embodiment.
  • the inductance control circuit 9 shown in Fig. 11 receives a subfield lighting rate signal SL output from a subfield lighting rate measuring unit 8 to output to the scan driver 5a and the sustain driver 6a, respectively, inductance control signals LC and LU for controlling the inductance value that contributes to the LC resonance depending on the lighting rate for each subfield.
  • Fig. 12 is a block diagram showing the structure of the inductance control circuit 9 shown in Fig. 11.
  • the inductance control circuit 9 of Fig. 12 includes a lighting rate/inductance LUT 91 and an inductance determining unit 92.
  • the lighting rate/inductance LUT 91 is connected to the inductance determining unit 92 and stores in a table format the relationship between the lighting rate and the inductance value contributing to the LC resonance based on experimental data. For example, 1800 nH is stored as the inductance value with respect to the lighting rate of 0 to 50 %, 1300 nH as the inductance value with respect to the lighting rate of 50 to 80 %, 520 nH as the inductance value with respect to the lighting rate of 80 to 90 %, and 360 nH as the inductance value with respect to the lighting rate of 90 to 100 %.
  • the inductance determining unit 92 reads a corresponding inductance value from the lighting rate/inductance LUT 91 in response to the subfield lighting rate signal SL output from the subfield lighting rate measuring unit 8, so as to output to the scan driver 5a and the sustain driver 6a, respectively, the inductance control signals LC and LU for setting the inductance values that contribute to the LC resonance of the scan driver 5a and the sustain driver 6a at the read inductance value. Determination of the inductance value is not particularly limited to the above example that the relationship between the lighting rate and the inductance value based on experimental data is stored in a table format, but the inductance value corresponding to the lighting rate may be evaluated by an approximate expression representing the relationship between the lighting rate and the inductance value.
  • the inductance control circuit 9 controls the inductance values contributing to the LC resonance of the scan driver 5a and the sustain driver 6a depending on the lighting rate measured by the subfield lighting rate measuring unit 8.
  • Fig. 13 is circuit diagram showing the structure of the sustain driver shown in Fig. 11. Since the scan driver 5a in this embodiment is also configured and operates similarly to the sustain driver 6a, a detailed description as to the scan driver 5a will not be given. Only the sustain driver 6a will now be described in detail.
  • the sustain driver 6a of Fig. 13 differs from the sustain driver 6 of Fig. 3 in that the recovery coil L is replaced with a variable inductance unit VL that varies the inductance value on the basis of the inductance control signal LU. Since the remaining parts are the same as those in the sustain driver 6 shown in Fig. 3, the identical parts are denoted with the identical symbols, and only the different parts will now be describe in detail.
  • variable inductance unit VL of Fig. 13 is connected between nodes N2 and N1 and varies the inductance value on the basis of the inductance control signal LU output from the inductance control circuit 9.
  • Fig. 14 is a circuit diagram showing an example of the variable inductance unit VL shown in Fig. 13.
  • the variable inductance unit VL of Fig. 14 includes recovery coils LA to LD and transistors QA to QD.
  • the recovery coil LA and the transistor QA are connected in series between the nodes N1 and N2, and the recovery coils LB to LD and the transistor QB to QD are likewise connected in series, respectively, between the nodes N1 and N2.
  • the transistors QA to QD have their gates provided with inductance control signals SA to SD, respectively.
  • the inductance control signals SA to SD are signals output as the inductance control signal LU from the inductance determining unit 92 shown in Fig. 12.
  • the transistors Q3, Q4, the recovery capacitor Cr, the variable inductance unit VL and the diodes D1 and D2 correspond to recovery means;
  • the subfield processor 3 and the inductance control circuit 9 correspond to control means;
  • the variable inductance unit VL corresponds to inductance means and variable inductance means;
  • the recovery coils LA to LD correspond to inductance elements;
  • the transistors QA to QD correspond to selection means.
  • the other parts are the same as those in the first embodiment.
  • Fig. 15 is a schematic diagram showing the on/off states of the transistors QA to QD in the variable inductance unit VL of Fig. 14 and drive waveforms provided at the time when sustain pulses Psu rise corresponding to the respective states.
  • inductance control signals SA to SD are output at a high level from the inductance determining unit 92 to turn the transistors QA to QD on, then the recovery coils LA to LD are connected in parallel between the nodes N2 and N1. Accordingly, a composite inductance value of the variable inductance unit VL becomes a minimum value, e. g., 360 nH, and the resonance time is 600 ns.
  • the drive waveform provided at the time when the sustain pulses Psu rise becomes such a drive waveform as to have a lower peak voltage Vp and a shorter recovery time.
  • the inductance control signals SA to SC are output at a high level from the inductance determining unit 92, while the inductance control signal SD is output at a low level therefrom to turn the transistors QA to QC on and the transistor QD off, then the recovery coils LA to LC are connected in parallel between the nodes N2 and N1. Accordingly, the composite inductance value of the variable inductance unit VL becomes a larger value, e. g., 680 nH, and the resonance time is 800 ns. As a result, the drive waveform provided at the time when the sustain pulses Psu rise has a higher peak voltage Vp and a longer recovery time.
  • the inductance control signals SA and SB are output at a high level from the inductance determining unit 92, while the inductance control signals SC and SD are output at a low level therefrom to turn the transistors QA and QB on and the transistors QC and QD off, then the recovery coils LA and LB are connected in parallel between the nodes N2 and N1. Accordingly, the composite inductance value of the variable inductance unit VL becomes a still larger value, e. g., 1300 nH, and the resonance time is 1100 ns. As a result, the drive waveform of the sustain pulses Psu has a still higher peak voltage Vp and a still longer recovery time.
  • the inductance value of the variable inductance unit VL becomes the inductance value of the recovery coil LA, that is , a maximum inductance value, e.g., 1800 nH, and the resonance time is 1300 ns.
  • the drive waveform of the sustain pulses Psu has a maximum peak voltage and the longest recovery time.
  • Fig. 16 is a diagram showing an example of the relationship between the resonance time and the loss of reactive power. It is understood as shown in Fig. 16 that the reactive power loss per pulse becomes decreased as the resonance time becomes increased. Therefore, the reactive power loss per pulse can be decreased by the increase of the inductance value contributing to the LC resonance.
  • the recovery time and the sustain period are controlled depending on the lighting rate for each subfield, and also, the inductance value of the variable inductance unit VL and the resonance time are increased as the lighting rate for each subfield becomes decreased. Therefore, since it is possible to set the inductance value larger and the resonance time longer in the case of a lower lighting rate, the reactive power can be more decreased with the improved recovery efficiency.
  • Fig. 17 is a circuit diagram showing the structure of another example of the variable inductance unit LU shown in Fig. 13.
  • the variable inductance unit of Fig. 17 includes recovery coils LA' to LD' and transistors QA' to QD'.
  • the recovery coil LA' and the transistor QA' are connected in parallel.
  • the recovery coils LB' to LD' are connected in parallel to the transistors QB' to QD', respectively.
  • Those recovery coils LA' to LD' and transistors QA' to QD' connected in parallel are connected in series between nodes N2 and N1.
  • the transistors QA' to QD' have their respective gates provided with inductance control signals SA' to SD', respectively.
  • the inductance control signals SA' to SD' are signals output as the inductance control signal LU from the inductance determining unit 92 shown in Fig. 12.
  • Fig. 18 is a schematic diagram showing the on/off states of the transistors QA' to QD' in the variable inductance unit of Fig. 17 and drive waveforms provided at the time when sustain pulses Psu rise corresponding to the respective states.
  • the inductance control signals SA' to SC' are output at a high level from the inductance determining unit 92, while the inductance control signal SD' is output at a low level therefrom to turn the transistors QA' to QC' on and the transistor QD' off, then the recovery coil LD' is connected between the nodes N2 and N1. Accordingly, the composite inductance value of the variable inductance unit becomes the inductance value of the recovery coil LD', that is, a minimum inductance value, e.g., 360 nH, and the resonance time is 600ns. As a result, the waveform provided at the time the sustain pulses Psu rise has a lower peak voltage Vp and a shorter recovery time.
  • the inductance control signals SA' and SB' are output at a high level from the inductance determining unit 92, while the inductance control signals SC' and SD' are output at a low level therefrom to turn the transistors QA' and QB' on and the transistors QC' and QD' off, then the recovery coils LC' and LD' are connected in series between the nodes N2 and N1. Accordingly, the composite inductance value of the variable inductance unit becomes a sum of the respective inductance values of the recovery coils LC' and LD', that is, a larger inductance value, e. g., 680 nH, and the resonance time is 800 ns. As a result, the drive waveform provided when the sustain pulses Psu rise has a higher peak voltage Vp and a longer recovery time.
  • the inductance control signal SA' is output at a high level from the inductance determining unit 92, while the inductance control signals SB' to SD' are output at a low level therefrom to turn the transistor QA' on and the transistors QB' to QD' off, then the recovery coils LB' to LD' are connected in series between the nodes N2 and N1. Accordingly, the composite inductance value of the variable inductance unit becomes a sum of the respective inductance values of recovery coils LB' to LD', that is, a still larger inductance value, e. g., 1300 nH, and the resonance time is 1100 ns. As a result, the drive waveform of the sustain pulses Psu has a still higher peak voltage Vp and a still longer recovery time.
  • the inductance control signals SA' to SD' are output at a low level from the inductance determining unit 92 to turn the transistors QA' to QD' off, then the recovery coils LA' to LD' are connected in series between the nodes N2 and N1. Accordingly, the composite inductance value of the variable inductance becomes a sum of the respective inductance values of the recovery coils LA' to LD', that is, a maximum inductance value, e. g., 1800 nH, and the resonance time is 1300 ns. Consequently, the drive waveform of the sustain pulses Psu has a maximum peak voltage Vp and the longest recovery time.
  • variable inductance unit of Fig. 17 As in the variable inductance unit VL of Fig. 14 as described above.
  • variable inductance unit its structure is not particularly limited to each of the aforementioned examples, but another structure that an inductance value is variable on the basis of inductance control signals is also applicable.
  • Fig. 19 is a block diagram showing the structure of the plasma display device according to the third embodiment of the present invention.
  • the plasma display device of Fig. 19 differs from that of Fig. 1 in that the subfield processor 3 is replaced by a subfield processor 3a that controls a scan driver 5b and a sustain driver 6b so that the resonance time, the discharge recovery time and the sustain period are varied depending on the lighting rate. Since the plasma display device of Fig. 19 is the same as that of Fig. 1 in the respect of the other parts, the identical parts are denoted with the identical characters, and only the different parts will now be described in detail.
  • the subfield processor 3a of Fig. 19 produces a scan driver driving control signal CS and a sustain driver driving control signal US for varying the resonance time, the discharge recovery time and the sustain period in response to a subfield lighting rate signal SL, so as to output the produced signals CS and US to the scan driver 5b and the sustain driver 6b, respectively.
  • the scan driver 5b and the sustain driver 6b operate in response to the scan driver driving control signal CS and the sustain driver driving control signal US, respectively, to vary the resonance time, the discharge recovery time and the sustain period of sustain pulses depending on the lighting rate and output the results to scan electrodes 12 and sustain electrodes 13 of a PDP 7.
  • Fig. 20 is a block diagram showing the structure of the subfield processor 3a shown in Fig. 19.
  • the subfield processor 3a of Fig. 20 is different from the subfield processor 3 of Fig. 4 in that a lighting rate/resonance time LUT 36 and a resonance time determining unit 37 are added, and a discharge control signal generator 35a substitues for the discharge control signal generator 35. Since the processor 3a is the same as the processor 3 of Fig. 4 in the respect of the other parts, the identical parts are denoted with the identical characters, and a detailed description thereof will not be given.
  • the lighting rate/resonance time LUT 36 shown in Fig. 20 is connected to the resonance time determining unit 37 and stores in a table format the relationship between the lighting rate and the resonance time based on experimental data.
  • 1300 ns is stored as the resonance time with respect to the lighting rate of from 0 to 10 %, 1200 ns as the resonance time with respect to the lighting rate of from 10 to 20 %, 1100 ns as the resonance time with respect to the lighting rate of from 20 to 30 %, 1000 ns as the resonance time with respect to the lighting rate of from 30 to 40 %, 850 ns as the resonance time with respect to the lighting rate of from 40 to 50 %, 800 ns as the resonance time with respect to the lighting rate of from 50 to 60 %, 750 ns as the resonance time with respect to the lighting rate of from 60 to 70 %, 700 ns as the resonance time with respect to the lighting rate of from 70 to 80 %, and 600 ns as the resonance time with respect to the
  • the resonance time determining unit 37 is connected to the discharge control signal generator 35a and reads a corresponding resonance time from the lighting rate/resonance time LUT 36 in response to the subfield lighting rate signal SL output from the subfield lighting rate measuring unit 8, so as to output the read resonance time to the discharge control signal generator 35. Determination of the resonance time is not particularly limited to the above example that the relationship between the lighting rate and the resonance time based on the experimental data is stored in the table format, but the resonance time corresponding to the lighting rate may be evaluated by an approximate expression representing the relationship between the lighting rate and the resonance time.
  • the lighting rate/recovery time LUT 31 stores 1100 ns as the discharge recovery time with respect to the lighting rate of from 0 to 10 %, 1000 ns as the discharge recovery time with respect to the lighting rate of from 10 to 20 %, 900 ns as the discharge recovery time with respect to the lighting rate of from 20 to 30 %, 800 ns as the discharge recovery time with respect to the lighting rate of from 30 to 40 %, 700 ns as the discharge recovery time with respect to the lighting rate of from 40 to 50 %, 650 ns as the discharge recovery time with respect to the lighting rate of from 50 to 60 %, 600 ns as the discharge recovery time with respect to the lighting rate of from 60 to 70 %, 550 ns as the discharge recovery time with respect to the lighting rate of from 70 to 80 %, and 500 ns with respect to the lighting rate of from 80 to 100 %.
  • the recovery time and the resonance time are set such that a difference between the recovery time and the resonance time becomes increased as the lighting rate becomes decreased.
  • Each discharge recovery time as above is set shorter than each resonance time in order to enhance the stability of discharge. Further, in this embodiment, the non-discharge recovery time is fixed to 1300 ns in order to reduce reactive power irrespective of the lighting rate.
  • the lighting rate/sustain period LUT 33 stores, for example, 8 ⁇ s as the sustain period with respect to the lighting rate of from 0 to 20 %, 7 ⁇ s as the sustain period with respect to the lighting rate of from 20 to 40 %, 6 ⁇ s as the sustain period with respect to the lighting rate of from 40 to 80 %, and 5 ⁇ s as the sustain period with respect to the lighting rate of from 80 to 100 %.
  • the discharge control signal generator 35a outputs control signals S1 to S5 as the sustain driver driving control signal US so that the sustain driver 6b outputs sustain pulses in the resonance time determined by the resonance time determining unit 37, the discharge recovery time determined by the recovery time determining unit 32 and the sustain period determined by the sustain period determining unit 34.
  • the scan driver 5b is also controlled by the subfield processor 3a, and the waveform and the period of the sustain pulses to be applied to the scan electrodes 12 are likewise controlled depending on the lighting rate for each subfield.
  • Fig. 21 is a circuit diagram showing the structure of the sustain driver 6b of Fig. 19. Since the scan driver 5b in this embodiment is also structured and operative like the sustain driver 6b, a detailed description as to the scan driver 5b will not be given, and only the sustain driver 6b will be described in detail.
  • the sustain driver 6b of Fig. 21 is different from the sustain driver 6 of Fig. 3 in that a recovery coil L1 is connected in parallel to a diode D3, a transistor Q5 and a recovery coil L2 connected in series between nodes N2 and N1. Since the sustain driver 6b of Fig. 21 is the same as the sustain driver 6 of Fig. 3 in the respect of the other parts, the identical parts are denoted with the identical characters, and a detailed description of the other parts will not be given.
  • the recovery coil L1 is connected between the nodes N2 and N1.
  • the inductance value of the recovery coil L1 is, e. g. , 1800 nH.
  • the diode D3, the transistor Q5 and the recovery coil L2 are connected in series between the nodes N2 and N1.
  • the inductance value of the recovery coil L2 is, e. g. , 450 nH.
  • the recovery coils L1 and L2 contribute to the LC resonance.
  • An inductance value contributing to such LC resonance at this time becomes 360 nH, which is a composite inductance value of the recovery coils L1 and L2.
  • Fig. 22 is a diagram showing an example of the relationship between the resonance time and the delay time caused by the recovery coils L1 and L2.
  • the delay time is 0 ns, i. e., the transistors Q3 and Q5 are turned on at the same time
  • the inductance value contributing to the LC resonance is 360 nH, which is the composite inductance value of the recovery coils L1 and L2, and the resonance time is 600 ns.
  • the delay time becomes increased, the proportion of 1800 nH, which is the inductance value of the recovery coil L1 becomes increased, and the inductance value contributing to the LC resonance becomes increased.
  • the resonance time becomes also increased, and finally, the inductance value contributing to the LC resonance becomes 1800 nH, which is the inductance value of the recovery coil L1, and the resonance time is 1300 ns. Accordingly, adjustment of the delay time enables the inductance value contributing to the LC resonance to be set to a predetermined value in the range of from 360 to 1800 nH, and enables the resonance time to be set to a desired time from 600 to 1300 ns.
  • the transistors Q3 to Q5, the recovery capacitor Cr, the recovery coils L1 and L2, and the diodes D1 to D3 correspond to recovery means; the subfield processor 3a to control means; the diode D3, the translator Q5 and the recovery coils L1 and L2 to inductance means and variable inductance means; the recovery capacitor Cr to a capacitive element; the recovery coil L1 to a first inductance element; the recovery coil L2 to a second inductance element; the diode D1 and the transistor Q3 to first switch means; and the diode D3 and the transistor Q5 to second switch means.
  • the remaining parts are the same as those in the first embodiment.
  • Figs. 23 to 26 are timing charts showing operations of the sustain driver 6b of Fig. 21 during the sustain time period.
  • Figs. 23 to 26 show the voltage on the node N1 of Fig. 21 and the control signals S1 to S5.
  • the control signal S2 attains a low level to turn the transistor Q2 off
  • the control signal S3 attains a high level to turn the transistor Q3 on
  • the control signal S5 attains a high level to turn the transistor Q5 on
  • the delay time is 0 ns.
  • the control signals S1 and S4 attain a low level to turn the transistors Q1 and Q4 off.
  • the recovery capacitor Cr is connected to the recovery coil L1 through the transistor Q3 and the diode D1 and also to the recovery coil L2 through the diode 3 and the transistor Q5. Consequently, 360 nH, which is the composite inductance value of the recovery coils L1 and L2 contributes to the LC resonance, and the resonance time is 600 ns.
  • the time period TA which is the discharge recovery time at this time, is 500 ns, during which the voltage on the node N1 rises from a ground potential to a peak voltage Vp1.
  • the discharge cells 14 start discharge to carry out sustain discharge. Further, the charges in the recovery capacitor Cr are exerted to the panel capacitance Cp through the transistor Q3, the diode D1 and the recovery coil L1.
  • the control signal S1 attains a high level to turn the transistor Q1 on, and the control signals S3 and S5 attain a low level to turn the transistors Q3 and Q5 off. Accordingly, the node N1 is connected to the power supply terminal V1, so that the voltage on the node N1 rises sharply and is then fixed to a sustain voltage Vsus.
  • the control signal S1 attains a low level to turn the transistor Q1 off, and the control signal S4 attains a high level to turn the transistor Q4 on.
  • the recovery capacitor Cr is connected to the recovery coil L1 through the diode 2 and the transistor Q4, so that the LC resonance caused by the recovery coil L1 and the panel capacitance Cp causes a gradual drop of the voltage on the node N1.
  • the charges stored in the panel capacitance Cp are stored in the recovery capacitor Cr through the recovery coil L1, the diode D2 and the transistor Q4 and are then recovered.
  • the recovery coil L1 contributes the LC resonance, so that the inductance value contributing to the LC resonance is 1800 nH, and the resonance time is 1300 ns.
  • the time period TC which is the non-discharge recovery time at this time, is 1300 ns, that is, the non-discharge recovery time is coincident with the resonance time.
  • the control signal S2 attains a high level to turn the transistor Q2 on, and the control signal S4 attains a low level to turn the transistor Q4 off.
  • the node N1 is connected to the ground terminal, so that the voltage on the node N1 falls and is fixed to the ground potential.
  • the inductance value contributing to the LC resonance is the composite inductance value of the recovery coils L1 and L2 over the entire discharge recovery time, thereby leading to a shorter resonance time and a shorter discharge recovery time.
  • the delay time of the control signal S5 is set.
  • the control signal S3 attains a high level to turn the transistor Q3 on, and after that, the control signal S5 attains a high level after delayed by a delay time DT1, so that the transistor Q5 is turned on.
  • the transistor Q3 is turned on, so that the recovery coil L1 contributes to the LC resonance, whereas the transistor Q5 is off, so that the recovery coil L2 does not contribute to the LC resonance.
  • both the transistors Q3 and Q5 are turned on, so that both the recovery coils L1 and L2 contribute to the LC resonance. This results in a larger inductance value contributing to the LC resonance and a longer resonance time.
  • the resonance time is 800 ns, and a peak voltage Vp2 of the sustain pulses Psu becomes higher than the peak voltage Vp1. Also, the discharge recovery time is made as long as 700 ns, resulting in increased recovery efficiency and decreased reactive power.
  • the delay time of the control signal S5 is made still longer.
  • the control signal S5 attains a high level after delayed by a delay time DT2, so that the transistor Q5 is turned on.
  • the time period during which only the recovery coil L1 contributes to the LC resonance becomes longer, while the time period during which the recovery coils L1 and L2 both contribute to the LC resonance becomes shorter, resulting in a still larger inductance value contributing to the LC resonance and a still longer resonance time.
  • the resonance time is 1100 ns, and a peak voltage Vp3 of the sustain pulses Psu becomes higher than the peak voltage Vp2.
  • the discharge recovery time is made as long as 900 ns, resulting in a more increased recovery efficiency and more decreased reactive power.
  • the control signal S5 is constantly at a low level, and the transistor Q5 is constantly off.
  • the recovery coil L1 contributes to the LC resonance, so that the inductance value contributing to the LC resonance becomes as large as 1800 nH, the resonance time becomes as long as 1300 ns, and the discharge recovery time is also made as long as 1300 ns. Consequently, a peak voltage Vp4 of the sustain pulses Psu is still higher than the peak voltage Vp3, leading to a more increased recovery efficiency and more decreased reactive power.
  • the time period TA which is the discharge recovery time
  • the inductance value contributing to the LC resonance is made larger with the resonance time made longer.
  • the discharge recovery time and the sustain period are varied together depending on the lighting rate in this embodiment, only the discharge recovery time and the resonance time may be varied without variation of the sustain period.
  • Fig. 27 is a circuit diagram showing the structure of another example of the sustain driver 6b of Fig. 19.
  • a sustain driver 6b' of Fig. 27 differs from the sustain driver 6b in that the diode D3 and the transistor Q5 are omitted, and the recovery coil L2 is connected to the recovery capacitor Cr through a transistor Q6 and a diode D4. Since the remaining parts of the sustain driver 6b' are the same as those of the sustain driver 6b of Fig. 21, the identical parts are denoted with the identical characters, and a detailed description thereof will not be given.
  • a transistor Q3, a diode D1 and a recovery coil L1 connected in series are connected in parallel, between the recovery capacitor Cr and a node N1, to the transistor Q6, the diode 4 and the recovery coil L2 connected in series.
  • the transistor Q6 has its gate provided with a control signal S5.
  • the sustain driver 6b' of Fig. 27 can also operate in the same manner and achieve the same effect as the sustain driver 6b of Fig. 21. Further, since only one transistor Q6 and one diode D4 are connected between the recovery capacitor Cr and the recovery coil L2, in the sustain driver 6b' of Fig. 27, a loss occurring along a current path can be more decreased with more decreased reactive power as compared to such a case that two transistors Q3 and Q5 and two diodes D1 and D3 are connected as in the sustain driver 6b of Fig. 21.
  • Fig. 28 is a circuit diagram showing the structure of still another example of the sustain driver of Fig. 19.
  • a sustain driver 6b" of Fig. 28 differs from the sustain driver 6b' of Fig. 27 in that the diode D2 is separated from the node N2, and a recovery coil L3 is provided between the diode D2 and the node N1. Since the remaining parts of the sustain driver 6b" are the same as those of the sustain driver 6b of Fig. 27, the identical parts are denoted with identical characters, and a detailed description thereof will not be given.
  • the recovery coil has its one end connected to the node N1 and the other end connected to an anode of the diode 2. Accordingly, the recovery coil that contributes to the LC resonance in a time period TC which is the non-discharge recovery time is the recovery coil L3.
  • the inductance value that contributes to the LC resonance in the non-discharge recovery time can be set to an arbitrary value independently of the inductance value that contributes to the LC resonance in the discharge recovery time.
  • the recovery time can be made sufficiently long without consideration of any discharge stability. For example, if the recovery time is set to 2000 ns, and the inductance value of the recovery coil L3 is set to such an inductance value that the resonance time is 2000 ns, then the non-discharge recovery time can be made still longer, resulting in more decreased reactive power.
  • Fig. 29 is a block diagram showing the structure of the plasma display device according to the fourth embodiment of the present invention.
  • the plasma display device of Fig. 29 differs from that of Fig. 19 in that the subfield processor 3a, the scan driver 5b and the sustain driver 6b are replaced by a subfield processor 3b, a scan driver 5c and a sustain driver 6c for varying the resonance time, the discharge recovery time, the non-discharge recovery time and the sustain period depending on the lighting rate. Since the remaining parts of the plasma display device of Fig. 29 are the same as those of the plasma display device of Fig. 19, the identical parts are denoted with the identical characters, and the different parts will be described in detail.
  • Fig. 30 is a block diagram showing the structure of the subfield processor 3b of Fig. 29.
  • the subfield processor 3b of Fig. 30 is different from the subfield processor 3a of Fig. 20 in that the discharge control signal generator 35a is replaced by a discharge control signal generator 35b that outputs control signals S1 to S5 for varying the resonance time, the discharge recovery time, the non-discharge recovery time and the sustain period depending on the lighting rate. Since the remaining parts of the subfield processor 3b are the same as those of the subfield processor 3a shown in Fig. 20, the identical parts are denoted with the identical characters, and a detailed description thereof will not be given.
  • the discharge control signal generator 35b of Fig. 30 outputs control signals S1 to S5 as the sustain driver driving control signal US so that the sustain driver 6c outputs sustain pulses in the resonance time determined by the resonance time determining unit 37, the recovery time, that is, the discharge recovery time and the non-discharge recovery time determined by the recovery time determining unit 32, and in the sustain period determined by the sustain period determining unit 34.
  • the scan driver 5c is also controlled by the subfield processor 3b, so that the waveform and the period of sustain pulses to be applied to the scan electrodes 12 are likewise controlled depending on the lighting rate for each subfield.
  • Fig. 31 is a circuit diagram showing the structure of the sustain driver 6c shown in Fig. 29. Since the scan driver 5c of this embodiment is also structured and operates in the same manner as the sustain driver 6c, a detailed description will now be given only on the sustain driver 6c not on the scan driver 5c.
  • the sustain driver 6c of Fig. 31 is different from the sustain driver 6b of Fig. 21 in that the diode D3 and the transistor Q5 are replaced by two transistors Q7 and Q8. Since the remaining parts of the sustain driver 6c are the same as those of the sustain driver 6b of Fig. 21, a detailed description thereof will not be given, with the identical parts denoted with the identical characters.
  • the transistor Q7 has its drain connected to the node N2 and its source connected to the source of the transistor Q8.
  • the transistor Q8 has its drain connected to the recovery coil L2.
  • Each of the transistors Q7 and Q8 has its gate provided with the control signal S5.
  • the transistors Q3, Q4, Q7 and Q8, the recovery capacitor Cr, the recovery coils L1 and L2, and the diodes D1 and D2 correspond to recovery means; the subfield processor 3b to control means; the transistors Q7 and Q8, and the recovery coils L2 and L2 to inductance means and variable inductance means; and the transistors Q7 and Q8 to second switch means.
  • the remaining parts are the same as those in the third embodiment.
  • Figs. 32 to 35 are timing charts showing operations of the sustain driver 6c of Fig. 31 in the sustain time period.
  • the voltage on the node N1 and the control signals S1 to S5 shown in Fig. 31 are illustrated in Figs. 32 to 35.
  • a time period TA to be the discharge recovery time, and delay times DT1 and DT2 are controlled depending on the lighting rate, while a time period TC to be the non-discharge recovery time, and delay times DT1 and DT2 are also controlled depending on the lighting rate.
  • the lighting rate for each subfield is detected, and as the detected lighting rate for each subfield becomes lower, the discharge recovery time, the non-discharge recovery time, the resonance time and the sustain period at the rising and falling of sustain pulses can become longer, resulting in the same effects as in the first embodiment.
  • discharge recovery time and its resonance time are set equal to the non-discharge recovery time and its resonance time in this embodiment, it may be controlled that they are set to be different times independently of each other.
  • the switch means for use is not particularly limited to this example, but an insulated gate bipolar transistor (IGBT) which is an element that a MOS (Metal Oxide Semiconductor) FET and a bipolar transistor are combine together in one chip, and the like may be employed.
  • IGBT insulated gate bipolar transistor
  • the diode D1 and the transistor Q3, the diode D2 and the transistor Q4, and the diode D3 and the transistor Q5 are used as the switch means in the third embodiment, such two field effect-transistors connected in series may be used as in the fourth embodiment, or an insulated gate bipolar transistor and the like may be used. In this respect, the same is applicable to a fifth embodiment which will be described later.
  • Fig. 36 is a block diagram showing the structure of the plasma display device according to the fifth embodiment of the present invention.
  • the plasma display device of Fig. 36 differs from that of Fig. 19 in that the subfield processor 3a, the scan driver 5b and the sustain driver 6b are replaced by a subfield processor 3c, a scan driver 5d and a sustain driver 6d for varying the resonance time, the discharge recovery time, the non-discharge recovery time and the sustain period depending on the lighting rate. Since the remaining parts of the plasma display device of Fig. 36 are the same as those of the plasma display device of Fig. 19., a detailed description will now be described on the different parts, with the identical parts denoted with the identical characters.
  • Fig. 37 is a block diagram showing the structure of the subfield processor 3c shown in Fig. 36.
  • the subfield processor 3c of Fig. 37 is different from the subfield processor 3a of Fig. 20 in that the discharge control signal generator 35a is replaced by a discharge control signal generator 35c that outputs control signals S1 to S6 for varying the resonance time, the discharge recovery time, the non-discharge recovery time and the sustain period depending on the lighting rate.
  • the remaining parts of the subfield processor 3c are the same as those of the subfield processor 3a of Fig. 20, and hence, a detailed description will not be given, with the identical parts denoted with the identical characters.
  • the discharge control signal generator 35c shown in Fig. 37 outputs control signals S1 to S6 as the sustain driver driving control signal US so that the sustain driver 6d outputs sustain pulses in the recovery time determined by the recovery time determining unit 32, i. e., the discharge recovery time and the non-discharge recovery time, and in the sustain period determined by the sustain period determining unit 34.
  • the scan driver 5d is also controlled by the subfield processor 3c, and the waveform and the period of sustain pulses to be applied to the scan electrodes 12 are likewise controlled depending on the lighting rate for each subfield.
  • Fig. 38 is a circuit diagram showing the structure of the sustain driver 6d of Fig. 36. Since the scan driver 5d of this embodiment is also structured and operative like the sustain driver 6d, a detailed description will now be made only on the sustain driver 6d, but not on the scan driver 5d.
  • the sustain driver 6d of Fig. 38 is different from the sustain driver 6b of Fig. 21 in that the diode D3 and the transistor Q5 are omitted, and the recovery coil L2 is connected to the recovery capacitor Cr through a transistor Q9 and a diode D5 and through a transistor Q10 and a diode D6. Since the remaining parts of the sustain driver 6d are the same as those of the sustain driver 6b of Fig. 21, a detailed description will not be given, with the identical parts denoted with the identical characters.
  • the transistor Q9 and the diode D5 connected in series are connected in parallel to the transistor Q10 and the diode D6 connected in series, between the recovery capacitor Cr and the recovery coil L2.
  • the transistor Q9 has its gate provided with the control signal S5, while the transistor Q10 has its gate provided with the control signal S6.
  • the sustain driver 6d shown in Fig. 38 it is possible, in the sustain driver 6d shown in Fig. 38, to turn on/off bi-directional currents between a node N4 and the node N3, and thus, it is possible to independently control the connection state of the recovery coil L2 being connected in parallel to the recovery coil L1. This makes it possible to vary the resonance time and the discharge recovery time at the rising of sustain pulses Psu and vary the resonance time and the non-discharge recovery time at the falling of the sustain pulses Psu.
  • the transistors Q3, Q4, Q9, Q10, the recovery capacitor Cr, the recovery coils L1, L2, and the diodes D1, D2, D5, D6 correspond to recovery means; the subfield processor 3c to control means; the transistors Q9, Q10, the diodes D5, D6, and the recovery coils L1, L2 to inductance means and variable inductance means; the diode D5 and the transistor Q9 to second switch means; the diode D2 and the transistor Q4 to third switch means; and the diode D6 and the transistor Q10 to fourth switch means.
  • the remaining parts are the same as those of the third embodiment.
  • Figs. 39 to 42 are timing charts showing operations of the sustain driver 6d of Fig. 38 in the sustain time period.
  • the voltage on the node N1 and the control signals S1 to S6 are illustrated in Figs. 39 to 42.
  • a time period TA to be the discharge recovery time and delay times DT1 and DT2 are controlled depending on the lighting rate, while a time period TC to be the non-discharge recovery time and delay times DT1 and DT2 are controlled depending on the lighting rate, like the fourth embodiment.
  • the lighting rate for each subfield is detected. As the detected lighting rate for each subfield becomes lower, the discharge recovery time, the non-discharge recovery time, the resonance time and the sustain period at the rising and falling of sustain pulses can become longer, resulting in achievement of the same effect as in the first embodiment.
  • the on/off states of the transistors Q9 and Q10 can independently be controlled by the control signals S5 and S6, it is possible to independently control the resonance time at the rising of sustain pulses and that at the falling of the sustain pulses. Also, the recovery coil L2 is employed at both the rising and falling of the sustain pulses, thereby enabling a simplified circuit configuration.
  • discharge recovery time and its resonance time are set equal to the non-discharge recovery time and its resonance time in this embodiment, it may be controlled that they are independently different times from each other.
  • Fig. 43 is a block diagram showing the structure of the plasma display device according to the sixth embodiment of the present invention.
  • the plasma display device of Fig. 43 is different from that of Fig. 36 in that the subfield processor 3c, the scan driver 5d and the sustain driver 6d are replaced by a subfield processor 3d, a scan driver 5e and a sustain driver 6e for varying the resonance time and the sustain period depending on the lighting rate. Since the remaining parts of the plasma display device of Fig. 43 are the same as those of the plasma display device of Fig. 36, the identical parts are denoted with the identical characters, and a detailed description will now be made on the different parts.
  • Fig. 44 is a block diagram showing the structure of the subfield processor 3d shown in Fig. 43.
  • the subfield processor 3d of Fig. 44 differs from the subfield processor 3c of Fig. 37 in that the discharge control signal generator 35c is replaced by a discharge control signal generator 35d that outputs control signals S1 to S6 for varying the resonance time and the sustain period depending on the lighting rate, with the recovery time fixed, and that neither the lighting rate/recovery time LUT 31 nor the recovery time determining unit 32 is provided. Since the remaining parts of the subfield processor 3d of Fig. 44 are the same as those of the processor 3c, the identical parts are denoted with the identical characters, and a detailed description will not be given.
  • the discharge control signal generator 35d shown in Fig. 44 outputs control signals S1 to S6 as the sustain driver driving control signal US so that the sustain driver 6e outputs sustain pulses in the resonance time determined by the resonance time determining unit 37 and in the sustain period determined by the sustain period determining unit 34.
  • the scan driver 5e is also controlled by the subfield processor 3d, and the waveform and the period of the sustain pulses to be applied to the scan electrodes 12 are likewise controlled depending on the lighting rate for each subfield.
  • the structure of the sustain driver 6e shown in Fig. 43 is the same as that of the sustain driver 6d shown in Fig. 38. Further, the scan driver 5e shown in Fig. 43 is also structured and operative like the sustain driver 6e.
  • the sustain driver 6e and that of the scan driver 5e such a structure as of the sustain driver 6b of Fig. 21, the sustain driver 6b' of Fig. 27, the sustain driver 6" of Fig. 28, the sustain driver 6c of Fig. 31 or the sustain driver 6d of Fig. 38 may be employed.
  • the subfield processor 3d of Fig. 44 varies the resonance time and the sustain period depending on the lighting rate, with the recovery period fixed.
  • Fig. 45 is a diagram showing an example of the relationship between the resonance time and the loss of reactive power, which exhibits data that the loss of reactive power per pulse is measured when the recovery time is fixed to 700 ns and the resonance time is varied. It is understood, as shown in Fig. 45, that the reactive power loss per pulse becomes decreased as the resonance time becomes shorter.
  • Fig. 46 is a diagram showing an example of the relationship between the lighting rate in each resonance time and the stable discharge voltage at which stable discharge can be carried out. It is understood, as shown in Fig. 46, that the stable discharge voltage becomes higher as the resonance time becomes longer even at the same lighting rate. It is found that when the resonance time is 1000 ns, for example, the stable discharge can be carried out at or below a sustain voltage Vsus of sustain pulses Psu at the lighting rate from 0 to 40 %, whereas the stable discharge cannot be harried out at the sustain voltage Vsus at the time the lighting rate exceeds approximately 40 %.
  • the stable discharge can be carried out at both a larger lighting rate and a smaller lighting rate.
  • the resonance time is longer, the stable light emission can be carried out at a smaller lighting rate, whereas the stable discharge cannot be carried out at a larger lighting rate.
  • the resonance time is set longer at a smaller lighting rate, whereas the resonance time is set shorter at a larger lighting rate.
  • reactive power is reduced at a larger lighting rate while the stable discharge is carried out at both larger and smaller lighting rates.
  • the resonance time is set to 1000 ns at the lighting rate from 0 to 20 %, 900 ns at the lighting rate from 20 to 50 %, 800 ns at the lighting rate from 50 to 80 %, and 700 ns at the lighting rate from 80 to 100 %.
  • the subfield processor 3 generates control signals S1 to S6 so that the sustain period be 8 ⁇ s at the lighting rate from 0 to 20 %, 7 ⁇ s at the lighting rate from 20 to 50 %, and 6 ⁇ s at the lighting rate from 80 to 100 %. Accordingly, the period of drive pulses is made longer at a smaller lighting rate, so as to ensure the sufficient resonance time.
  • the lighting rate for each subfield is detected, and thus, as the detected lighting rate for each subfield becomes smaller, the resonance time and the sustain period of the sustain pulses are made longer.
  • the stable discharge voltage constant by setting the resonance time longer at a smaller lighting rate while setting it shorter at a larger lighting rate.
  • setting the shorter resonance time enables the stable discharge and improved reactive efficiency and decreased reactive power.
  • the recovery time is fixed, a period of clamping to a power supply voltage can be made constant, allowing an increased discharge stability. Consequently, even though the lighting rate varies, the stable discharge can be carried out, resulting in the decreased reactive power and decreased power consumption.
  • the same structures as those of the inductance control circuit 9 and the sustain driver 6a shown in Figs. 11 to 13 may be used as structures for varying the resonance time depending on the lighting rate.
  • the present invention is likewise applicable to the case with pulses of negative polarity that discharge is carried out at the falling of sustain pulses.
  • the recovery time and the like are set so that stable discharge can always be made depending on the lighting rate at the time of falling of sustain pulses when discharge is carried out and that the reactive power can be decreased.
  • the drive pulses can be driven in an optimum recovery time and an optimum LC resonance time corresponding to the lighting rate. Therefore, in the case of a larger lighting rate, setting a shorter recovery time enables the stable discharge, and setting a shorter resonance time enables the decreased reactive power. On the other hand, in the case of a smaller lighting rate, setting a longer recovery time enables the decreased reactive power. This makes it possible to carry out the stable discharge and decrease the reactive power and power consumption even though the lighting rate is varied.
  • the drive pulses can be driven in the optimum recovery time and the optimum LC resonance time corresponding to the lighting rate. Accordingly, it is made possible to make the stable discharge voltage constant by setting the inductance value of the inductance element larger to set the resonance time longer in the case of a smaller lighting rate, while setting the inductance value of the inductance element smaller to set the resonance time shorter in the case of a larger lighting rate.
  • setting a shorter resonance time enables the stable discharge, and increasing the recovery efficiency enables the decreased reactive power.
  • setting a fixed recovery time allows the increased discharge stability. This makes it possible to carry out the stable discharge and thus decrease the reactive power and the power consumption even though the lighting rate is varied.
EP01963523A 2000-09-13 2001-09-07 Anzeige und ihr ansteuerverfahren Withdrawn EP1331623A4 (de)

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JP2000277878 2000-09-13
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JP2001266383A JP3390752B2 (ja) 2000-09-13 2001-09-03 表示装置およびその駆動方法
JP2001266383 2001-09-03
PCT/JP2001/007792 WO2002023518A1 (fr) 2000-09-13 2001-09-07 Dispositif d'affichage et procede de commande associe

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CN (1) CN1264129C (de)
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EP1667096A1 (de) 2004-11-24 2006-06-07 Samsung SDI Co., Ltd. Plasmaanzeige und Verfahren zu ihrer Ansteuerung
EP1708161A2 (de) * 2005-03-30 2006-10-04 LG Electronics Inc. Plasmaanzeigevorrichtung und Verfahren zu ihrer Ansteuerung
EP1760685A2 (de) * 2005-09-06 2007-03-07 LG Electronics Inc. Plasmaanzeigevorrichtung
CN100369083C (zh) * 2004-10-10 2008-02-13 东南大学 槽型等离子体显示板行电极的驱动电路及其驱动方法
CN100369084C (zh) * 2004-10-14 2008-02-13 东南大学 槽型等离子体显示板的高电压扫描维持驱动电路及其驱动方法
EP1901266A3 (de) * 2006-09-15 2008-10-29 Samsung SDI Co., Ltd. Plasmaanzeigevorrichtung und Verfahren zu ihrer Ansteuerung

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KR20040016020A (ko) * 2002-08-14 2004-02-21 엘지전자 주식회사 플라즈마 디스플레이 패널의 에너지 회수장치 및 그의구동방법
WO2004055770A1 (ja) * 2002-12-13 2004-07-01 Matsushita Electric Industrial Co., Ltd. プラズマディスプレイパネルの駆動方法
EP1486938A4 (de) * 2002-12-13 2009-01-14 Panasonic Corp Plasmaanzeigetafelansteuerverfahren
JP4619014B2 (ja) 2003-03-28 2011-01-26 株式会社日立製作所 プラズマディスプレイパネルの駆動方法
KR100578802B1 (ko) * 2003-11-27 2006-05-11 삼성에스디아이 주식회사 플라즈마 표시 장치와 플라즈마 표시 패널의 구동 방법 및구동 장치
JP2005266330A (ja) * 2004-03-18 2005-09-29 Pioneer Electronic Corp プラズマディスプレイ表示装置及びその駆動方法
JP4611677B2 (ja) * 2004-07-15 2011-01-12 日立プラズマディスプレイ株式会社 駆動回路
KR100627388B1 (ko) * 2004-09-01 2006-09-21 삼성에스디아이 주식회사 플라즈마 표시 장치와 그 구동 방법
JP4520826B2 (ja) * 2004-11-09 2010-08-11 日立プラズマディスプレイ株式会社 表示装置及び表示方法
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WO2007004298A1 (ja) * 2005-07-06 2007-01-11 Fujitsu Hitachi Plasma Display Limited プラズマディスプレイの駆動方法及び装置
KR20080034923A (ko) * 2005-08-23 2008-04-22 마츠시타 덴끼 산교 가부시키가이샤 플라즈마 디스플레이 패널 구동 회로 및 플라즈마디스플레이 장치
JP2007065179A (ja) * 2005-08-30 2007-03-15 Fujitsu Hitachi Plasma Display Ltd プラズマディスプレイ装置
KR100704454B1 (ko) 2006-01-05 2007-04-06 엘지전자 주식회사 선택적 소거 방식의 플라즈마 디스플레이 패널의 구동 방법
JPWO2007094293A1 (ja) 2006-02-14 2009-07-09 パナソニック株式会社 プラズマディスプレイパネルの駆動方法およびプラズマディスプレイ装置
JP2009069561A (ja) * 2007-09-14 2009-04-02 Panasonic Corp プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法
US20110001745A1 (en) * 2008-02-06 2011-01-06 Panasonic Corporation Capacitive load drive device, plasma display device with a capacitive load drive device, and drive method for a plasma display panel
CN101719346B (zh) * 2009-12-31 2012-09-19 四川虹欧显示器件有限公司 等离子显示器的x驱动电路

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2872618A1 (fr) * 2004-07-01 2006-01-06 Thomson Licensing Sa Procede de commande d'un dispositif d'affichage d'images
CN100369083C (zh) * 2004-10-10 2008-02-13 东南大学 槽型等离子体显示板行电极的驱动电路及其驱动方法
CN100369084C (zh) * 2004-10-14 2008-02-13 东南大学 槽型等离子体显示板的高电压扫描维持驱动电路及其驱动方法
EP1667096A1 (de) 2004-11-24 2006-06-07 Samsung SDI Co., Ltd. Plasmaanzeige und Verfahren zu ihrer Ansteuerung
US7619589B2 (en) 2004-11-24 2009-11-17 Samsung Sdi Co., Ltd. Plasma display and driving method thereof
EP1708161A2 (de) * 2005-03-30 2006-10-04 LG Electronics Inc. Plasmaanzeigevorrichtung und Verfahren zu ihrer Ansteuerung
EP1708161A3 (de) * 2005-03-30 2007-10-31 LG Electronics Inc. Plasmaanzeigevorrichtung und Verfahren zu ihrer Ansteuerung
EP1760685A2 (de) * 2005-09-06 2007-03-07 LG Electronics Inc. Plasmaanzeigevorrichtung
EP1760685A3 (de) * 2005-09-06 2008-06-11 LG Electronics Inc. Plasmaanzeigevorrichtung
EP1901266A3 (de) * 2006-09-15 2008-10-29 Samsung SDI Co., Ltd. Plasmaanzeigevorrichtung und Verfahren zu ihrer Ansteuerung

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KR20020059711A (ko) 2002-07-13
CN1388950A (zh) 2003-01-01
TW518540B (en) 2003-01-21
CN1264129C (zh) 2006-07-12
EP1331623A4 (de) 2009-09-16
JP2002162932A (ja) 2002-06-07
JP3390752B2 (ja) 2003-03-31
WO2002023518A1 (fr) 2002-03-21

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