EP1324307A2 - Circuit for the voltage supply of a liquid crystal display device - Google Patents

Abstract

A potential divider (1) comprises series resistors (R1-R5), with intervening voltage (V2-V5) tappings (22-25). One (25) of the voltage tappings (a slider in this case) has a fine adjustment (3) for the voltage level (V5) tapped off. <??>An Independent claim - is included for an iterative method of calibrating the circuit, which includes measurement, correction and storage of the adjustment.

Description

The invention relates to a circuit arrangement for the voltage supply of a liquid crystal display device, a liquid crystal display device including this circuit arrangement and a method for calibrating the circuit arrangement.

A liquid crystal display (LCD) device typically includes two glass plates fastened parallel to each other, between which a layer with liquid crystals is arranged. The two glass panes each support the liquid crystal layer facing side electrodes, which are subjected to different voltages can be used to determine the optical properties of the electrodes To change liquid crystals. These optical properties are essentially those that affect light transmission. For dot matrix liquid crystal display devices are the electrodes as punctiform surfaces (picture elements, pixel) formed on the one side of the liquid crystal layer line by line and on the other side are connected in columns. You will be using appropriate electrical Driven circuits that contain a row and column driver. Such Row and column drivers cyclically control the electrodes with different voltages different polarity. Several, for example, six different intermediate voltages are used needed. These intermediate voltages are usually determined by a generated corresponding voltage divider, its outputs with the row and column drivers are connected. The voltage divider typically contains a plurality of in series switched resistors, between which the different voltage levels are tapped become.

• Während einer "geraden" Halbperiode 101 wird die Spaltenspannung 104 auf dem Pegel V2 ("urselektiert") gehalten oder auf V6 ("selektiert") gesetzt. Für eingeschaltete (z. B. schwarze) Bildpunkte erzeugt der Zeilentreiber die Spannung V1, für ausgeschaltete (z. B. weiße) Bildpunkte V3, so dass an den entsprechenden Flüssigkristallen die Spannung V1 - V2 bzw. V3 - V2, oder V1 - V6 bzw. V3 - V6, liegt.
• Während einer "ungeraden" Halbperiode 102 gelten analoge Verhältnisse, mit dem Unterschied, dass die Spannungen an einer bei (V1 - V6)/2 befindlichen Symmetrieachse 105 zu spiegeln sind. An den entsprechenden Flüssigkristallen liegt dann die Spannung V6 - V5 bzw. V4 - V5, oder V6 - V1 bzw. V4 - V1.

The problem underlying the present invention is illustrated with reference to FIG. 1. Six voltage levels V1 to V6 are shown in a schematic diagram. The voltage level V1 is usually equal to the LCD operating voltage Vlcd, and V6 can be identical to ground. A voltage curve 103 of a row typical of commercial liquid crystal display devices and a voltage curve 104 of a column are shown schematically. A distinction is made between two half-periods 101, 102 in the cyclic activation of the electrodes:

• During an "even" half-period 101, column voltage 104 is held at level V2 ("initially selected") or set to V6 ("selected"). The line driver generates the voltage V1 for switched on (e.g. black) pixels, for switched off (e.g. white) pixels V3, so that the voltage V1 - V2 or V3 - V2, or V1 - V6 on the corresponding liquid crystals or V3 - V6.
• Analogous conditions apply during an "odd" half-period 102, with the difference that the voltages on an axis of symmetry 105 located at (V1-V6) / 2 are to be mirrored. The voltage V6 - V5 or V4 - V5, or V6 - V1 or V4 - V1 is then applied to the corresponding liquid crystals.

So that the time average is the same for all pixels in a column, regardless of the number of pixels switched on or off in a column, the voltages occurring in a half-period should be symmetrical, ie the following should apply: V1 - V2 = V2 - V3; V4 - V5 = V5 - V6. In addition, the voltage levels should ideally be equidistant in the following sense: V1 - V2 = V2 - V3 = V4 - V5 = V5 - V6 = Vd, where Vd is the constant differential voltage (equidistance). If even one of the six voltage levels - for example due to production fluctuations etc. - deviates from the ideal value and violates the equidistance conditions (1) or (2), asymmetries result, which provide different contributions from pixels that are switched on and off. This leads to undesirable image distortions, which are easily perceived by the eye and reduce the image quality. This type of distortion is called "crosstalk" because it depends on the mutual interaction of pixel contents.

Liquid crystal display devices are particularly sensitive to this type of crosstalk with grayscale display or color display. With these, the grayscale lies on the steep flank of the characteristic curve (VT curve) of the liquid crystal. There are already deviations here of a few millivolts from the equidistance conditions (1) or (2) recognizable by the eye and are perceived as disturbing.

For a complete correction of all errors that cause crosstalk by means of calibration a circuit would be required which allows all voltage levels to be set independently compared to a reference voltage, for example. Such However, switching would be extremely complex and would take up a large area and consume more electrical power. It would be for practical applications therefore unsuitable.

JP-A-10-062743 discloses a circuit for a liquid crystal display device, with which the crosstalk is to be eliminated. The circuit is designed that two voltage levels are always changed at the same time. This is done using achieved two embodiments. In a first embodiment, two resistors changed from a plurality of resistors connected in series. To do this is an elevated Hardware effort and / or greater accuracy of the resistor chain taps required. In a second embodiment, a resistor is connected from two in parallel Resistance chains changed. This draws an increased current draw and / or an increased one Space requirement after itself.

It is therefore an object of the invention to provide a circuit arrangement for the voltage supply a liquid crystal display device or a liquid crystal display device create what reduces the crosstalk to an acceptable level and at the same time simple is constructed, saves space and electricity. Another object of the invention is a method specify for calibration of such a circuit arrangement. These tasks will be solved by the circuit arrangement, the liquid crystal display device and the calibration method, as defined in the independent claims. Advantageous embodiments are specified in the dependent claims.

The circuit arrangement according to the invention for the voltage supply of the row and column drivers a liquid crystal display device includes a voltage divider with a A large number of resistors connected in series and arranged between the resistors Voltage taps for tapping different voltage levels. A single the voltage taps is with means for fine adjustment of the voltage level tapped there fitted.

The liquid crystal display device according to the invention includes a liquid crystal layer, Row and column drivers and a circuit arrangement for the voltage supply of the Row and column drivers. The circuit arrangement is an inventive, above described circuit arrangement.

(a) Auswahl einer Anfangs-Feineinstellung;

(b) Messung des Wertes eines die Gesamtheit der Spannungspegel charakterisierenden Qualitätsparameters;

(c) Feststellung, ob der gemessene Qualitätsparameterwert in einem vorgegebenen Qualitätsintervall liegt;

(d) falls die Feststellung in Schritt (c) negativ ist: rekursive Bestimmung einer neuen Feineinstellung und Wiederholung der Schritte (b) und (c);

(e) falls die Feststellung in Schritt (c) positiv ist: Speichern der aktuellen Feineinstellung.

The method according to the invention for calibrating the circuit arrangement according to the invention includes the following steps:

(a) selection of an initial fine adjustment;

(b) measuring the value of a quality parameter characterizing the entirety of the voltage levels;

(c) determining whether the measured quality parameter value is within a predetermined quality interval;

(d) if the determination in step (c) is negative: recursively determining a new fine adjustment and repeating steps (b) and (c);

(e) if the determination in step (c) is positive: save the current fine adjustment.

The calibration is carried out once, individually for each copy of the circuit arrangement.

The invention is based on a thorough analysis of the accuracy of the voltage levels and of the various influences and parameters that influence this accuracy. As result This analysis can state that both systematic and statistical Errors affect the accuracy of the voltage levels. As an example of a statistical The statistical fluctuations of the contact resistance in are impaired here called the resistance chain, which directly relates to those tapped from the resistance chain Affect voltage level.

On the basis of these findings, attempts were made to specify an upper limit for the differences in the mean voltage values of black or white pixels, which result from inaccuracies in the voltage level, in accordance with the laws of error calculation. The result is the so-called D formula: D = V 1-2 V 2+ V 3 V 4 + 2 V 5 V 6 2 ,

The quantity D can be understood as a "quality parameter" characterizing the quality of the total of the voltage levels. According to the invention, the crosstalk is now reduced in that one of the voltage levels V2, V3, V4 or V5 is varied or finely adjusted by the absolute amount | D | to minimize. In other words: one of the voltage levels is varied until the measured quality parameter value D lies in a predetermined quality interval: | D | <D _Q. Analog multiplexers are preferably used as means for fine adjustment of the one voltage level, which only consist of a series of N-channel MOS switches and are therefore particularly simple and compact. The resulting resistance of the resistor chain is not changed by such a variation in a voltage level. The voltage level V5 or V2 is preferably varied; note that the D formula (3) is (anti-) symmetrical with respect to voltages V2, V5. A variation of V2 or V5 has the greatest effect on the quality parameter D because these voltages are multiplied by a factor of 2 in the D formula (3); in addition, the variation of V2 or V5 also has practical advantages in terms of the design of the circuit.

These and other aspects of the invention are described with reference to those described below Embodiments illuminates.

Figur 1

zeigt in einem schematischen Diagramm sechs Spannungspegel V1 bis V6 und eine für handelsübliche Flüssigkristallanzeigevorrichtungen typische Spannungsform einer Spalte.

Figur 2

zeigt schematisch ein Schaltbild eines Teils der erfindungsgemäßen Schaltungsanordnung.

Figur 3

zeigt eine schematische Draufsicht auf einen Layout-Teil der erfindungsgemäßen Schaltungsanordnung.

Figur 4

zeigt ein Flussdiagramm des erfindungsgemäßen Kalibrierverfahrens.

The invention is described in detail below with reference to drawings.

Figure 1

shows in a schematic diagram six voltage levels V1 to V6 and a typical voltage waveform of a column for commercial liquid crystal display devices.

Figure 2

shows schematically a circuit diagram of part of the circuit arrangement according to the invention.

Figure 3

shows a schematic plan view of a layout part of the circuit arrangement according to the invention.

Figure 4

shows a flow diagram of the calibration method according to the invention.

A schematic circuit diagram of part of the circuit arrangement according to the invention, namely of the voltage divider 1 is shown in Figure 2. The voltage divider 1 includes a chain of five resistors R1-R5 connected in series. At a first end 11 of the Resistor chain, a voltage V1 is applied, a voltage at a second end 12 V6, with the second end preferably grounded (i.e. grounded) to Vnd = 0) and V1 is Vlcd, the operating voltage of the honeycomb display device. Voltage taps 22-25 for tapping are differently secured between the resistors R1-R5 Voltage level V2-V5 arranged. So a voltage level of V2 <V1 is applied tapped a voltage tap 22 between the resistors R1 and R2 Voltage level V3 <V2 at a voltage tap 23 between the resistors R2 and R3, etc. A single voltage tap 25 of the voltage taps 22-25 is designed such that the voltage level tapped there, in the present example V5, is finely adjustable.

Means 3 for fine adjustment of the one voltage level V5 can, for example, as a plurality of Tap contacts can be formed on a resistive track. Figure 3 shows in a exemplary embodiment, eight equidistant tap contacts 31-38 on a resistive Lane 45. The location of this group 3 on eight tap contacts 31-38 the web 45 can be different, depending on which voltage level system is selected becomes. A voltage level system is characterized by the ratio V5 / V1, which can typically assume the values 1/4, 1/5, ..., 1/11. On the web 45 could also multiple groups of tap contacts can be provided, each group one Voltage level system is assigned so that by choosing a particular group certain voltage level system can be selected.

All elements of the circuit arrangement are preferably accommodated on a common substrate, so that it is an integrated circuit. The resistors R1-R5 can z. B. by means of strip-shaped implantations 41-45 of semiconductor material of a first conductivity type, for example p ⁺ , in a semiconductor material of a second conductivity type, for example n; other examples are n ⁺ or n ^- in p ^- or poly-Si. It should be noted that a resistor does not necessarily correspond to exactly one stripe; rather, resistance in the sense used here is defined by the two taps that limit it. The variable resistor R5 in the example of FIG. 3 is limited by one of the tap contacts 31-38 on the one hand and the ground contact 12 on the other hand, so that it comprises part of the strip 45 and the entire strip 46.

In the following, an example is used to explain how the number and the distance of the tap contacts 31-38 can be selected. Consider a liquid crystal display device whose liquid crystal has a transition region with a width of 200 mV. For the sake of simplicity, it is assumed that the characteristic curve is linear in the entire transition area, ie its flank has a constant slope of -1 / (200 mV). It is known that differences in light transmission between two pixels of more than approx. 2% are perceived by the eye. Consequently, the real light transmittances of two pixels with the same nominal light transmittance should differ by at most 2%, which means a voltage difference of at most 4 mV (2% of 200 mV) or a quality interval (-D _Q , + D _Q ) with D _Q = 4 corresponds to mV. In order to ensure that the quality parameter D comes to lie within the quality interval (-D _Q , + D _Q ), the distances between the tap contacts 31-38 must be selected such that the voltage difference between two tap contacts? V = 2D _Q = 8 mV is present. With eight tap contacts 31-38, the quality parameter D can thus be varied within a range of 7? V = 56 mV, which is sufficient for most applications. In this exemplary embodiment with eight tap contacts 31-38, 3 bits are necessary in order to store the optimal fine adjustment. Of course, other configurations are possible, for example a 4-bit calibration with 16 tap contacts, between each of which there is a voltage difference? V = 4 mV.

As shown symbolically in the right half of FIG. 2, each tap contact 31-38 is connected to an input 51-58 of a static analog multiplexer 5, which, for. B. consists of a series of N-channel MOS switches and is therefore particularly simple. The multiplexer 5 is preferably by a one or more times programmable read-only memory (such as one-time programmable read-only memory, OTP; programmable read-only memory, PROM; erasable programmable read-only memory, EPROM; electrically erasable programmable read -only memory, E ² PROM; etc.) checked. This has the task of storing an optimal fine adjustment of the voltage level V5 once found, that is to say to connect the respectively optimal tap contact to the output 25 'of the voltage tap 25 for V5.

FIG. 4 shows a flow diagram of the calibration method according to the invention. At the beginning a suitable voltage level system 91 (cf. explanations for FIG. 3) and a suitable one Operating voltage V1, 92, e.g. V1 = 9 V, selected. A calibration parameter P becomes set to an initial value P (0) 93. The calibration parameter P characterizes the current one Fine adjustment of the variable voltage level V5. In the exemplary embodiment in FIG. 3 P can therefore be a number between 0 and 7, which indicates which of the eight tap contacts 31-38 is currently connected to the output 25 'of the voltage tap 25 for V5, this Number is preferably stored in binary or hexadecimal notation. As an initial value P (0) is preferably the one in which, ideally, the equidistance condition (2) would be fulfilled. A run variable (only used internally for the following loop 95-98) n (n = 0, 1, 2, ...) is first set to zero 94.

An iteration loop 95-98 is then run through one or more times, in which the calibration parameter P is recursively optimized on the basis of the quality parameter D. For this purpose, the current value D (n) of the quality parameter D is first determined 95 by measuring the current voltages V1-V6 and inserting them into the D formula (3). The current value D (n) is then examined 96 whether it is in a predetermined quality interval (-D _Q , + D _Q ), bpsw. D _Q = 2 mV can be selected. If this is the case, the current calibration parameter P (n) is written 99 in a calibration register, for example in an OTP ROM. If D (n) is not in the quality interval, a new calibration parameter P (n + 1) is recursively calculated 97 from the old calibration parameter P (n). B. according to the formula P ( n +1): = P ( n ) - rnd [ D ( n ) · V 1 nom / (Δ V · V 1)] happen, where? V is a voltage step size at a nominal operating voltage V1nom, z. B.? V = 4 mV at V1nom = 9 V, and the operator rnd [X] rounds the operand X to the nearest whole number. The operand X in the square brackets in equation (4) essentially indicates the number of tap contacts by which the fine adjustment has to be changed in an iteration step. It is composed of the factors D (n) /? V and V1nom / V1, the latter factor being a correction that takes into account that the voltage step size? V is scaled with V1. After calculation 97 of the new calibration parameter P (n + 1), the run variable n is increased 98 by one, and the iteration loop 95-98 is run through again. This is repeated until the current quality parameter value D (n) lies in the specified quality interval (-D _Q , + D _Q ).

The calibration described above is done once for each circuit instance by the circuit manufacturer or the manufacturer of the liquid crystal display device. In the latter case, a special probe for contacting the Electrodes are used on the glass plates, or the different voltage levels V1-V6 could be switched to a certain output contact in succession. All Voltage measurements required for calibration should have the highest possible load resistance be measured so as not to falsify the measured values.

The circuit arrangement according to the invention and the calibration method according to the invention reduce the crosstalk of pixels to an acceptable level. These advantages come with display devices with grayscale display or color display devices especially to its advantage. The circuit arrangement is simple, space and energy saving.

Claims (14)

Circuit arrangement for the voltage supply of the row and column drivers Honeycomb crystal display device comprising a voltage divider (1) having a plurality of Series-connected resistors (R1-R5) and with between the resistors (R1-R5) arranged voltage taps (22-25) for tapping different voltage levels (V2-V5), a single one (25) of the voltage taps (22-25) with means (3) for Fine adjustment of the voltage level (V5) tapped there is equipped. Circuit arrangement according to claim 1, wherein the fine adjustment means (3) a plurality of Tap contacts (31-38) and means (5) for selecting a tap contact. Circuit arrangement according to claim 2, wherein the selection means (5) as an analog Multiplexer are formed, the inputs (51-58) with the tap contacts (31-38) are connected. Circuit arrangement according to claim 3, wherein the circuit arrangement once or contains multiple programmable read-only memories to control the multiplexer (5). Circuit arrangement according to one of the preceding claims, wherein the with the Fine adjustment means (3) equipped voltage tap (25) one of the two voltage taps (22, 25), which are the two ends (11, 12) of the voltage divider (1) closest. Circuit arrangement according to one of the preceding claims, wherein the Voltage divider (1) has exactly four voltage taps (22-25). Circuit arrangement according to one of the preceding claims, wherein all elements the circuit arrangement are housed on a common substrate. Circuit arrangement according to claim 7, wherein the resistors (R1-R5) are implemented by means of strip-shaped implants (41-46) of semiconductor material of a first conductivity type (p ⁺ ) in a semiconductor material of a second conductivity type (n). Honeycomb crystal display device including a liquid crystal layer, line and Column drivers and a circuit arrangement for the voltage supply of the row and Column driver, the circuit arrangement being a circuit arrangement according to one of the preceding claims. Method for calibrating a circuit arrangement according to one of claims 1-8, comprising the following steps: (a) selecting (93) an initial fine adjustment; (b) measurement (95) of the value (D (n)) of a quality parameter (D) characterizing the entirety of the voltage levels (V1-V6); (c) determining (96) whether the measured quality parameter value (D (n)) is within a predetermined quality interval (-D _Q , + D _Q ); (d) if the determination (96) in step (c) is negative: recursively determining (97) a new fine adjustment (P (n + 1)) and repeating steps (b) and (c); (e) if the determination (96) in step (c) is positive: storing (99) the current fine adjustment (P (n)). Method according to Claim 10, a first operating voltage V1 being applied to one end (11) of the voltage divider (1) and a second operating voltage V6 being applied to the other end (12) of the voltage divider (2), the voltage divider (1) having four voltage taps (22- 25) for tapping four voltage levels (V2, V3, V4, V5) and the quality parameter (D) in step (b) is defined by D = V 1-2 V 2+ V 3 V 4 + 2 V 5 V 6 2 , The method of claim 11, wherein the fine adjustment is voltage level V2 or V5 concerns. A method according to any of claims 10-12, wherein the quality interval (D _Q, + D _Q) is selected in step (c) such that for this quality interval (D _Q, + D _Q) lying quality parameter values (D ( n)) differentiate the real light transmittances of two pixels with the same nominal light transmittance by at most 2%. The method of any of claims 10-13, wherein storing (99) the current one Fine adjustment (P (n)) takes place in a one or more times programmable read-only memory.

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