EP1271440B1 - High-voltage regulator with external control - Google Patents

High-voltage regulator with external control Download PDF

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Publication number
EP1271440B1
EP1271440B1 EP01202429A EP01202429A EP1271440B1 EP 1271440 B1 EP1271440 B1 EP 1271440B1 EP 01202429 A EP01202429 A EP 01202429A EP 01202429 A EP01202429 A EP 01202429A EP 1271440 B1 EP1271440 B1 EP 1271440B1
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EP
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Prior art keywords
voltage
output
terminal
transistor
differential amplifier
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EP01202429A
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German (de)
French (fr)
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EP1271440A1 (en
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Arthur Descombes
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EM Microelectronic Marin SA
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EM Microelectronic Marin SA
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Priority to DE60115408T priority Critical patent/DE60115408T2/en
Priority to AT01202429T priority patent/ATE311644T1/en
Priority to EP01202429A priority patent/EP1271440B1/en
Publication of EP1271440A1 publication Critical patent/EP1271440A1/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the present invention generally relates to a regulator circuit high voltage for delivering at least a first regulated output voltage from a high input voltage, in particular of the order of a few tens of volts. More particularly, the present invention relates to such a high-voltage regulator in the form of an integrated circuit controlling an external device of regulation.
  • FIG. 1 shows a control circuit generally designated by the numerical reference 1 comprising an external regulation device 2, consisting of a JFET transistor, and a control circuit 10 of this external regulation device 2.
  • This regulator circuit 1 is designed to to deliver a regulated output voltage V REG allowing the supply of an associated device, not shown.
  • This regulated output voltage V REG is derived from a high level input voltage V HV of the order of a few tens of volts, typically ranging between 15 and 30 volts.
  • Such a voltage regulator circuit is notably used in devices smoke detection, as described for example in the document EP-A1-0 759 602, for deriving a low level regulated voltage (e.g. volts) necessary inter alia to power a microprocessor of the device of smoke detection.
  • a low level regulated voltage e.g. volts
  • the line voltage supplying the smoke detection devices is for example of the order of 15 to 30 volts.
  • the regulator circuit 1 of FIG. 1 typically comprises a differential amplifier 4 whose input is connected to the output of a voltage divider circuit 5, formed in this example of two resistors 51, 52 connected in series, the other input of the differential amplifier 4 being connected to a reference cell 6 delivering a reference voltage V REF .
  • This reference cell 6 is typically a cell delivering a reference voltage stable in temperature called "bandgap".
  • the output of the differential amplifier 4 is directly connected to the gate of the transistor JFET forming the regulation device 2.
  • the arrangement illustrated in FIG. 1 thus ensures that the voltage present at the output node of the voltage divider circuit 5, namely the connection node between the resistors 51 and 52, is substantially equal to the reference voltage V REF .
  • values R1, R2 of the resistors 51 and 52 being chosen so that the regulated output voltage V REG of the regulator circuit 1 has a determined value, for example of the order of 5 volts.
  • This regulated voltage V REG feeds in particular the differential amplifier 4 and the reference cell 6 of the regulator 1 as illustrated in FIG.
  • a disadvantage of the regulator circuit of FIG. 1 resides notably in the choice of the external regulation device 2 and the costs of this regulation device.
  • the JFET transistor must be chosen to withstand relatively high drain-source voltages (in the example of the order of 25 volts), this drain-source voltage being in particular a function of the high input voltage V HV and the regulated voltage V REG that it is desired to deliver at the output of the regulator.
  • the cost of this JFET transistor increases with the maximum drain-source voltage at which this regulating element can be subjected. It is therefore desirable, particularly with a view to reducing costs, to propose an alternative solution to the solution presented in FIG.
  • a serious disadvantage of the solution of Figure 1 lies in the fact that its application is limited by the high input voltage likely to be applied to the regulator input as well as through the regulated output voltage that one wants to deliver.
  • the limits imposed by the technology would make use of the regulator circuit of Figure 1 too expensive or even impossible, especially when you want to make this regulator in a technology below the micron.
  • This regulator circuit includes a voltage divider circuit outputting a divided voltage, a cell of reference outputting a determined reference voltage, an amplifier differential receiving as input the divided voltage and the reference voltage and a VDMOS transistor whose gate is connected to the output of the amplifier.
  • the present invention therefore aims to propose a solution allowing to overcome the aforementioned drawbacks, and in particular to propose a solution allowing the use of a less expensive external control device as well as a solution that can be used with higher high input voltages.
  • Another object of the present invention is to propose a solution that can be made and manufactured in less than one micron CMOS technology, particularly in 0.5 ⁇ m CMOS technology.
  • the present invention thus relates to a high-voltage regulator whose features are set forth in claim 1.
  • the regulating device external is advantageously controlled via a MOSFET transistor high-specific voltage likely to see at its terminals a drain-source voltage of the order of a few tens of volts.
  • a MOSFET transistor high-specific voltage likely to see at its terminals a drain-source voltage of the order of a few tens of volts.
  • the present invention requires the use of additional elements, additional costs caused by the addition of these elements are nevertheless less than the economy that can be expected from the costs of external regulation.
  • the high-voltage MOSFET transistors used in the of the present invention are perfectly compatible with the technology Standard CMOS and do not require or few masks and / or implantation additional for their manufacture.
  • the circuit regulator is arranged to deliver a first regulated output voltage, so-called intermediate and a second regulated output voltage certain components of the regulator circuit, such as the differential amplifier and the reference cell of the regulator, as well as the possible power supply of the electronics associated device, such as, for example, the microprocessor responsible for the operations of a smoke detection device.
  • the voltage regulated intermediate is used for example in the context of the application to a smoke detection device, to provide the current required for the generation of the infrared pulse by the infrared diode which these are typically equipped with detection devices.
  • this preferred embodiment of the present invention allows the displacement of the infrared diode of the input on the output of the regulator circuit where the intermediate regulated voltage is delivered.
  • Voltage necessary for the generation of the infrared pulse in a detection device of smoke is typically of the order of ten volts, that is to say much higher at the voltage levels used to power the device electronics.
  • this intermediate regulated voltage is of one level. lower than the input voltage of the regulator circuit, thus enabling a reduction in losses during the generation of the infrared pulse, and yet greater than the supply voltage of the electronics to ensure a power level adequate for the generation of this infrared pulse.
  • the circuit regulator is arranged so that the differential amplifier controlling the device external regulation has a hysteresis, this ensuring in particular a stability increased operation of the regulator.
  • FIG. 2 shows a general block diagram of a high-voltage regulator circuit for delivering a regulated output voltage designated V REG1 .
  • this regulator circuit is denoted globally by the reference numeral 1 and comprises in particular an external regulation device 2, constituted in this example by a single n-channel JFET transistor, as well as an integrated circuit. command generally designated by the reference numeral 10, for example realized in the form of an ASIC.
  • the high input voltage V HV may vary in this example from about 15 to about 50 volts.
  • the regulated output voltage V REG1 is in this example of the order of ten volts.
  • the external regulation device 2 comprises an input terminal 21 (the drain of the JFET transistor) connected to the high input voltage V HV , an output terminal 22 (the source of the JFET transistor) on which the voltage is supplied. regulated output V REG1 , and a control terminal 23 (the gate of the JFET transistor) through which the conduction state of the external regulating device 2 is controlled.
  • the control terminals 23 and output terminals 22 are respectively connected to terminals 11 and 12 of the integrated circuit 10.
  • a terminal 13 of the integrated circuit 10 is connected to the ground V SS of the circuit.
  • Figure 8 which will be discussed in detail later, for example has another external control device comprising an arrangement of two complementary bipolar transistors and a resistor.
  • the integrated circuit 10 essentially comprises a differential amplifier 4, a voltage divider circuit 5, a reference cell 6, and a high-voltage control element 3.
  • the voltage divider circuit 5 is formed in this example of two resistors 51, 52 connected in series between the terminal 12 of the integrated circuit 10, namely the output terminal of the external regulating device 2, and the ground V SS of the circuit. It will of course be understood that other voltage divider circuits could be used by those skilled in the art.
  • the regulator circuit 1 furthermore typically comprises an external capacitive element C EXT1 forming a buffer connected to the output terminal 22.
  • connection node between the two resistors 51, 52 is connected to a first input terminal of the differential amplifier 4. It will be easily understood that the voltage applied to this first input terminal of the differential amplifier 4 as well as the regulated voltage V REG1 are proportional in a ratio determined by the values R1 and R2 of the resistors 51, 52.
  • the second input terminal of the differential amplifier 4 is connected to the reference cell 6 producing a voltage of designated reference REF , this reference cell 6 is typically a cell of the "bandgap" type delivering a reference voltage for example of the order of about 1.2 volts.
  • the output of the differential amplifier 4 is applied to the gate of a High-voltage MOSFET transistor 3 of a specific type.
  • This MOSFET transistor high-voltage 3 here of the n-channel type, is already known to those skilled in the art.
  • the particularity of this high-voltage transistor lies in particular in the structure specificity of the gate oxide which has a greater thickness on the side drain that on the source side as well as in the presence of a buffer zone on the drain side consisting of an n-type well (or p for a high-voltage MOSFET transistor p-channel).
  • FIGS. 3a and 3b respectively show the diagrams of a transistor HIGH VOLTAGE N-CHANNEL MOSFET, OR HVNMOS, AND A P-CHANNEL MOSFET high-voltage, or HVPMOS.
  • the HVNMOS transistors notably present the advantage of a high breakdown voltage typically greater than 30 volts.
  • a another advantage of this type of transistor lies in the fact that their manufacture is perfectly compatible with standard CMOS technology.
  • the high-voltage MOSFET transistor 3 is connected on the drain side to the control terminal 23 of the external regulation device 2 via the terminal 11, and on the source side to the ground V SS via the terminal 13.
  • a resistor 30 of value R0 is connected between the terminals 11 and 12 of the integrated circuit 10, namely between the control terminals 23 and output 22 of the external regulating device 2. It will be noted that this resistor 30 is only necessary in the case where the external regulating device 2 consists of a JFET transistor as illustrated. In the event that the external regulating device were constructed as an arrangement of bipolar transistors as illustrated in FIG. 8, this resistor 30 is no longer necessary.
  • the differential amplifier 4 as well as the reference cell 6 are powered by a supply voltage V DD , for example of the order of 3 volts.
  • V DD a supply voltage
  • this supply voltage V DD is advantageously also delivered by the regulator circuit 1 itself.
  • the only elements that must support high voltages at their terminals are the transistor 3 and the resistors 30, 51 and 52, these the latter being advantageously integrated in the form of diffusion regions of type n or "n-well" resistors.
  • the differential amplifier 4 is itself a conventional differential amplifier only supporting low voltages at its terminals.
  • FIG. 4 shows a regulator circuit according to the invention in which the integrated circuit 10 further comprises means, indicated generally by the reference numeral 100, for delivering a second regulated output voltage V REG2 advantageously for supplying various electronic components of the control circuit, such as in particular the differential amplifier 4 and the reference cell 6, or other electronic components associated with the regulator.
  • V REG2 is used as the supply voltage V DD for the differential amplifier 4 and the reference cell 6.
  • the means 100 preferably comprise, as illustrated, a second high-voltage n-channel MOSFET transistor designated by the numeral 101, a control element 102 constituted in this example of a p-MOS transistor, a differential amplifier 104 and a voltage divider circuit 105.
  • the high-voltage MOSFET 101 is analogous to transistor 3 and is connected by its drain terminal to the output terminal 22 of the external device of regulation 2, and, by its source terminal at the source terminal of the p-MOS transistor 102.
  • the gate of the high-voltage MOSFET transistor 101 is connected to the divider circuit of voltage 5 at the connection node between resistors 53 and 54.
  • These resistors 53 and 54 in series replace the resistor 51 of Figure 2 and the sum of the R11 values and R12 of these resistors 53 and 54 is equivalent to the value R1 of the resistor 51 of FIG. 2.
  • the division ratio of the voltage divider circuit 5 thus remains unchanged with respect to the voltage applied to the amplifier input differential 4.
  • the ratio of the resistors R11, R12 and R2 is chosen so that the voltage applied to the gate of the high-voltage transistor 101 causes a determined potential drop between drain and source of this transistor 101, the voltage present on the source of this transistor 101 being then representative of the output voltage V REG1 minus the determined potential drop across the terminals of the transistor 101. It will therefore be understood that the essential role of the high-voltage transistor 101 is to lower the output voltage V REG1 to a level tolerable for downstream circuits.
  • the voltage divider circuit 105 is constituted, between the drain terminal of the p-MOS transistor 102 and the ground V SS , of two resistors 151 and 152, the division ratio of this divider circuit 105. being determined by the values R3 and R4 of these resistances.
  • the second regulated output voltage V REG2 is delivered to a terminal 14 of the integrated circuit 10 on the drain terminal of the p-MOS transistor 102 across the voltage divider circuit 105, a second capacitive capacitor C EXT2 element typically being connected to the this marker 14.
  • connection node between the two resistors 151 and 152 is connected to a first input terminal of the differential amplifier 104.
  • the voltage applied to this first input terminal of the differential amplifier 104 as well as the second output voltage Regulated V REG2 are proportional in a ratio determined by the values R3 and R4 of the resistors 151, 152.
  • the second input terminal of the differential amplifier 104 is connected, analogously to the differential amplifier 4, to the control cell. reference 6 producing the reference voltage V REF .
  • the output of the differential amplifier 104 is applied to the gate of the p-MOS transistor 102. It will again be understood that the arrangement of the differential amplifier 104 illustrated in FIG. 4 imposes that the voltage present at the output node of the circuit voltage divider 105, namely the connection node between the resistors 151 and 152, is substantially equal to the reference voltage V REF , the values R3 and R4 of the resistors being chosen so that the second regulated output voltage V REG2 of the Regulator circuit 1 has a determined value, for example of the order of 3 volts.
  • This regulated voltage V REG2 supplies, in particular, the differential amplifier 4 and the reference cell 6 of the regulator 1 as already mentioned.
  • the supply of the differential amplifier 104 is provided, on the one hand, by the mass V SS and, on the other hand, by the voltage present at the source terminal of the transistor p
  • a capacitive element 106 is disposed on the output of the differential amplifier 104 between the gate and drain terminals of the p-MOS transistor 102. This capacitive element 106 provides a stability of the regulated output voltage V REG2 .
  • the regulator circuit allows the displacement of the infrared diode of the detector, necessary for the generation of the infrared pulse, from the input to the output of the circuit.
  • regulator on the terminal 12 of the circuit where the regulated output voltage V REG1 is delivered.
  • Figure 4 schematically shows the arrangement of this infrared diode indicated by the reference numeral 200 and control means 210 connected in series with the diode 200, here a bipolar transistor, for triggering the infrared pulse.
  • the present invention makes it possible thus a reduction of the losses during the generation of the infrared pulse, especially because the regulated voltage used for this generation is less than the input voltage.
  • the infrared diode and its control means are placed at the high voltage input 21, the regulated output voltage is not sufficient to supply this diode infrared and allow the generation of the required pulse.
  • the differential amplifier 4 used in the circuit controller of Figure 2 or 4 is a conventional type differential amplifier an exemplary embodiment of which is illustrated in Figure 6.
  • the differential amplifier 4 illustrated in FIG. 6 comprises a differential pair of transistors M1, M2 (in the occurrence of two identical p-MOS transistors), the gates of which form the differential amplifier inputs 4.
  • Each transistor M1, M2 is connected in series in the reference branch of a current mirror 41, 42, each mirror of current 41, 42 conventionally comprising two n-MOS transistors M11, M12 and M21, M22 connected grid grid grid.
  • M12 and M22 transistors of the branches of current mirrors 41 and 42 are themselves connected respectively to the reference and exit branches of another designated current mirror globally by the reference numeral 43 and comprising two p-MOS transistors M13 and M23.
  • the output of the differential amplifier 4 is formed of the node of connection between the p-MOS transistors M23 and n-MOS M22 of the output branch of the current mirror 43.
  • a p-MOS transistor M3 connected between the power supply terminal V DD and the connection node of the p-MOS transistors M1, M2 of the input differential pair ensures adequate polarization of the transistors, a determined bias voltage V BIAS being applied to the gate of this p-MOS transistor M3.
  • the differential amplifier 4 further comprises an additional output stage comprising p-MOS transistors M5 and n-MOS M6 forming an inverter arrangement for delivering the output signal designated OUT and its inverse OUT_B, a p-MOS transistor M4 controlled by the bias voltage V BIAS being connected in series with these transistors M5, M6 to ensure proper polarization of the latter.
  • the differential amplifier 4 forms a comparator outputting logic level signals.
  • the differential amplifier 104 used in the regulator circuit of FIG. must be designed to tolerate higher voltages at its terminals and may be realized on the basis of a diagram similar to the differential amplifier 4 of FIG. by employing cascode montages well known to those skilled in the art, that is to say assemblies of two or more transistors in series.
  • Figure 7 shows a example of realization of such a differential amplifier using cascode editing.
  • the transistors Q1, Q2, Q11, Q12, Q21, Q22, Q13, Q23 and Q3 essentially fulfill the same roles as the transistors M1, M2, M11, M12, M21, M22, M13, M23 and M3 of the circuit of FIG. Cascode assemblies are used in order to limit the voltages likely to occur across the transistors of this differential amplifier 104, in particular the transistors connected between the supply voltages V P and Vss. It will be noted that the voltage V P is taken from the source of the high voltage MOSFET transistor 101.
  • transistors Q12 and Q22 are each connected in series respectively with a second n-MOS transistor Q51 arranged between the transistors Q12 and Q13 and a second n-MOS transistor Q52 disposed between transistors Q22 and Q23.
  • transistors Q3 and Q23 are each connected in series with a second p-MOS transistor Q41 disposed between transistor Q3 and the connection node of the differential pair and a second p-MOS transistor Q42 disposed between transistors Q22 and Q23.
  • the output terminal of the differential amplifier 104 is formed of the connection node between the transistors Q42 and Q52.
  • n-MOS transistor Q50 conventionally forms a current mirror with transistors Q51 and Q52.
  • a p-MOS transistor additional Q40 form conventionally a current mirror with the transistors Q41 and Q42.
  • Each of these transistors Q40 and Q50 is connected in series with a cascode arrangement of two transistors respectively p-MOS Q43, Q44 and n-MOS Q53, Q54.
  • the n-MOS transistor Q54 still forms a current mirror with a another n-MOS transistor Q55 connected in series in the branch comprising the p-MOS transistors Q40, Q43 and Q44.
  • the polarization of the transistors is fixed by a bias current I BIAS applied in the current path of a p-MOS transistor Q31 connected in current mirror with the transistor Q3, this polarization current I BIAS being itself mirrored in the branch comprising the n-MOS transistors Q50, Q53 and Q54 by means of a p-MOS transistor Q32.
  • the assembly illustrated in FIG. 7 assures that none of the transistors of this differential amplifier 104 does not see at its terminals a too high voltage susceptible to cause a breakdown of this transistor.
  • the configuration of FIG. 7 is given by way of example only, the person skilled in the art can make many modifications to the diagram presented, or even choose a alternative configuration.
  • the differential amplifier 104 must basically meet higher constraints than the differential amplifier 4 because it is powered by a higher voltage, in this example typically of the order of 4 to 7 volts.
  • FIG. 5 shows another advantageous variant of the regulator circuit according to the invention substantially similar to the variant of FIG. 4.
  • the differential amplifier 4 of the regulator circuit 1 is arranged to present a hysteresis.
  • This hysteresis has the advantage of making the stability of the regulator less critical and consequently a periodic variation of the first regulated voltage V REG1 .
  • the regulator of FIG. 5 thus forms a "bang-bang" type regulator delivering a regulated voltage varying between two determined voltage levels.
  • the differential amplifier 4 forms in this example a comparator, that is to say it provides output signals OUT and OUT_B logic levels.
  • the hysteresis of the differential amplifier can be generated from various ways. One of them is illustrated schematically in Figure 5 and call to two transmission gates 7, 8 connected to the input on which is applied the output voltage of the voltage divider circuit 5, and an inverter 9 connected to the output of the differential amplifier 4.
  • the divider circuit 5 is furthermore slightly modified so that the resistor 54 is subdivided into two resistors 55 and 56 whose sum of the values R121 and R122 is equivalent to the value R12 of the resistor 54 of Figure 4.
  • the hysteresis is determined by the ratio of the values R11, R121, R122 and R2 of the resistors 53, 55, 56 and 52.
  • connection node between the resistors 55 and 56 is connected to the input of the first transmission gate 7 and the connection node between the resistors 56 and 52 is connected to the input of the second transmission gate 8.
  • the state of the transmission doors 7 and 8 is controlled according to the output of the amplifier differential 4, the transmission gates 7 and 8 being respectively passing and non-passing when the output signal (not inverted) of the differential amplifier 4 is at the high state, and, on the opposite, respectively non-passing and passing when the signal output of the differential amplifier 4 is low.
  • the exit inverted OUT_B of the differential amplifier 4 is connected to the inverting terminal of the door 7 and the non-inverting terminal of the door 8, this inverted output OUT_B being also applied, via the inverter 9, to the non-inverting terminal of the door 7 and the inverting terminal of the door 8.
  • the JFET transistor used as an external regulating device 2 in the embodiments described above could be replaced by another suitable device.
  • the JFET transistor can advantageously be replaced by the device illustrated in FIG. Figure 8 consists of an assembly conventionally named "pseudo-Darlington" comprising two complementary bipolar transistors, namely a transistor bipolar pnp type B1 and a bipolar transistor type npn B2.
  • Darlingtion assembly comprising two bipolar transistors of the same type could alternatively be used in place of the pseudo-Darlingtion montage of the figure 8.
  • the emitter and the collector of the transistor B1 respectively form the input 21 on which the high input voltage V HV is applied and the output 22 on which the regulated output voltage V is delivered.
  • REG1 the base of this transistor B1 being connected to the collector of the bipolar transistor B2, the emitter of this transistor B2 being connected to the collector of the transistor B1.
  • the base of the transistor B2 forms the control terminal 23 of the external control device.
  • this external regulation device 2 further comprises a resistor 25 connected in parallel between the input terminal 21 and the control terminal 23.
  • the device shown in Figure 8 includes a higher number components, the costs of this device are nevertheless lower than the costs associated with to the use of a JFET transistor, thus constituting an advantage in the optical a reduction in the manufacturing costs of the regulator circuit.
  • the regulator circuit according to the invention is in no way limited by the type of external control device used in the modes aforementioned embodiments, namely a JFET transistor.
  • other suitable arrangements such as the arrangement of FIG. 8, may be used by the skilled person.

Abstract

The regulator comprises an external JFET transistor (2) which is governed by a control unit (10) to produce a regulated voltage (Vreg1) from a supply (Vhv). The control unit consists of a differential amplifier (4) which is supplied from a voltage divider (5) connected to the regulated voltage and a reference cell (6) and controls the external regulator through a MOSFET transistor (3)

Description

La présente invention concerne de manière générale un circuit régulateur haute-tension permettant de délivrer au moins une première tension de sortie régulée à partir d'une tension d'entrée haute, notamment de l'ordre de quelques dizaines de volts. Plus particulièrement, la présente invention concerne un tel régulateur haute-tension sous la forme d'un circuit intégré commandant un dispositif externe de régulation.The present invention generally relates to a regulator circuit high voltage for delivering at least a first regulated output voltage from a high input voltage, in particular of the order of a few tens of volts. More particularly, the present invention relates to such a high-voltage regulator in the form of an integrated circuit controlling an external device of regulation.

Diverses applications nécessitent la fourniture d'une tension régulée déterminée à partir d'une tension d'entrée haute, cette tension régulée étant notamment utilisée pour alimenter l'électronique d'un dispositif associé. La figure 1 montre un circuit régulateur désigné globalement par la référence numérique 1 comprenant un dispositif externe de régulation 2, constitué d'un transistor JFET, et un circuit de commande 10 de ce dispositif externe de régulation 2. Ce circuit régulateur 1 est conçu pour délivrer une tension de sortie régulée VREG permettant l'alimentation d'un dispositif associé, non représenté. Cette tension de sortie régulée VREG est dérivée d'une tension d'entrée VHV de niveau haut de l'ordre de quelques dizaines de volts pouvant typiquement varier entre 15 et 30 volts.Various applications require the provision of a regulated voltage determined from a high input voltage, this regulated voltage being used in particular to power the electronics of an associated device. FIG. 1 shows a control circuit generally designated by the numerical reference 1 comprising an external regulation device 2, consisting of a JFET transistor, and a control circuit 10 of this external regulation device 2. This regulator circuit 1 is designed to to deliver a regulated output voltage V REG allowing the supply of an associated device, not shown. This regulated output voltage V REG is derived from a high level input voltage V HV of the order of a few tens of volts, typically ranging between 15 and 30 volts.

Un tel circuit régulateur de tension est notamment utilisé dans des dispositifs de détection de fumée, comme décrit par exemple dans le document EP-A1-0 759 602, pour dériver une tension régulée de niveau bas (par exemple 5 volts) nécessaire entre autres à l'alimentation d'un microprocesseur du dispositif de détection de fumée. Dans le cadre d'une telle application, la tension de ligne alimentant les dispositifs de détection de fumée est par exemple de l'ordre de 15 à 30 volts.Such a voltage regulator circuit is notably used in devices smoke detection, as described for example in the document EP-A1-0 759 602, for deriving a low level regulated voltage (e.g. volts) necessary inter alia to power a microprocessor of the device of smoke detection. In the context of such an application, the line voltage supplying the smoke detection devices is for example of the order of 15 to 30 volts.

Le circuit régulateur 1 de la figure 1 comprend typiquement un amplificateur différentiel 4 dont une entrée est connectée à la sortie d'une circuit diviseur de tension 5, formé dans cet exemple de deux résistances 51, 52 branchées en série, l'autre entrée de l'amplificateur différentiel 4 étant connectée à une cellule de référence 6 délivrant une tension de référence VREF. Cette cellule de référence 6 est typiquement une cellule délivrant une tension de référence stable en température dite de « bandgap ». La sortie de l'amplificateur différentiel 4 est directement reliée à la grille du transistor JFET formant le dispositif de régulation 2.The regulator circuit 1 of FIG. 1 typically comprises a differential amplifier 4 whose input is connected to the output of a voltage divider circuit 5, formed in this example of two resistors 51, 52 connected in series, the other input of the differential amplifier 4 being connected to a reference cell 6 delivering a reference voltage V REF . This reference cell 6 is typically a cell delivering a reference voltage stable in temperature called "bandgap". The output of the differential amplifier 4 is directly connected to the gate of the transistor JFET forming the regulation device 2.

L'agencement illustré dans la figure 1 assure ainsi que la tension présente au noeud de sortie du circuit diviseur de tension 5, à savoir le noeud de connexion entre les résistances 51 et 52, soit sensiblement égale à la tension de référence VREF, les valeurs R1, R2 des résistances 51 et 52 étant choisies de sorte que la tension de sortie régulée VREG du circuit régulateur 1 ait une valeur déterminée, par exemple de l'ordre de 5 volts. Cette tension régulée VREG alimente notamment l'amplificateur différentiel 4 et la cellule de référence 6 du régulateur 1 comme illustré dans la figure 1.The arrangement illustrated in FIG. 1 thus ensures that the voltage present at the output node of the voltage divider circuit 5, namely the connection node between the resistors 51 and 52, is substantially equal to the reference voltage V REF . values R1, R2 of the resistors 51 and 52 being chosen so that the regulated output voltage V REG of the regulator circuit 1 has a determined value, for example of the order of 5 volts. This regulated voltage V REG feeds in particular the differential amplifier 4 and the reference cell 6 of the regulator 1 as illustrated in FIG.

Un inconvénient du circuit régulateur de la figure 1 réside notamment dans le choix du dispositif externe de régulation 2 et les coûts de ce dispositif de régulation. Dans l'exemple de la figure 1, on comprendra que le transistor JFET doit être choisi pour résister à des tensions drain-source relativement élevées (dans l'exemple de l'ordre de max. 25 volts), cette tension drain-source étant notamment fonction de la tension d'entrée haute VHV et de la tension régulée VREG que l'on désire délivrer en sortie du régulateur. On notera que le coût de ce transistor JFET augmente avec la tension drain-source maximale à laquelle cet élément de régulation peut être soumis. Il est donc désirable, notamment dans l'optique de réduire les coûts, de proposer une solution alternative à la solution présentée dans la figure 1.A disadvantage of the regulator circuit of FIG. 1 resides notably in the choice of the external regulation device 2 and the costs of this regulation device. In the example of FIG. 1, it will be understood that the JFET transistor must be chosen to withstand relatively high drain-source voltages (in the example of the order of 25 volts), this drain-source voltage being in particular a function of the high input voltage V HV and the regulated voltage V REG that it is desired to deliver at the output of the regulator. Note that the cost of this JFET transistor increases with the maximum drain-source voltage at which this regulating element can be subjected. It is therefore desirable, particularly with a view to reducing costs, to propose an alternative solution to the solution presented in FIG.

Un autre inconvénient de la solution illustrée dans la figure 1 réside dans le fait que la grille du transistor JFET formant le dispositif externe de régulation 2 est directement commandée par la sortie de l'amplificateur différentiel 4. La tension de grille du transistor JFET est donc limitée par la tension de sortie de l'amplificateur différentiel 4 qui est elle-même dépendante de la technologie utilisée.Another disadvantage of the solution illustrated in Figure 1 lies in the fact that the gate of the JFET transistor forming the external regulating device 2 is directly controlled by the output of the differential amplifier 4. The voltage of gate of the JFET transistor is therefore limited by the output voltage of the amplifier differential 4 which is itself dependent on the technology used.

Un sérieux inconvénient de la solution de la figure 1 réside donc dans le fait que son application est limitée par la tension d'entrée haute susceptible d'être appliquée à l'entrée du régulateur ainsi que par la tension de sortie régulée que l'on désire délivrer. Ainsi, si la tension d'entrée haute venait à être augmentée et/ou si la tension de sortie régulée venait à être réduite, par exemple à 3 volts, les limites imposées par la technologie rendraient l'utilisation du circuit régulateur de la figure 1 trop coûteuse voire même impossible, en particulier lorsque l'on désire fabriquer ce régulateur dans une technologie inférieure au micron.A serious disadvantage of the solution of Figure 1 lies in the fact that its application is limited by the high input voltage likely to be applied to the regulator input as well as through the regulated output voltage that one wants to deliver. Thus, if the high input voltage were to be increased and / or if the regulated output voltage had to be reduced, for example to 3 volts, the limits imposed by the technology would make use of the regulator circuit of Figure 1 too expensive or even impossible, especially when you want to make this regulator in a technology below the micron.

Dans un même ordre d'idée, on peut citer le document intitulé "Smart Power ICs - Technologies and Applications" particulièrement les pages 435 à 463 du chapitre 11 rédigé par B. Murari et al. (Eds.) et édité en 1996 par Springer Verlag, Berlin, Deutschland. Dans ce document, il est décrit un circuit régulateur haute-tension destiné à un chargeur de batterie. Ce circuit régulateur comprend notamment un circuit diviseur de tension délivrant en sortie une tension divisée, une cellule de référence délivrant en sortie une tension de référence déterminée, un amplificateur différentiel recevant en entrée la tension divisée et la tension de référence et un transistor VDMOS dont la grille est connectée à la sortie de l'amplificateur.In the same vein, we can cite the document entitled "Smart Power ICs - Technologies and Applications "particularly pages 435 to 463 of the chapter 11 written by B. Murari et al. (Eds.) And published in 1996 by Springer Verlag, Berlin, Deutschland. In this document, a high-voltage regulator circuit is described intended for a battery charger. This regulator circuit includes a voltage divider circuit outputting a divided voltage, a cell of reference outputting a determined reference voltage, an amplifier differential receiving as input the divided voltage and the reference voltage and a VDMOS transistor whose gate is connected to the output of the amplifier.

La présente invention a donc pour but de proposer une solution permettant de remédier aux inconvénients susmentionnés, et notamment proposer une solution permettant l'utilisation d'un dispositif de régulation externe moins coûteux ainsi qu'une solution pouvant être utilisée avec des tensions d'entrée hautes plus élevées.The present invention therefore aims to propose a solution allowing to overcome the aforementioned drawbacks, and in particular to propose a solution allowing the use of a less expensive external control device as well as a solution that can be used with higher high input voltages.

Un autre but de la présente invention est de proposer une solution pouvant être réalisée et fabriquée dans une technologie CMOS inférieure au micron, en particulier dans une technologie CMOS 0.5 µm.Another object of the present invention is to propose a solution that can be made and manufactured in less than one micron CMOS technology, particularly in 0.5 μm CMOS technology.

La présente invention a ainsi pour objet un régulateur haute-tension dont les caractéristiques sont énoncées dans la revendication 1.The present invention thus relates to a high-voltage regulator whose features are set forth in claim 1.

Des modes de réalisation avantageux de la présente invention font l'objet des revendications indépendantes.Advantageous embodiments of the present invention are the subject of the independent claims.

D'une manière générale, selon la présente invention, le dispositif de régulation externe est avantageusement commandé par l'intermédiaire d'un transistor MOSFET haute-tension spécifique susceptible de voir à ses bornes une tension drain-source de l'ordre de quelques dizaines de volts. De la sorte, les contraintes imposées sur le dispositif de régulation ainsi que sur l'amplificateur différentiel sont moindres, ceci impliquant notamment des coûts moins élevés en ce qui concerne le dispositif de régulation externe.In general, according to the present invention, the regulating device external is advantageously controlled via a MOSFET transistor high-specific voltage likely to see at its terminals a drain-source voltage of the order of a few tens of volts. In this way, the constraints imposed on the regulating device as well as on the differential amplifier are less, this including lower costs for the external regulation.

Bien que la présente invention nécessite l'utilisation d'éléments additionnels, les coûts supplémentaires causés par l'adjonction de ces éléments sont néanmoins moindres que l'économie pouvant être espérée sur les coûts liés au dispositif de régulation externe. En outre, les transistors MOSFET haute-tension utilisés dans le cadre de la présente invention sont parfaitement compatibles avec la technologie CMOS standard et ne nécessitent pas ou peu de masques et/ou d'implantation additionnels pour leur fabrication.Although the present invention requires the use of additional elements, additional costs caused by the addition of these elements are nevertheless less than the economy that can be expected from the costs of external regulation. In addition, the high-voltage MOSFET transistors used in the of the present invention are perfectly compatible with the technology Standard CMOS and do not require or few masks and / or implantation additional for their manufacture.

Selon un mode de réalisation préféré de la présente invention, le circuit régulateur est agencé pour délivrer une première tension de sortie régulée, dite intermédiaire, ainsi qu'une seconde tension de sortie régulée permettant l'alimentation de certains composants du circuit régulateur, tels l'amplificateur différentiel et la cellule de référence du régulateur, ainsi que l'alimentation éventuelle de l'électronique d'un dispositif associé, tel par exemple le microprocesseur chargé des opérations d'un dispositif de détection de fumée. Selon ce mode de réalisation préféré, la tension régulée intermédiaire est par exemple utilisée, dans le cadre de l'application à un dispositif de détection de fumée, pour fournir le courant nécessaire à la génération de l'impulsion infrarouge par la diode infrarouge dont sont typiquement équipés ces dispositifs de détection.According to a preferred embodiment of the present invention, the circuit regulator is arranged to deliver a first regulated output voltage, so-called intermediate and a second regulated output voltage certain components of the regulator circuit, such as the differential amplifier and the reference cell of the regulator, as well as the possible power supply of the electronics associated device, such as, for example, the microprocessor responsible for the operations of a smoke detection device. According to this preferred embodiment, the voltage regulated intermediate is used for example in the context of the application to a smoke detection device, to provide the current required for the generation of the infrared pulse by the infrared diode which these are typically equipped with detection devices.

Dans le cadre d'une application dans un détecteur de fumée et contrairement au circuit régulateur de la figure 1, on notera que ce mode de réalisation préféré de la présente invention permet le déplacement de la diode infrarouge de l'entrée sur la sortie du circuit régulateur où est délivrée la tension régulée intermédiaire. La tension nécessaire à la génération de l'impulsion infrarouge dans un dispositif de détection de fumée est typiquement de l'ordre d'une dizaine de volts, c'est-à-dire bien supérieure aux niveaux de tensions utilisés pour alimenter l'électronique du dispositif. Selon ce mode de réalisation de l'invention, cette tension régulée intermédiaire est d'un niveau inférieur à la tension d'entrée du circuit régulateur, permettant ainsi une réduction des pertes lors de la génération de l'impulsion infrarouge, et néanmoins supérieur à la tension d'alimentation de l'électronique afin d'assurer un niveau d'alimentation adéquat en vue de la génération de cette impulsion infrarouge.In the context of an application in a smoke detector and unlike to the regulator circuit of Figure 1, it should be noted that this preferred embodiment of the present invention allows the displacement of the infrared diode of the input on the output of the regulator circuit where the intermediate regulated voltage is delivered. Voltage necessary for the generation of the infrared pulse in a detection device of smoke is typically of the order of ten volts, that is to say much higher at the voltage levels used to power the device electronics. According to this embodiment of the invention, this intermediate regulated voltage is of one level. lower than the input voltage of the regulator circuit, thus enabling a reduction in losses during the generation of the infrared pulse, and yet greater than the supply voltage of the electronics to ensure a power level adequate for the generation of this infrared pulse.

Selon encore un autre mode de réalisation de la présente invention, le circuit régulateur est agencé de sorte que l'amplificateur différentiel commandant le dispositif de régulation externe présente une hystérèse, ceci assurant notamment une stabilité accrue du fonctionnement du régulateur.According to yet another embodiment of the present invention, the circuit regulator is arranged so that the differential amplifier controlling the device external regulation has a hysteresis, this ensuring in particular a stability increased operation of the regulator.

D'autres caractéristiques et avantages de la présente invention apparaítront plus clairement à la lecture de la description détaillée qui suit, faite en référence aux dessins annexés donnés à titre d'exemples non limitatifs et dans lesquels :

  • la figure 1, déjà présentée, est un schéma bloc d'un circuit régulateur haute-tension de l'art antérieur comprenant un dispositif externe de régulation constitué d'un transistor JFET à canal n ;
  • la figure 2 est un schéma bloc général d'un circuit régulateur haute-tension comprenant un dispositif externe de régulation constitué d'un transistor JFET à canal n ;
  • les figures 3a et 3b sont des vues en coupe schématiques de transistors MOSFET à haute tension, respectivement à canal n et à canal p, réalisés selon une technologie CMOS standard ;
  • la figure 4 montre une première variante de réalisation du circuit régulateur haute-tension selon l'invention permettant de délivrer une première tension de sortie régulée de niveau intermédiaire et une seconde tension de sortie régulée de niveau bas ou nominal permettant l'alimentation de composants électroniques ;
  • la figure 5 montre une seconde variante de réalisation du circuit régulateur haute-tension selon l'invention dans laquelle l'amplificateur différentiel commandant le dispositif externe de régulation présente en outre une hystérèse ;
  • la figure 6 est un schéma détaillé d'un exemple de réalisation de l'amplificateur différentiel commandant le dispositif externe de régulation ;
  • la figure 7 est un schéma détaillé d'un exemple de réalisation de l'amplificateur différentiel du circuit régulateur des figures 4 et 5 utilisé pour produire la seconde tension de sortie régulée de niveau bas ; et
  • la figure 8 est un schéma d'un dispositif externe de régulation susceptible de remplacer le transistor JFET utilisé comme dispositif externe de régulation dans les circuits régulateurs des figures 2, 4 et 5.
Other characteristics and advantages of the present invention will appear more clearly on reading the detailed description which follows, made with reference to the appended drawings given as non-limiting examples and in which:
  • FIG. 1, already presented, is a block diagram of a high-voltage regulator circuit of the prior art comprising an external regulation device consisting of an n-channel JFET transistor;
  • FIG. 2 is a general block diagram of a high-voltage regulator circuit comprising an external control device consisting of an n-channel JFET transistor;
  • Figures 3a and 3b are schematic sectional views of high-voltage MOSFET transistors, respectively n-channel and p-channel, made according to a standard CMOS technology;
  • FIG. 4 shows a first embodiment of the high-voltage regulator circuit according to the invention for delivering a first intermediate level regulated output voltage and a second low or nominal level regulated output voltage for supplying electronic components. ;
  • FIG. 5 shows a second embodiment of the high-voltage regulator circuit according to the invention in which the differential amplifier controlling the external regulation device also has a hysteresis;
  • Figure 6 is a detailed diagram of an exemplary embodiment of the differential amplifier controlling the external control device;
  • Fig. 7 is a detailed diagram of an exemplary embodiment of the differential amplifier of the regulator circuit of Figs. 4 and 5 used to produce the second low level regulated output voltage; and
  • FIG. 8 is a diagram of an external regulating device capable of replacing the JFET transistor used as an external regulating device in the regulator circuits of FIGS. 2, 4 and 5.

La figure 2 montre un schéma bloc général d'un circuit régulateur haute-tension permettant de délivrer une tension de sortie régulée désignée VREG1. Comme précédemment en référence à la figure 1, ce circuit régulateur est désigné globalement par la référence numérique 1 et comprend notamment un dispositif externe de régulation 2, constitué dans cet exemple d'un unique transistor JFET à canal n, ainsi qu'un circuit intégré de commande désigné globalement par la référence numérique 10, par exemple réalisé sous la forme d'un ASIC.FIG. 2 shows a general block diagram of a high-voltage regulator circuit for delivering a regulated output voltage designated V REG1 . As previously with reference to FIG. 1, this regulator circuit is denoted globally by the reference numeral 1 and comprises in particular an external regulation device 2, constituted in this example by a single n-channel JFET transistor, as well as an integrated circuit. command generally designated by the reference numeral 10, for example realized in the form of an ASIC.

Dans le cadre de l'application spécifique comme régulateur de tension dans un dispositif de détection de fumée, la haute tension d'entrée VHV peut varier dans cet exemple de 15 à 50 volts environ. La tension de sortie régulée VREG1 est dans cet exemple de l'ordre d'une dizaine de volts.In the context of the specific application as a voltage regulator in a smoke detection device, the high input voltage V HV may vary in this example from about 15 to about 50 volts. The regulated output voltage V REG1 is in this example of the order of ten volts.

Le dispositif externe de régulation 2 comprend un terminal d'entrée 21 (le drain du transistor JFET) connecté à la tension d'entrée haute VHV, un terminal de sortie 22 (la source du transistor JFET) sur lequel est délivrée la tension de sortie régulée VREG1, et un terminal de commande 23 (la grille du transistor JFET) par le biais duquel l'état de conduction du dispositif externe de régulation 2 est commandé. Les terminaux de commande 23 et de sortie 22 sont respectivement reliés à des bornes 11 et 12 du circuit intégré 10. Une borne 13 du circuit intégré 10 est reliée à la masse VSS du circuit. On notera déjà ici que d'autres dispositifs externe de régulation pourraient être utilisés en lieu et place du transistor JFET. La figure 8, qui sera discutée ultérieurement de manière détaillée, présente par exemple un autre dispositif externe de régulation comprenant un agencement de deux transistors bipolaires complémentaires et d'une résistance.The external regulation device 2 comprises an input terminal 21 (the drain of the JFET transistor) connected to the high input voltage V HV , an output terminal 22 (the source of the JFET transistor) on which the voltage is supplied. regulated output V REG1 , and a control terminal 23 (the gate of the JFET transistor) through which the conduction state of the external regulating device 2 is controlled. The control terminals 23 and output terminals 22 are respectively connected to terminals 11 and 12 of the integrated circuit 10. A terminal 13 of the integrated circuit 10 is connected to the ground V SS of the circuit. It will be noted here that other external control devices could be used instead of the JFET transistor. Figure 8, which will be discussed in detail later, for example has another external control device comprising an arrangement of two complementary bipolar transistors and a resistor.

Le circuit intégré 10 comporte essentiellement un amplificateur différentiel 4, un circuit diviseur de tension 5, une cellule de référence 6, ainsi qu'un élément de commande haute-tension 3. Le circuit diviseur de tension 5 est formé dans cet exemple de deux résistances 51, 52 branchées en série entre la borne 12 du circuit intégré 10, à savoir le terminal de sortie du dispositif externe de régulation 2, et la masse VSS du circuit. On comprendra bien évidemment que d'autres circuits diviseurs de tension pourraient être utilisés par l'homme du métier. Le circuit régulateur 1 comporte en outre typiquement un élément capacitif externe CEXT1 formant tampon branché sur le terminal de sortie 22.The integrated circuit 10 essentially comprises a differential amplifier 4, a voltage divider circuit 5, a reference cell 6, and a high-voltage control element 3. The voltage divider circuit 5 is formed in this example of two resistors 51, 52 connected in series between the terminal 12 of the integrated circuit 10, namely the output terminal of the external regulating device 2, and the ground V SS of the circuit. It will of course be understood that other voltage divider circuits could be used by those skilled in the art. The regulator circuit 1 furthermore typically comprises an external capacitive element C EXT1 forming a buffer connected to the output terminal 22.

Le noeud de connexion entre les deux résistances 51, 52 est relié à une première borne d'entrée de l'amplificateur différentiel 4. On aura aisément compris que la tension appliquée sur cette première borne d'entrée de l'amplificateur différentiel 4 ainsi que la tension régulée VREG1 sont proportionnelles dans un rapport déterminé par les valeurs R1 et R2 des résistances 51, 52. La seconde borne d'entrée de l'amplificateur différentiel 4 est reliée quant à elle à la cellule de référence 6 produisant une tension de référence désignée VREF, cette cellule de référence 6 étant typiquement une cellule du type « bandgap » délivrant une tension de référence par exemple de l'ordre de 1.2 volts environ.The connection node between the two resistors 51, 52 is connected to a first input terminal of the differential amplifier 4. It will be easily understood that the voltage applied to this first input terminal of the differential amplifier 4 as well as the regulated voltage V REG1 are proportional in a ratio determined by the values R1 and R2 of the resistors 51, 52. The second input terminal of the differential amplifier 4 is connected to the reference cell 6 producing a voltage of designated reference REF , this reference cell 6 is typically a cell of the "bandgap" type delivering a reference voltage for example of the order of about 1.2 volts.

La sortie de l'amplificateur différentiel 4 est appliquée sur la grille d'un transistor MOSFET haute-tension 3 d'un type spécifique. Ce transistor MOSFET haute-tension 3, ici du type à canal-n, est déjà connu de l'homme du métier. La particularité de ce transistor haute-tension réside notamment dans la structure spécifique de l'oxyde de grille qui présente une épaisseur plus importante du côté drain que du côté source ainsi que dans la présence d'une zone tampon du côté drain constituée d'un caisson de type n (ou p pour un transistor MOSFET haute-tension à canal-p).The output of the differential amplifier 4 is applied to the gate of a High-voltage MOSFET transistor 3 of a specific type. This MOSFET transistor high-voltage 3, here of the n-channel type, is already known to those skilled in the art. The particularity of this high-voltage transistor lies in particular in the structure specificity of the gate oxide which has a greater thickness on the side drain that on the source side as well as in the presence of a buffer zone on the drain side consisting of an n-type well (or p for a high-voltage MOSFET transistor p-channel).

Les figures 3a et 3b montrent respectivement les schémas d'un transistor MOSFET à canal n haute-tension, ou HVNMOS, et d'un transistor MOSFET à canal p haute-tension, ou HVPMOS. Les transistors HVNMOS présentent notamment l'avantage d'une tension de claquage élevée typiquement supérieure à 30 volts. Un autre avantage de ce type de transistor réside dans le fait que leur fabrication est parfaitement compatible avec la technologie CMOS standard.FIGS. 3a and 3b respectively show the diagrams of a transistor HIGH VOLTAGE N-CHANNEL MOSFET, OR HVNMOS, AND A P-CHANNEL MOSFET high-voltage, or HVPMOS. The HVNMOS transistors notably present the advantage of a high breakdown voltage typically greater than 30 volts. A another advantage of this type of transistor lies in the fact that their manufacture is perfectly compatible with standard CMOS technology.

Pour de plus amples détails concernant ce type de transistors haute-tension, on pourra notamment se référer à l'article de MM. C. Bassin, H. Ballan et M. Declercq intitulé « High-Voltage Devices for 0.5-µm Standard CMOS Technology », IEEE Electron Device Letters, vol. 21, No. 1, Janvier 2000, relatif à la fabrication de tels transistors haute-tension en technologie 0.5 microns. A titre d'exemple, il ressort de la Table 1 de ce document qu'un transistor MOSFET haute-tension à canal-n ayant une tension de claquage de l'ordre de 30 volts peut être réalisé en technologie CMOS standard sans que cela ne nécessite de masques ou d'implants additionnels.For further details concerning this type of high-voltage transistors, we can in particular refer to the article by MM. C. Bassin, H. Ballan and M. Declercq entitled "High-Voltage Devices for 0.5-μm CMOS Standard Technology", IEEE Electron Device Letters, Vol. 21, No. 1, January 2000, relating to the manufacture of such High-voltage transistors in 0.5 micron technology. For example, it appears from the Table 1 of this document that a n-channel high-voltage MOSFET having a breakdown voltage of the order of 30 volts can be achieved in CMOS technology standard without the need for additional masks or implants.

En se référant à nouveau à la figure 2, on peut constater que le transistor MOSFET haute-tension 3 est connecté, du côté drain, au terminal de commande 23 du dispositif externe de régulation 2 via la borne 11, et, du côté source, à la masse VSS via la borne 13. Afin d'assurer une polarisation adéquate du transistor JFET formant le dispositif externe de régulation 2, une résistance 30 de valeur R0 est connectée entre les bornes 11 et 12 du circuit intégré 10, à savoir entre les terminaux de commande 23 et de sortie 22 du dispositif externe de régulation 2. On notera que cette résistance 30 n'est nécessaire que dans le cas où le dispositif externe de régulation 2 est constitué d'un transistor JFET comme illustré. Dans l'éventualité où le dispositif externe de régulation était réalisé sous la forme d'un agencement de transistors bipolaires comme illustré en figure 8, cette résistance 30 n'est plus nécessaire.Referring again to FIG. 2, it can be seen that the high-voltage MOSFET transistor 3 is connected on the drain side to the control terminal 23 of the external regulation device 2 via the terminal 11, and on the source side to the ground V SS via the terminal 13. In order to ensure adequate polarization of the transistor JFET forming the external regulating device 2, a resistor 30 of value R0 is connected between the terminals 11 and 12 of the integrated circuit 10, namely between the control terminals 23 and output 22 of the external regulating device 2. It will be noted that this resistor 30 is only necessary in the case where the external regulating device 2 consists of a JFET transistor as illustrated. In the event that the external regulating device were constructed as an arrangement of bipolar transistors as illustrated in FIG. 8, this resistor 30 is no longer necessary.

Dans la figure 2, on notera que l'amplificateur différentiel 4 ainsi que la cellule de référence 6 sont alimentés par une tension d'alimentation VDD, par exemple de l'ordre de 3 volts. Dans la suite de la présente description, selon la présente invention, cette tension d'alimentation VDD est avantageusement également délivrée par le circuit régulateur 1 lui-même.In FIG. 2, it will be noted that the differential amplifier 4 as well as the reference cell 6 are powered by a supply voltage V DD , for example of the order of 3 volts. In the remainder of the present description, according to the present invention, this supply voltage V DD is advantageously also delivered by the regulator circuit 1 itself.

Selon l'invention, on notera que les seuls éléments devant supporter des tensions élevée à leurs bornes sont le transistor 3 et les résistances 30, 51 et 52, ces dernières étant avantageusement intégrées sous la forme de régions de diffusion de type n ou résistances « n-well ». L'amplificateur différentiel 4 est quant à lui un amplificateur différentiel conventionnel ne devant supporter que des tensions basses à ses bornes.According to the invention, it will be noted that the only elements that must support high voltages at their terminals are the transistor 3 and the resistors 30, 51 and 52, these the latter being advantageously integrated in the form of diffusion regions of type n or "n-well" resistors. The differential amplifier 4 is itself a conventional differential amplifier only supporting low voltages at its terminals.

La figure 4 montre un circuit régulateur selon l'invention dans lequel le circuit intégré 10 comporte en outre des moyens, désignés globalement par la référence numérique 100, pour délivrer une seconde tension de sortie régulée VREG2 permettant avantageusement d'alimenter divers composants électroniques du circuit régulateur, tels notamment l'amplificateur différentiel 4 et la cellule de référence 6, ou d'autres composants électroniques associés au régulateur. Dans la figure 4, on notera que la tension de sortie régulée VREG2 est utilisée comme tension d'alimentation VDD pour l'amplificateur différentiel 4 et la cellule de référence 6.FIG. 4 shows a regulator circuit according to the invention in which the integrated circuit 10 further comprises means, indicated generally by the reference numeral 100, for delivering a second regulated output voltage V REG2 advantageously for supplying various electronic components of the control circuit, such as in particular the differential amplifier 4 and the reference cell 6, or other electronic components associated with the regulator. In FIG. 4, it will be noted that the regulated output voltage V REG2 is used as the supply voltage V DD for the differential amplifier 4 and the reference cell 6.

Les moyens 100 comprennent préférablement, comme illustré, un second transistor MOSFET haute-tension à canal n désigné par la référence numérique 101, un élément de régulation 102 constitué dans cet exemple d'un transistor p-MOS, un amplificateur différentiel 104 et un circuit diviseur de tension 105.The means 100 preferably comprise, as illustrated, a second high-voltage n-channel MOSFET transistor designated by the numeral 101, a control element 102 constituted in this example of a p-MOS transistor, a differential amplifier 104 and a voltage divider circuit 105.

Le transistor MOSFET haute-tension 101 est analogue au transistor 3 et est branché par son terminal de drain au terminal de sortie 22 du dispositif externe de régulation 2, et, par son terminal de source au terminal de source du transistor p-MOS 102. La grille du transistor MOSFET haute-tension 101 est reliée au circuit diviseur de tension 5 au noeud de connexion entre des résistances 53 et 54. Ces résistances 53 et 54 en série remplacent la résistance 51 de la figure 2 et la somme des valeurs R11 et R12 de ces résistances 53 et 54 est équivalente à la valeur R1 de la résistance 51 de la figure 2. Le rapport de division du circuit diviseur de tension 5 reste ainsi inchangé en ce qui concerne la tension appliquée sur l'entrée de l'amplificateur différentiel 4.The high-voltage MOSFET 101 is analogous to transistor 3 and is connected by its drain terminal to the output terminal 22 of the external device of regulation 2, and, by its source terminal at the source terminal of the p-MOS transistor 102. The gate of the high-voltage MOSFET transistor 101 is connected to the divider circuit of voltage 5 at the connection node between resistors 53 and 54. These resistors 53 and 54 in series replace the resistor 51 of Figure 2 and the sum of the R11 values and R12 of these resistors 53 and 54 is equivalent to the value R1 of the resistor 51 of FIG. 2. The division ratio of the voltage divider circuit 5 thus remains unchanged with respect to the voltage applied to the amplifier input differential 4.

Le rapport des résistances R11, R12 et R2 est choisi de sorte que la tension appliquée sur la grille du transistor haute-tension 101 provoque une chute de potentiel déterminée entre drain et source de ce transistor 101, la tension présente sur la source de ce transistor 101 étant alors représentative de la tension de sortie VREG1 moins la chute de potentiel déterminée présente aux bornes du transistor 101. On comprendra donc que le rôle essentiel du transistor haute-tension 101 est d'abaisser la tension de sortie VREG1 à un niveau tolérable pour les circuits situés en aval.The ratio of the resistors R11, R12 and R2 is chosen so that the voltage applied to the gate of the high-voltage transistor 101 causes a determined potential drop between drain and source of this transistor 101, the voltage present on the source of this transistor 101 being then representative of the output voltage V REG1 minus the determined potential drop across the terminals of the transistor 101. It will therefore be understood that the essential role of the high-voltage transistor 101 is to lower the output voltage V REG1 to a level tolerable for downstream circuits.

Le circuit diviseur de tension 105 est constitué dans cet exemple de l'agencement série, entre le terminal de drain du transistor p-MOS 102 et la masse VSS, de deux résistances 151 et 152, le rapport de division de ce circuit diviseur 105 étant déterminé par les valeurs R3 et R4 de ces résistances. La seconde tension de sortie régulée VREG2 est délivrée à une borne 14 du circuit intégré 10 sur le terminal de drain du transistor p-MOS 102 aux bornes du circuit diviseur de tension 105, un second élément capacitif CEXT2 formant tampon étant typiquement branché à cette borne 14.In this example of the series arrangement, the voltage divider circuit 105 is constituted, between the drain terminal of the p-MOS transistor 102 and the ground V SS , of two resistors 151 and 152, the division ratio of this divider circuit 105. being determined by the values R3 and R4 of these resistances. The second regulated output voltage V REG2 is delivered to a terminal 14 of the integrated circuit 10 on the drain terminal of the p-MOS transistor 102 across the voltage divider circuit 105, a second capacitive capacitor C EXT2 element typically being connected to the this marker 14.

Le noeud de connexion entre les deux résistances 151 et 152 est relié à une première borne d'entrée de l'amplificateur différentiel 104. La tension appliquée sur cette première borne d'entrée de l'amplificateur différentiel 104 ainsi que la seconde tension de sortie régulée VREG2 sont proportionnelles dans un rapport déterminé par les valeurs R3 et R4 des résistances 151, 152. La seconde borne d'entrée de l'amplificateur différentiel 104 est reliée, de manière analogue à l'amplificateur différentiel 4, à la cellule de référence 6 produisant la tension de référence VREF.The connection node between the two resistors 151 and 152 is connected to a first input terminal of the differential amplifier 104. The voltage applied to this first input terminal of the differential amplifier 104 as well as the second output voltage Regulated V REG2 are proportional in a ratio determined by the values R3 and R4 of the resistors 151, 152. The second input terminal of the differential amplifier 104 is connected, analogously to the differential amplifier 4, to the control cell. reference 6 producing the reference voltage V REF .

La sortie de l'amplificateur différentiel 104 est appliquée sur la grille du transistor p-MOS 102. On comprendra à nouveau que l'agencement de l'amplificateur différentiel 104 illustré dans la figure 4 impose que la tension présente au noeud de sortie du circuit diviseur de tension 105, à savoir le noeud de connexion entre les résistances 151 et 152, soit sensiblement égale à la tension de référence VREF, les valeurs R3 et R4 des résistances étant choisies de sorte que la seconde tension de sortie régulée VREG2 du circuit régulateur 1 ait une valeur déterminée, par exemple de l'ordre de 3 volts. Cette tension régulée VREG2 alimente notamment l'amplificateur différentiel 4 et la cellule de référence 6 du régulateur 1 comme déjà mentionné.The output of the differential amplifier 104 is applied to the gate of the p-MOS transistor 102. It will again be understood that the arrangement of the differential amplifier 104 illustrated in FIG. 4 imposes that the voltage present at the output node of the circuit voltage divider 105, namely the connection node between the resistors 151 and 152, is substantially equal to the reference voltage V REF , the values R3 and R4 of the resistors being chosen so that the second regulated output voltage V REG2 of the Regulator circuit 1 has a determined value, for example of the order of 3 volts. This regulated voltage V REG2 supplies, in particular, the differential amplifier 4 and the reference cell 6 of the regulator 1 as already mentioned.

Contrairement à l'amplificateur différentiel 4, l'alimentation de l'amplificateur différentiel 104 est assurée, d'une part, par la masse VSS et, d'autre part, par la tension présente au niveau du terminal de source du transistor p-MOS 102. Avantageusement, un élément capacitif 106 est disposé sur la sortie de l'amplificateur différentiel 104 entre les terminaux de grille et de drain du transistor p-MOS 102. Cet élément capacitif 106 assure une stabilité de la tension de sortie régulée VREG2.Unlike the differential amplifier 4, the supply of the differential amplifier 104 is provided, on the one hand, by the mass V SS and, on the other hand, by the voltage present at the source terminal of the transistor p Advantageously, a capacitive element 106 is disposed on the output of the differential amplifier 104 between the gate and drain terminals of the p-MOS transistor 102. This capacitive element 106 provides a stability of the regulated output voltage V REG2 .

Dans le cadre spécifique d'une application dans un détecteur de fumée, le circuit régulateur selon l'invention permet le déplacement de la diode infrarouge du détecteur, nécessaire à la génération de l'impulsion infrarouge, de l'entrée vers la sortie du circuit régulateur sur la borne 12 du circuit où est délivrée la tension de sortie régulée VREG1. La figure 4 montre schématiquement l'agencement de cette diode infrarouge indiquée par la référence numérique 200 et du moyen de commande 210 monté en série avec la diode 200, ici un transistor bipolaire, permettant le déclenchement de l'impulsion infrarouge.In the specific context of an application in a smoke detector, the regulator circuit according to the invention allows the displacement of the infrared diode of the detector, necessary for the generation of the infrared pulse, from the input to the output of the circuit. regulator on the terminal 12 of the circuit where the regulated output voltage V REG1 is delivered. Figure 4 schematically shows the arrangement of this infrared diode indicated by the reference numeral 200 and control means 210 connected in series with the diode 200, here a bipolar transistor, for triggering the infrared pulse.

Par rapport à la solution antérieure de la figure 1, la présente invention permet ainsi une réduction des pertes lors de la génération de l'impulsion infrarouge, notamment car la tension régulée utilisée pour cette génération est moindre que la tension d'entrée. Au moyen de la solution de la figure 1, on rappellera à nouveau que la diode infrarouge et son moyen de commande sont placé à l'entrée haute-tension 21, la tension de sortie régulée n'étant pas suffisante pour alimenter cette diode infrarouge et permettre la génération de l'impulsion requise.Compared with the previous solution of FIG. 1, the present invention makes it possible thus a reduction of the losses during the generation of the infrared pulse, especially because the regulated voltage used for this generation is less than the input voltage. Using the solution in Figure 1, it will be recalled again that the infrared diode and its control means are placed at the high voltage input 21, the regulated output voltage is not sufficient to supply this diode infrared and allow the generation of the required pulse.

Comme déjà mentionné, l'amplificateur différentiel 4 utilisé dans le circuit régulateur de la figure 2 ou 4 est un amplificateur différentiel de type conventionnel dont un exemple de réalisation est illustré dans la figure 6. L'amplificateur différentiel 4 illustré dans la figure 6 comprend une paire différentielle de transistors M1, M2 (en l'occurrence deux transistors p-MOS identiques), les grilles desquels forment les entrées de l'amplificateur différentiel 4. Chaque transistor M1, M2 est branché en série dans la branche de référence d'un miroir de courant 41, 42, chaque miroir de courant 41, 42 comprenant de manière conventionnelle deux transistors n-MOS M11, M12 et M21, M22 branchés grille à grille. Les transistors M12 et M22 des branches de sortie des miroirs de courant 41 et 42 sont eux-même branchés respectivement dans les branches de référence et de sortie d'un autre miroir de courant désigné globalement par la référence numérique 43 et comprenant deux transistors p-MOS M13 et M23. La sortie de l'amplificateur différentiel 4 est formée du noeud de connexion entre les transistors p-MOS M23 et n-MOS M22 de la branche de sortie du miroir de courant 43.As already mentioned, the differential amplifier 4 used in the circuit controller of Figure 2 or 4 is a conventional type differential amplifier an exemplary embodiment of which is illustrated in Figure 6. The differential amplifier 4 illustrated in FIG. 6 comprises a differential pair of transistors M1, M2 (in the occurrence of two identical p-MOS transistors), the gates of which form the differential amplifier inputs 4. Each transistor M1, M2 is connected in series in the reference branch of a current mirror 41, 42, each mirror of current 41, 42 conventionally comprising two n-MOS transistors M11, M12 and M21, M22 connected grid grid. M12 and M22 transistors of the branches of current mirrors 41 and 42 are themselves connected respectively to the reference and exit branches of another designated current mirror globally by the reference numeral 43 and comprising two p-MOS transistors M13 and M23. The output of the differential amplifier 4 is formed of the node of connection between the p-MOS transistors M23 and n-MOS M22 of the output branch of the current mirror 43.

Un transistor p-MOS M3 connecté entre le terminal d'alimentation VDD et le noeud de connexion des transistors p-MOS M1, M2 de la paire différentielle d'entrée assure une polarisation adéquate des transistors, une tension de polarisation déterminée VBIAS étant appliquée sur la grille de ce transistor p-MOS M3.A p-MOS transistor M3 connected between the power supply terminal V DD and the connection node of the p-MOS transistors M1, M2 of the input differential pair ensures adequate polarization of the transistors, a determined bias voltage V BIAS being applied to the gate of this p-MOS transistor M3.

Dans l'illustration de la figure 6, l'amplificateur différentiel 4 comporte en outre un étage de sortie additionnel comprenant des transistors p-MOS M5 et n-MOS M6 formant un agencement inverseur permettant de délivrer le signal de sortie désigné OUT et son inverse OUT_B, un transistor p-MOS M4 commandé par la tension de polarisation VBIAS étant branché en série avec ces transistors M5, M6 afin d'assurer une polarisation adéquate de ces derniers. De la sorte, l'amplificateur différentiel 4 forme un comparateur délivrant en sortie des signaux de niveaux logiques. In the illustration of FIG. 6, the differential amplifier 4 further comprises an additional output stage comprising p-MOS transistors M5 and n-MOS M6 forming an inverter arrangement for delivering the output signal designated OUT and its inverse OUT_B, a p-MOS transistor M4 controlled by the bias voltage V BIAS being connected in series with these transistors M5, M6 to ensure proper polarization of the latter. In this way, the differential amplifier 4 forms a comparator outputting logic level signals.

Il convient de mentionner que la structure de l'amplificateur différentiel 4 illustrée dans la figure 6 n'est donnée qu'à titre d'exemple uniquement et que d'autres configurations pourraient être envisagées par l'homme du métier.It should be mentioned that the structure of the differential amplifier 4 shown in Figure 6 is for illustrative purposes only and other configurations could be envisaged by the skilled person.

L'amplificateur différentiel 104 utilisé dans le circuit régulateur de la figure 4 doit être conçu pour tolérer des tensions plus élevées à ses bornes et peut être réalisé sur la base d'un schéma analogue à l'amplificateur différentiel 4 de la figure 6 en employant des montages cascodes bien connus de l'homme du métier, c'est-à-dire des montages de deux ou plusieurs transistors en série. La figure 7 montre un exemple de réalisation d'un tel amplificateur différentiel utilisant des techniques de montage cascode.The differential amplifier 104 used in the regulator circuit of FIG. must be designed to tolerate higher voltages at its terminals and may be realized on the basis of a diagram similar to the differential amplifier 4 of FIG. by employing cascode montages well known to those skilled in the art, that is to say assemblies of two or more transistors in series. Figure 7 shows a example of realization of such a differential amplifier using cascode editing.

Les transistors Q1, Q2, Q11, Q12, Q21, Q22, Q13, Q23 et Q3 remplissent essentiellement les mêmes rôles que les transistors M1, M2, M11, M12, M21, M22, M13, M23 et M3 du circuit de la figure 6. Des montages cascodes sont utilisés afin de limiter les tensions susceptibles d'apparaítre aux bornes des transistors de cet amplificateur différentiel 104, notamment les transistors branchés entre les tensions d'alimentation VP et Vss. On notera que la tension VP est prélevée sur la source du transistor MOSFET haute-tension 101. Ainsi les transistors Q12 et Q22 sont chacun branchés en série respectivement avec un second transistor n-MOS Q51 disposé entre les transistors Q12 et Q13 et un second transistor n-MOS Q52 disposé entre les transistors Q22 et Q23. De même, les transistors Q3 et Q23 sont chacun branchés en série avec un second transistor p-MOS Q41 disposé entre le transistor Q3 et le noeud de connexion de la paire différentielle et un second transistor p-MOS Q42 disposé entre les transistors Q22 et Q23. La borne de sortie de l'amplificateur différentiel 104 est formée du noeud de connexion entre les transistors Q42 et Q52.The transistors Q1, Q2, Q11, Q12, Q21, Q22, Q13, Q23 and Q3 essentially fulfill the same roles as the transistors M1, M2, M11, M12, M21, M22, M13, M23 and M3 of the circuit of FIG. Cascode assemblies are used in order to limit the voltages likely to occur across the transistors of this differential amplifier 104, in particular the transistors connected between the supply voltages V P and Vss. It will be noted that the voltage V P is taken from the source of the high voltage MOSFET transistor 101. Thus the transistors Q12 and Q22 are each connected in series respectively with a second n-MOS transistor Q51 arranged between the transistors Q12 and Q13 and a second n-MOS transistor Q52 disposed between transistors Q22 and Q23. Similarly, transistors Q3 and Q23 are each connected in series with a second p-MOS transistor Q41 disposed between transistor Q3 and the connection node of the differential pair and a second p-MOS transistor Q42 disposed between transistors Q22 and Q23. . The output terminal of the differential amplifier 104 is formed of the connection node between the transistors Q42 and Q52.

Un transistor n-MOS additionnel Q50 forme de manière conventionnelle un miroir de courant avec les transistors Q51 et Q52. De même, un transistor p-MOS additionnel Q40 forme de manière conventionnelle un miroir de courant avec les transistors Q41 et Q42. Chacun de ces transistors Q40 et Q50 est branché en série avec un montage cascode de deux transistors respectivement p-MOS Q43, Q44 et n-MOS Q53, Q54. Le transistor n-MOS Q54 forme encore un miroir de courant avec un autre transistor n-MOS Q55 branché en série dans la branche comprenant les transistors p-MOS Q40, Q43 et Q44.An additional n-MOS transistor Q50 conventionally forms a current mirror with transistors Q51 and Q52. Similarly, a p-MOS transistor additional Q40 form conventionally a current mirror with the transistors Q41 and Q42. Each of these transistors Q40 and Q50 is connected in series with a cascode arrangement of two transistors respectively p-MOS Q43, Q44 and n-MOS Q53, Q54. The n-MOS transistor Q54 still forms a current mirror with a another n-MOS transistor Q55 connected in series in the branch comprising the p-MOS transistors Q40, Q43 and Q44.

La polarisation des transistors est fixée par un courant de polarisation IBIAS appliqué dans le chemin de courant d'un transistor p-MOS Q31 branché en miroir de courant avec le transistor Q3, ce courant de polarisation IBIAS étant lui-même miroité dans la branche comprenant les transistors n-MOS Q50, Q53 et Q54 au moyen d'un transistor p-MOS Q32. The polarization of the transistors is fixed by a bias current I BIAS applied in the current path of a p-MOS transistor Q31 connected in current mirror with the transistor Q3, this polarization current I BIAS being itself mirrored in the branch comprising the n-MOS transistors Q50, Q53 and Q54 by means of a p-MOS transistor Q32.

Le montage illustré dans la figure 7 assure qu'aucun des transistors de cet amplificateur différentiel 104 ne voit à ses bornes une tension trop élevée susceptible de causer un claquage de ce transistor.The assembly illustrated in FIG. 7 assures that none of the transistors of this differential amplifier 104 does not see at its terminals a too high voltage susceptible to cause a breakdown of this transistor.

Au même titre que l'amplificateur différentiel 4 de la figure 6, la configuration de la figure 7 n'est donnée qu'à titre d'exemple uniquement, l'homme du métier pouvant apporter de nombreuses modifications au schéma présenté, voire choisir une configuration alternative. On notera que l'amplificateur différentiel 104 doit essentiellement répondre à des contraintes plus élevées que l'amplificateur différentiel 4 étant donné que celui-ci est alimenté par une tension plus élevée, dans cet exemple typiquement de l'ordre de 4 à 7 volts.In the same way as the differential amplifier 4 of FIG. 6, the configuration of FIG. 7 is given by way of example only, the person skilled in the art can make many modifications to the diagram presented, or even choose a alternative configuration. Note that the differential amplifier 104 must basically meet higher constraints than the differential amplifier 4 because it is powered by a higher voltage, in this example typically of the order of 4 to 7 volts.

La figure 5 montre une autre variante avantageuse du circuit régulateur selon l'invention sensiblement similaire à la variante de la figure 4. Outre les moyens permettant de délivrer la seconde tension de sortie régulée VREG2, l'amplificateur différentiel 4 du circuit régulateur 1 est agencé pour présenter une hystérèse. Cette hystérèse a pour avantage de rendre moins critique la stabilité du régulateur et pour conséquence une variation périodique de la première tension régulée VREG1. Le régulateur de la figure 5 forme de la sorte un régulateur de type « bang-bang » délivrant une tension régulée variant entre deux niveaux de tension déterminés. On notera en outre que l'amplificateur différentiel 4 forme dans cet exemple un comparateur, c'est-à-dire qu'il fournit des signaux de sortie OUT et OUT_B de niveaux logiques.FIG. 5 shows another advantageous variant of the regulator circuit according to the invention substantially similar to the variant of FIG. 4. In addition to the means for delivering the second regulated output voltage V REG2 , the differential amplifier 4 of the regulator circuit 1 is arranged to present a hysteresis. This hysteresis has the advantage of making the stability of the regulator less critical and consequently a periodic variation of the first regulated voltage V REG1 . The regulator of FIG. 5 thus forms a "bang-bang" type regulator delivering a regulated voltage varying between two determined voltage levels. Note further that the differential amplifier 4 forms in this example a comparator, that is to say it provides output signals OUT and OUT_B logic levels.

L'hystérèse de l'amplificateur différentiel peut être générée de diverses manières. L'une d'entre elles est illustrée schématiquement dans la figure 5 et fait appel à deux portes de transmission 7, 8 branchées à l'entrée sur laquelle est appliquée la tension de sortie du circuit diviseur de tension 5, et un inverseur 9 branché sur la sortie de l'amplificateur différentiel 4. Par rapport, à la variante illustrée dans la figure 4, le circuit diviseur 5 est en outre légèrement modifié de sorte que la résistance 54 est subdivisée en deux résistances 55 et 56 dont la somme des valeurs R121 et R122 est équivalente à la valeur R12 de la résistance 54 de la figure 4. L'hystérèse est déterminée par le rapport des valeurs R11, R121, R122 et R2 des résistances 53, 55, 56 et 52.The hysteresis of the differential amplifier can be generated from various ways. One of them is illustrated schematically in Figure 5 and call to two transmission gates 7, 8 connected to the input on which is applied the output voltage of the voltage divider circuit 5, and an inverter 9 connected to the output of the differential amplifier 4. Compared to the illustrated variant in FIG. 4, the divider circuit 5 is furthermore slightly modified so that the resistor 54 is subdivided into two resistors 55 and 56 whose sum of the values R121 and R122 is equivalent to the value R12 of the resistor 54 of Figure 4. The hysteresis is determined by the ratio of the values R11, R121, R122 and R2 of the resistors 53, 55, 56 and 52.

Le noeud de connexion entre les résistances 55 et 56 est connecté à l'entrée de la première porte de transmission 7 et le noeud de connexion entre les résistances 56 et 52 est connecté à l'entrée de la seconde porte de transmission 8. L'état des portes de transmission 7 et 8 est contrôlé en fonction de la sortie de l'amplificateur différentiel 4, les portes de transmission 7 et 8 étant respectivement passante et non-passante lorsque le signal de sortie (non inversé) de l'amplificateur différentiel 4 est à l'état haut, et, à l'opposé, respectivement non passante et passante lorsque le signal de sortie de l'amplificateur différentiel 4est à l'état bas. En l'occurrence, la sortie inversée OUT_B de l'amplificateur différentiel 4 est connectée à la borne inverseuse de la porte 7 et la borne non-inverseuse de la porte 8, cette sortie inversée OUT_B étant par ailleurs appliquée, via l'inverseur 9, sur la borne non-inverseuse de la porte 7 et la borne inverseuse de la porte 8.The connection node between the resistors 55 and 56 is connected to the input of the first transmission gate 7 and the connection node between the resistors 56 and 52 is connected to the input of the second transmission gate 8. The state of the transmission doors 7 and 8 is controlled according to the output of the amplifier differential 4, the transmission gates 7 and 8 being respectively passing and non-passing when the output signal (not inverted) of the differential amplifier 4 is at the high state, and, on the opposite, respectively non-passing and passing when the signal output of the differential amplifier 4 is low. In this case, the exit inverted OUT_B of the differential amplifier 4 is connected to the inverting terminal of the door 7 and the non-inverting terminal of the door 8, this inverted output OUT_B being also applied, via the inverter 9, to the non-inverting terminal of the door 7 and the inverting terminal of the door 8.

Dans le cadre de la réalisation de la figure 5, il est par ailleurs avantageux de commander le dispositif externe de régulation 2 par l'intermédiaire d'un miroir de courant formé de deux transistors MOSFET haute-tension à canal n, à savoir le transistor 3 déjà mentionné et un transistor haute-tension analogue, désigné 3*, dont la grille et le drain sont connectés ensemble à la sortie de l'amplificateur différentiel 4.In the context of the embodiment of FIG. 5, it is also advantageous to control the external regulating device 2 via a mirror of current formed of two n-channel high-voltage MOSFET transistors, namely the transistor 3 already mentioned and a similar high-voltage transistor, designated 3 *, whose the gate and the drain are connected together to the output of the differential amplifier 4.

Finalement, comme déjà mentionné plus haut, le transistor JFET utilisé comme dispositif externe de régulation 2 dans les modes de réalisation décrits ci-dessus pourrait être remplacé par un autre dispositif adéquat. Par exemple, le transistor JFET peut avantageusement être remplacé par le dispositif illustré dans la figure 8 constitué d'un montage conventionnellement nommé « pseudo-Darlington » comprenant deux transistors bipolaires complémentaires, à savoir un transistor bipolaire de type pnp B1 et un transistor bipolaire de type npn B2. On notera qu'un montage Darlingtion comprenant deux transistors bipolaires de même type pourrait alternativement être utilisé en lieu et place du montage pseudo-Darlingtion de la figure 8.Finally, as already mentioned above, the JFET transistor used as an external regulating device 2 in the embodiments described above could be replaced by another suitable device. For example, the JFET transistor can advantageously be replaced by the device illustrated in FIG. Figure 8 consists of an assembly conventionally named "pseudo-Darlington" comprising two complementary bipolar transistors, namely a transistor bipolar pnp type B1 and a bipolar transistor type npn B2. It will be noted that Darlingtion assembly comprising two bipolar transistors of the same type could alternatively be used in place of the pseudo-Darlingtion montage of the figure 8.

Dans l'illustration de la figure 8, l'émetteur et le collecteur du transistor B1 forment respectivement l'entrée 21 sur laquelle est appliquée la haute tension d'entrée VHV et la sortie 22 sur laquelle est délivrée la tension de sortie régulée VREG1, la base de ce transistor B1 étant reliée au collecteur du transistor bipolaire B2, l'émetteur de ce transistor B2 étant connecté au collecteur du transistor B1. La base du transistor B2 forme le terminal de commande 23 du dispositif externe de régulation. On notera que ce dispositif externe de régulation 2 comporte en outre une résistance 25 montée en parallèle entre le terminal d'entrée 21 et le terminal de commande 23.In the illustration of FIG. 8, the emitter and the collector of the transistor B1 respectively form the input 21 on which the high input voltage V HV is applied and the output 22 on which the regulated output voltage V is delivered. REG1 , the base of this transistor B1 being connected to the collector of the bipolar transistor B2, the emitter of this transistor B2 being connected to the collector of the transistor B1. The base of the transistor B2 forms the control terminal 23 of the external control device. It will be noted that this external regulation device 2 further comprises a resistor 25 connected in parallel between the input terminal 21 and the control terminal 23.

Bien que le dispositif illustré dans la figure 8 comprenne un nombre plus élevé de composants, les coûts de ce dispositif sont néanmoins moindres que les coûts liés à l'utilisation d'un transistor JFET, ceci constituant donc un avantage dans l'optique d'une réduction des coûts de fabrication du circuit régulateur.Although the device shown in Figure 8 includes a higher number components, the costs of this device are nevertheless lower than the costs associated with to the use of a JFET transistor, thus constituting an advantage in the optical a reduction in the manufacturing costs of the regulator circuit.

De nombreuses modifications et/ou améliorations de la présente invention peuvent être envisagées sans sortir du cadre de l'invention défini par les revendications annexées. En particulier, le circuit régulateur selon l'invention n'est nullement limité par le type de dispositif externe de régulation utilisé dans les modes de réalisation susmentionnés, à savoir un transistor JFET. Comme mentionné, d'autres agencements adéquats, tel l'agencement de la figure 8, peuvent être utilisés par l'homme du métier.Many modifications and / or improvements of the present invention can be envisaged without departing from the scope of the invention defined by the appended claims. In particular, the regulator circuit according to the invention is in no way limited by the type of external control device used in the modes aforementioned embodiments, namely a JFET transistor. As mentioned, other suitable arrangements, such as the arrangement of FIG. 8, may be used by the skilled person.

Claims (9)

  1. High-voltage regulator circuit (1) for delivering at least a first regulated output voltage (VREG1) from a high input voltage (VHV) having a value higher than the first regulated output voltage, this regulator circuit including a regulation device (2) including an input terminal (21) to which said high input voltage is applied, an output terminal (22) at which said first regulated output voltage is delivered, and a control terminal (23) connected to a control circuit (10) of said external regulation device, this control circuit (10) including:
    a first voltage divider circuit (5) connected between said output terminal (22) and a reference potential or ground (VSS), and delivering at one output a first divided voltage proportional, in a determined ratio, to said first regulated output voltage (VREG1);
    a reference cell (6) delivering at one output a determined reference voltage (VREF);
    a first differential amplifier (4) including first and second inputs to which are respectively applied said first divided voltage delivered by the first voltage divider circuit (5) and said reference voltage (VREF) delivered by the reference cell (6), the output of this first differential amplifier controlling the conduction state of said regulation device (2), and
       a first high-voltage MOSFET transistor (3) including drain, source and gate terminals respectively connected to the control terminal (23) of the regulation device (2), to ground (VSS), and to the output of said first differential amplifier (4),
       characterised in that the regulation device (2) is external to the control circuit (10),
       in that the control circuit (10) includes means (100) able to deliver a second regulated output voltage (VREG2) powering at least said differential amplifier (4) and said reference cell (6), and
       in that said means (100) for delivering a second regulated voltage include:
    a second high-voltage MOSFET transistor (101) including drain, source and gate terminals, the drain and gate terminals of said high-voltage MOSFET transistor (101) being respectively connected to the output terminal (22) of the regulation device (2) and to a second output of the first voltage divider circuit (5) delivering a second divided voltage proportional, in a determined ratio, to said first regulated output voltage (VREG1);
    a regulation element (102) including a first terminal connected to the source terminal of the second high-voltage MOSFET transistor (101), said second regulated output voltage (VREG2) being delivered at a second terminal of the regulation element;
    a second voltage divider circuit (105) connected between the second terminal of the regulation element (102) and ground (VSS), and delivering at one output a divided voltage proportional, in a determined ratio, to said second regulated output voltage (VREG2); and
    a second differential amplifier (104) including first and second inputs to which are respectively applied said divided voltage delivered by said second voltage divider circuit (105), and said reference voltage (VREF) delivered by the reference cell (6), the output of said second differential amplifier (104) being connected to a third terminal of the regulation element (102), said second differential amplifier being powered by the voltage present at the connection node between the source terminals of said second high-voltage MOSFET transistor (101) and the first terminal of said regulation element (102).
  2. Regulator circuit according to claim 1, characterised in that the regulation element (102) is a p-channel MOSFET transistor including drain, source and gate terminals, the source terminal of this p-channel transistor (102) being connected to the source terminal of the second high-voltage MOSFET transistor (101), the drain terminal of said p-channel MOSFET transistor delivering said second regulated output voltage (VREG2) and the gate terminal being connected to the output of the second differential amplifier (104).
  3. Regulator circuit according to claim 1, characterised in that said differential amplifier (4) controlling the conduction state of the external regulation device (2) is arranged to have a hysteresis such that said first regulated voltage (VREG1) varies between first and second determined voltage levels.
  4. Regulator circuit according to claim 3, characterised in that said control circuit (10) includes an additional high-voltage MOSFET transistor (3*) including drain, source and gate terminals, said additional high-voltage MOSFET transistor (3*) forming, with said first high-voltage MOSFET transistor (3), a current mirror, the drain and gate terminals of the additional high-voltage MOSFET transistor (3*) being connected together to the gate terminal of the first high-voltage MOSFET transistor (3) and the source terminal of the additional high-voltage MOSFET transistor (3*) being connected to ground (VSS).
  5. Regulator circuit according to any one of the preceding claims, characterised in that said high-voltage MOSFET transistor or transistors (3; 3*; 102) are n-channel MOSFET transistors including a gate oxide having a greater thickness on the drain side than on the source side and a buffer zone on the drain side formed by an n-well.
  6. Regulator circuit according to any one of the preceding claims, characterised in that the voltage divider circuit or circuits (5, 105) are resistive divider circuits.
  7. Regulator circuit according to any one of claims 1 to 6, characterised in that said regulation device (2) is a JFET transistor including drain, source and gate terminals respectively forming the input, output and control terminals of said regulation device,
       and in that said control circuit (10) further includes a resistive element (30) connected between the control (23) and output (22) terminals of said regulation device (2).
  8. Regulator circuit according to any one of claims 1 to 6, characterised in that said regulation device (2) includes a Darlington or pseudo-Darlington circuit with two bipolar transistors (B1, B2).
  9. Regulator circuit according to claim 8, characterised in that said regulation device (2) includes a pnp bipolar transistor (B1) and an npn bipolar transistor (B2) arranged in a pseudo-Darlington circuit,
       the base and the collector of the pnp bipolar transistor (B1) being respectively connected to the collector and the emitter of the npn bipolar transistor (B2),
       the emitter of the pnp bipolar transistor (B1), the collector of the pnp bipolar transistor (B1) and the base of the npn bipolar transistor (B2) respectively forming the input, output and control terminals of said regulation device,
       a resistor (25) further being connected between the emitter of the pnp bipolar transistor (B1) and the base of the npn bipolar transistor (B2).
EP01202429A 2001-06-25 2001-06-25 High-voltage regulator with external control Expired - Lifetime EP1271440B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE60115408T DE60115408T2 (en) 2001-06-25 2001-06-25 High voltage regulator with external control
AT01202429T ATE311644T1 (en) 2001-06-25 2001-06-25 HIGH VOLTAGE REGULATOR WITH EXTERNAL CONTROL
EP01202429A EP1271440B1 (en) 2001-06-25 2001-06-25 High-voltage regulator with external control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP01202429A EP1271440B1 (en) 2001-06-25 2001-06-25 High-voltage regulator with external control

Publications (2)

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EP1271440A1 EP1271440A1 (en) 2003-01-02
EP1271440B1 true EP1271440B1 (en) 2005-11-30

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EP01202429A Expired - Lifetime EP1271440B1 (en) 2001-06-25 2001-06-25 High-voltage regulator with external control

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EP (1) EP1271440B1 (en)
AT (1) ATE311644T1 (en)
DE (1) DE60115408T2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3011146B1 (en) 2013-09-23 2015-10-23 Commissariat Energie Atomique CHARGE PUMP CIRCUIT FOR GENERATING NEGATIVE VOLTAGE

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3611335A (en) * 1968-11-13 1971-10-05 Bbk Electronics Inc Multiple combustion sensing device with false alarm prevention
US3913082A (en) * 1973-02-02 1975-10-14 Jenson Robert S Ionization aerosol detector
JPH0715410B2 (en) * 1987-03-06 1995-02-22 能美防災株式会社 Radiant fire detector

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"Unitrode Integrated Circuits - Product and Applications Handbook", 1995, UNITRODE INTEGRATED CIRCUITS CORPORATION, MERRIMACK, NH *
MURARI B. ET AL: "Smart Power ICs - Technologies and Applications", 1996, SPRINGER VERLAG, BERLIN *

Also Published As

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DE60115408D1 (en) 2006-01-05
ATE311644T1 (en) 2005-12-15
EP1271440A1 (en) 2003-01-02
DE60115408T2 (en) 2006-08-24

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