EP0649079B1 - Regulated voltage generating circuit of bandgap type - Google Patents

Regulated voltage generating circuit of bandgap type Download PDF

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Publication number
EP0649079B1
EP0649079B1 EP94202878A EP94202878A EP0649079B1 EP 0649079 B1 EP0649079 B1 EP 0649079B1 EP 94202878 A EP94202878 A EP 94202878A EP 94202878 A EP94202878 A EP 94202878A EP 0649079 B1 EP0649079 B1 EP 0649079B1
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EP
European Patent Office
Prior art keywords
transistor
transistors
emitter
circuit
supply terminal
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EP94202878A
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German (de)
French (fr)
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EP0649079A1 (en
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Timothy Ridgers
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Philips Composants et Semiconducteurs SAS
Koninklijke Philips NV
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Philips Composants et Semiconducteurs SAS
Koninklijke Philips Electronics NV
Philips Electronics NV
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

  • the present invention relates to a generator circuit stabilized voltage comprising a cell of the so-called "bandgap" type, in which a plurality of transistors connected in parallel forms a set equivalent to a first transistor, of a first polarity, whose transmitter is connected to one end of a first resistor emitter, the other end of this resistor being connected by elsewhere at the emitter of a second transistor, of the same polarity, of emitter area equal to that of one of the transistors forming the first transistor, second transistor whose base is connected to that of the first transistor, the node joining the emitter of the second transistor at the first emitter resistor being coupled to a first supply terminal through a second resistor transmitter, circuit further comprising an amplifier acting on the base of the first and second transistors to ensure equality of currents flowing through the first and second respectively transistors, which transistors have their collector powered at from a second supply terminal.
  • a stabilized voltage generator circuit is notably known from document EP-A-0 465 094.
  • Voltage generator circuits independent of variations in temperature and supply voltage are very often necessary for the realization of integrated devices modern.
  • voltage generator circuits of the "bandgap" type require a supply voltage which is above 3 direct junction voltages (3.V BE ) and even 4.V BE .
  • the object of the invention is therefore to propose a generator circuit of the "bandgap" type capable of operating under a supply voltage which hardly exceeds the stabilized voltage generated, (which is usually of the order of 2.V BE , ie ⁇ 1.2 V), a circuit which could nevertheless have stability performance at least as high as the known circuits operating under a supply voltage of 5 Volts.
  • V BE a voltage which is partly related to the drop of voltage provided in the first, second and third current source, and on the other hand, in relation to the voltage supplied by the circuit with determined voltage drop.
  • the known circuit of the prior art cited above comprises a starting device consisting of 4 junctions and a field effect transistor taking the place of a resistance of high value, the whole arranged in series between the power terminals.
  • this known circuit requires a supply voltage which must be greater than 4.V BE .
  • the circuit according to the invention can be supplied with a voltage of only 2 volts, if desired.
  • the circuit according to the invention has a large number of operating elements symmetrically which ensures high error compensation residual, so this circuit has an output voltage high stability against temperature differences as well only deviations from the supply voltage.
  • the circuit according to the invention also has the peculiarity to enter into operation as soon as the voltage power is applied to it.
  • the switch device can be presented in various forms, the simplest being essentially reduced to a transistor with field effect from which the control electrode receives a signal appropriate command.
  • each of the transistors of the current mirror having its transmitter coupled to the first terminal supply by means of a value transmitter resistor determined, another resistance whose value is equal to half of said determined value pairs the transmitter of the error amplifier transistor at the same first terminal feed.
  • the first and second current sources are reduced to resistances of equal value collector, while the third source of current is constituted by another resistance, of value half of the value of one of these collector resistors.
  • a voltage generator circuit comprises a cell 1 of the "bandgap" type as well as an amplifier 2 delivering a reference voltage Vref.
  • the cell 1 comprises a first transistor T 1 and a second transistor T 2 , the transistor T 1 having an emitter surface m times larger than the emitter surface of the second transistor T 2 .
  • the transistor T 1 is preferably made up of m individual transistors connected in parallel, which gives greater precision than the constitution of a single transistor T 1 . In what follows, the transistor T 1 , whatever its constitution will be considered as a single transistor.
  • the emitter is connected to a first end of a first emitter resistor 12, the other end of this resistor being connected on the one hand to the emitter of the second transistor T 2 and on the other hand a first terminal of power supply 9 (ground) through a second emitter resistor 13.
  • the bases of the transistors T 1 and T 2 are connected to each other.
  • the collectors of the transistors T 1 and T 2 are supplied from a second supply terminal 8 through respectively a first collector resistor 14, 15 and a second collector resistor 16, 17, these resistors taking the place of sources of current paired.
  • said resistances of collector each formed of two equal resistance parts, in series. Also for a technological reason, it will be necessary to have of another resistance whose value is equal to one of these four resistance parts.
  • Amplifier 2 includes an input stage provided with a pair of PNP type transistors T 3 , T 4 , the emitters of equivalent area, are respectively connected to the collector of the first and second transistors T 1 , T 2 .
  • the bases of the transistors T 3 and T 4 are connected to each other and coupled to the first supply terminal 9 through a circuit 7 ensuring a determined voltage drop, close to or slightly higher than a voltage drop of one direct polarized junction.
  • the collector of transistor T 4 is connected to the input of a current mirror M formed of NPN transistors T 5 and T 6 , the transistor T 5 being connected as a diode while the collector of transistor T 3 is connected to the collector of transistor T 6 , this node constituting the output of the current mirror.
  • the emitters of transistors T 5 and T 6 are coupled to the first supply terminal 9 through resistors equal to resistors 25 and 26 respectively.
  • the amplifier 2 finally comprises an output stage essentially constituted by a transistor called an error amplifier T 56 of the NPN type, a so-called bias transistor T 34 of the PNP type and a so-called compensation transistor T 22 , NPN type.
  • Each of the transistors constituting the output stage has been represented as formed by two transistors connected in parallel, this for the same technological reasons already mentioned above, that is to say that the transistor T 56 has an emitter surface equivalent to all of the emitter surfaces of transistors T 5 and T 6 , that transistor T 34 has an emitter surface equivalent to all of the emitter surfaces of transistors T 3 and T 4 and that transistor T 22 has an emitter area equivalent to twice the emitter area of transistor T 2 . Subsequently, these transistors will be considered as single transistors even if they are formed by two half surface transistors, connected in parallel.
  • the node joining the collectors of the transistors T 3 and T 6 , constituting the output of the input stage, is connected to the base of the error amplifier transistor T 56 .
  • the node connecting the bases of the pair of transistors T 3 and T 4 is connected to the base of the bias transistor T 34 and the collectors of the transistors T 34 and T 56 are connected to the node 117 connecting the bases of the transistors T 1 and T 2 , node which on the one hand is connected to the output terminal 18 of the amplifier and on the other hand is connected to the base of the compensation transistor T 22 .
  • the node connecting the emitter of the bias transistor T 34 to the collector of the compensation transistor T 22 is coupled to the second power supply terminal 8 via a resistor 35 whose value is equal to one of the resistors 14-17, again half the value of the first collector resistor 14, 15 or half of its equivalent, the second collector resistor 16, 17.
  • Resistor 35 thus achieves a simplified current source delivering a current of value twice the current flowing through resistors 14, 15 (or 16.17).
  • the error amplifying transistor T 56 has its emitter coupled to the first supply terminal 9 via two emitter resistors in parallel 45, 46 which are equal to each other and each equal to one of the emitter resistors 25 or 26 of transistors T 5 and T 6 .
  • the emitter of the compensation transistor T 22 is coupled to the first supply terminal 9 via a resistor 43 whose value is equal to the second emitter resistor 13 of the cell 1.
  • a capacitor 19 of low and non-critical value can be connected in parallel between the node 117 and the base of the error amplifier transistor T 56 so as to ensure better stability of the generator circuit, at high frequency.
  • said second terminal 8 can be connected to the positive power source Vcc.
  • the circuit stabilized voltage generator can be switched on or off operation by means of a switch device 11 arranged in series between the power source itself 10 brought to the positive potential Vcc and the conductor which was called second terminal supply 8.
  • a current I S is firstly divided into two portions I 1 and I 2 as a function of the collector resistors 14, 15 on the one hand and 16, 17 d 'somewhere else.
  • the current I 1 is in turn divided on the one hand into a current I A entering the emitter of the transistor T 3 and a current I pt entering the collector of the transistor T 1 .
  • the current I 2 is in turn divided into a current I B entering the emitter of transistor T 4 and a current I pt entering the collector of transistor T 2 .
  • the cell is supplied in such a way that the collector currents of transistor T 1 and of transistor T 2 are equal to each other.
  • the difference between the current between I A and I B appears at the output of the input stage of the amplifier namely on the node connecting the collectors of the transistors T 3 and T 6 current difference which is applied to the base of transistor T 56 .
  • the collector current of transistor T 56 which is an amplified error current, is applied to node 117 joining the bases of transistors T 1 , T 2 , T 22 and provides a feedback setting the voltage of this node so that the currents I pt passing through the transistors T 1 and T 2 are equal. Since the bases of the transistors T 3 and T 4 are connected together, and the resistors 14, 15 - 16, 17 are equal to each other, the currents I A and I B are substantially equal.
  • the compensation transistor T 22 has an emitter surface twice that of the transistor T 2 . Its emitter is connected to an emitter resistance 43 of value equal to the second emitter resistance 13 of cell 1, which is crossed by a current equal to 2.I pt . Also, the transistor T 22 also outputs it, a current very substantially equal to 2.I pt . As the resistor 35 is chosen to have a value equal to one of the resistors 14-17 and the bias transistor T 34 is chosen with an emitter surface twice that of one of the transistors T 3 or T 4 , it follows that the current entering the emitter of transistor T 34 is very substantially equal to 2.I A. Thus, another current with a value I s flows from the supply terminal 8 into the resistor 35.
  • I e (T 2 ) emitter current of transistor T 2
  • I e (T 2 ) (V T / R 12 ) .
  • the current I e (T 2 ) is therefore a current proportional to the absolute temperature and the collector current of the same transistor, denoted I pt is also a current of the same property whose value is very close to I e (T 2 ).
  • the compensation transistor T 22 in parallel on the transistor T 2 , is arranged to debit a current equal to 2.I pt by noting that this transistor T 22 has its base connected to the base of the transistor T 2 and its collector subjected to a voltage which is identical to the collector voltage of transistor T 2 , since the current I s passing through the resistor 35 is very substantially equal to the current I s , sum of the currents passing through the collector resistors 14, 15 and 16, 17.
  • V (7) + V BE (T 34 ) + R 35 .I s expression in which V (7) is the voltage drop in circuit 7, V BE (T 34 ) is the emitter-base voltage of transistor T 34 , and R 35 is the value of the resistor 35.
  • the voltage drop in the resistor 35 can be chosen to be relatively low, less than 1 V BE for example, but more than several V T.
  • the minimum supply voltage can be a little more than 2.V BE and less, 3V BE if necessary.
  • Vcc voltage of this source
  • the voltage of this source can be equal to the previously defined voltage or a little higher if one chooses a switch device 11 having its own internal resistance.
  • PNP transistors T 3 , T 4 , T 34 operate with an identical emitter / base voltage and an identical current density.
  • the NPN transistors T 1 , T 2 , T 22 operate at the same collector / base voltage and, moreover, the transistors T 2 and T 22 operate with the same current density and the same V BE .
  • the transistors T 5 and T 6 operate at all identical current conditions since the collector of transistor T 6 is connected to the base of transistor T 56 operating symmetrically with all the transistors T 5 and T 6 , while the transistor T 5 has its collector connected to its base. This reproduces a total operating symmetry for the transistors T 5 , T 6 .
  • transistors T 3 and T 4 operate at identical collector voltage.
  • the output voltage Vref It is only at node 117, carrying the output voltage Vref, that there is a difference with respect to the base voltage of the transistors T 5 and T 6 . Indeed, the value of Vref is of the order of 1.25 Volts, independent of the supply voltage.
  • the base / collector voltage of the transistors T 3 and T 4 is generally different from the base / collector voltage of the transistor T 34 although it is easy to provide a voltage equality for a nominal value of the voltage of food.
  • collector current of transistor T 34 should be a little lower or higher than the sum of the collector currents of transistors T 3 and T 4 , depending on whether the voltage drop in resistors 25 and 26 has been chosen lower or higher than the voltage drop of circuit 7, and / or that the supply voltage deviates from its nominal value.
  • the cascode type configuration of all the PNP transistors has the effect of multiplying the output resistance of these transistors and this especially when adopting a relatively high voltage drop in resistors 35, 14-17 is that is to say clearly greater than V T.
  • FIGS. 2A, 2B and 2C show exemplary embodiments of the block 7 of FIG. 1 ensuring a determined voltage drop, close to that of a direct polarized junction or slightly higher.
  • the value of this voltage drop is chosen mainly as a function of the nominal voltage provided on the second supply terminal 8 and of the voltage drops in the resistors 25, 26, 45, 46.
  • a preferred value is chosen to ensure, at the nominal supply voltage, an approximate equality between the voltage V ref of the node 117 and the voltage of the collectors of the transistors T 3 and T 4 .
  • the generator circuit then operates optimally with a very high degree of symmetry eliminating most of the causes of second order errors.
  • the circuit 7 is reduced to a bipolar transistor T 7 connected as a diode and directly biased.
  • the bipolar transistor T 7 can be replaced by an N-channel MOS type transistor, connected in an equivalent manner, so as to have a voltage drop corresponding to its threshold voltage. A voltage drop slightly higher than a V BE is then obtained, whose temperature behavior is advantageous for the operation of the generator circuit.
  • the circuit 7 is in the form of a circuit, known per se, in which a resistance bridge 71, 72 connects in parallel with the collector-emitter path of an NPN T 70 transistor whose base is connected to the intermediate point of this resistance bridge.
  • This arrangement provides a voltage drop proportional to a V BE , the proportionality factor, greater than 1, being chosen at will according to the values of resistors 71 and 72.
  • FIG. 2C provides yet another mounting example usable for the circuit 7 of FIG. 1, which is reduced here to a resistor bridge 73, 74 connected between the second power supply terminal 8 (or the power source Vcc) and the mass (terminal 9).
  • the voltage drop used to flow the base current of the transistors T 3 , T 4 , and T 34 is that occurring at the terminals of the resistor 74. Admittedly, this voltage drop is affected by variations in supply voltage, but this is favorable since the variation in voltage across the resistor 74 occurs in the same direction as the variation in the emitter voltage of the transistors T 3 and T 4 .
  • the variation of the currents I A and I B as a function of the variations of the supply voltage Vcc is reduced.
  • circuit 7 will be chosen which provides a lower voltage drop, the closer to 1 V BE , the lower the minimum supply voltage is desired.
  • FIG. 3 represents an exemplary embodiment of the switch 11 of FIG. 1. It essentially consists of a P-channel field effect transistor T 20 , with enrichment, the source of which is connected to the power source 10 carrying the voltage Vcc, through a resistor 31, the drain of which is connected to terminal 8 called the second supply terminal.
  • the gate of this transistor T 20 receives via a terminal 30 a control signal placing the transistor either in conduction or out of conduction under the effect of a control voltage varying between the voltage of the ground and the voltage Vcc.
  • the resistor 31 in series with the source of the transistor T 20 , as well as of the internal resistance of this transistor.
  • FIG. 4 provides another exemplary embodiment of the switch device 11 of FIG. 1, an example in which a pre-regulation of the current (2.I s ) supplying the amplifier 2 of FIG. 1 is also ensured.
  • a field effect transistor T 40 of the MOS field effect type has its source connected to the first supply terminal 9, (ground). Its gate receives a suitable control signal from a control terminal 41. Its drain is coupled to the power source 10, at Vcc voltage, via a resistor 42 and a PNP type transistor T 43 connected as a diode.
  • Another PNP transistor, T 44 has its base connected to the base of transistor T 43 and its emitter, with an area n times larger than that of the emitter of transistor T 43 , coupled to source 10 via a resistor. emitter 47.
  • the collector of transistor T 44 supplies a current to terminal 8, called the second supply terminal, the value of which is determined for a nominal voltage Vcc, varies logarithmically, and therefore only slightly, when Vcc varies.
  • circuit of figure 4 is a equivalent to that of Figure 3 in which the source resistance 31 would have a value varying in the same direction as the value of Vcc, thus attenuating variations in the voltage produced on terminal 8.
  • FIG. 5 presents a variant of the circuit of FIG. 4 according to which it is a bipolar transistor T 50 , of PNP type, which replaces the transistor T 40 of FIG. 4, the collector of which is connected to terminal 9 (ground) , and the base of which receives an appropriate control signal from the control terminal 51.
  • the emitter of transistor T 50 is coupled to the power source 10 (Vcc) via a resistor 52 of high value and the base-emitter path of a PNP transistor, T 53 . Between the resistor 52 and the collector of this transistor T 53 is inserted a resistor 54, the value of which is chosen to create a voltage drop close to V T under the nominal operating conditions.
  • the collector of transistor T 53 is connected to the base of another PNP transistor, T 55 , whose emitter, with an area n times larger than that of the emitter of transistor T 53 , is connected to the source of food 10.
  • the collector of transistor T 55 delivers a preset current at terminal 8, the value of which varies little as a function of variations in Vcc around its nominal value, as in the previous example.
  • the circuit of FIG. 4 uses a transistor T 40 of the MOS type for the power interruption function while the circuit of FIG. 5 shows a bipolar transistor T 50 to perform the same function.
  • transistor T 40 of the MOS type for the power interruption function
  • FIG. 5 shows a bipolar transistor T 50 to perform the same function.
  • the specialist will easily recognize that the use of these types of transistors could have been exchanged and that they are in no way specific to each of the examples described, where an NPN type transistor could also have been used easily.

Description

La présente invention concerne un circuit générateur de tension stabilisée comportant une cellule du type dit "bandgap", dans laquelle une pluralité de transistors connectés en parallèle forme un ensemble équivalent à un premier transistor, d'une première polarité, dont l'émetteur est connecté à une extrémité d'une première résistance d'émetteur, l'autre extrémité de cette résistance étant connectée par ailleurs à l'émetteur d'un deuxième transistor, de même polarité, de surface d'émetteur égale à celle de l'un des transistors formant le premier transistor, deuxième transistor dont la base est reliée à celle du premier transistor, le noeud joignant l'émetteur du deuxième transistor à la première résistance d' émetteur étant couplé à une première borne d'alimentation à travers une deuxième résistance d'émetteur, circuit comportant en outre un amplificateur agissant sur la base des premier et deuxième transistors pour assurer l'égalité des courants qui traversent respectivement les premier et le deuxième transistors, lesquels transistors ont leur collecteur alimenté à partir d'une deuxième borne d'alimentation.The present invention relates to a generator circuit stabilized voltage comprising a cell of the so-called "bandgap" type, in which a plurality of transistors connected in parallel forms a set equivalent to a first transistor, of a first polarity, whose transmitter is connected to one end of a first resistor emitter, the other end of this resistor being connected by elsewhere at the emitter of a second transistor, of the same polarity, of emitter area equal to that of one of the transistors forming the first transistor, second transistor whose base is connected to that of the first transistor, the node joining the emitter of the second transistor at the first emitter resistor being coupled to a first supply terminal through a second resistor transmitter, circuit further comprising an amplifier acting on the base of the first and second transistors to ensure equality of currents flowing through the first and second respectively transistors, which transistors have their collector powered at from a second supply terminal.

Un circuit générateur de tension stabilisée, est notamment connu du document EP-A-0 465 094.A stabilized voltage generator circuit is notably known from document EP-A-0 465 094.

Les circuits générateurs de tension indépendante des variations de la température et de la tension d'alimentation sont très souvent nécessaires pour la réalisation de dispositifs intégrés modernes.Voltage generator circuits independent of variations in temperature and supply voltage are very often necessary for the realization of integrated devices modern.

Le principe de circuit du type dit "bandgap", basé sur une configuration de deux transistors parcourus par un courant égal mais ayant un rapport de surface d'émetteur différent de 1, créant une différence de densité de courant dans ces transistors et une différence de tension émetteur-base corrélative est maintenant largement utilisé en raison de ses excellentes performances.The principle of a "bandgap" type circuit, based on a configuration of two transistors traversed by an equal current but having an emitter area ratio other than 1, creating a difference in current density in these transistors and a correlative emitter-base voltage difference is now widely used due to its excellent performance.

En raison principalement d'un nombre d'applications pour appareils portatifs fonctionnant sur piles, on observe actuellement une tendance à spécifier que les circuits correspondants puissent fonctionner sous une tension d'alimentation réduite, notamment sous 3 Volts au lieu de 5 Volts qui était la norme habituelle auparavant. Dans ces conditions, certaines configurations de circuits ne conviennent plus et doivent être modifiées pour accepter une alimentation à faible tension.Mainly due to a number of applications for portable devices operating on batteries, we currently observe a tendency to specify that the corresponding circuits can operate under reduced supply voltage, especially under 3 Volts instead of 5 Volts which was the usual norm before. Under these conditions, certain circuit configurations do not are more suitable and must be changed to accept a low voltage power supply.

En général, les circuits générateurs de tension du type "bandgap" requièrent une tension d'alimentation qui se situe au dessus de 3 tensions de jonction en direct (3.VBE) et même 4.VBE.In general, voltage generator circuits of the "bandgap" type require a supply voltage which is above 3 direct junction voltages (3.V BE ) and even 4.V BE .

L'invention a donc pour but de proposer un circuit générateur de type "bandgap" susceptible de fonctionner sous une tension d'alimentation qui dépasse peu la tension stabilisée générée, (laquelle est habituellement de l'ordre de 2.VBE, soit ≈ 1,2 V), circuit qui pourrait néanmoins présenter des performances de stabilité au moins aussi élevée que les circuit connus fonctionnant sous une tension d'alimentation de 5 Volts.The object of the invention is therefore to propose a generator circuit of the "bandgap" type capable of operating under a supply voltage which hardly exceeds the stabilized voltage generated, (which is usually of the order of 2.V BE , ie ≈ 1.2 V), a circuit which could nevertheless have stability performance at least as high as the known circuits operating under a supply voltage of 5 Volts.

A cet effet, un circuit générateur de tension stabilisée conforme au paragraphe introductif est, selon l'invention, caractérisé en ce que le collecteur de chacun des premier et deuxième transistors est relié à la deuxième borne d'alimentation respectivement par une première et une deuxième source de courant délivrant un courant de même valeur,

  • en ce que l'amplificateur comporte un étage d'entrée muni de deux transistors, de polarité opposée à celle des premier et deuxième transistors, dont les émetteurs de surface équivalente, sont respectivement connectés aux collecteurs des premier et deuxième transistors, dont les bases sont connectées entre elles et couplées à la première borne d'alimentation à travers un circuit à chute de tension déterminée, et dont les collecteurs sont respectivement connectés à l'entrée et à la sortie d'un miroir de courant, de rapport unité, composé de transistors de ladite première polarité et dont les émetteurs sont couplés à la première borne d'alimentation,
  • en ce que l'amplificateur comporte un étage de sortie essentiellement constitué d'un transistor dit amplificateur d'erreur, de la première polarité, d'un transistor dit de polarisation, de la deuxième polarité ainsi que d'un transistor dit de compensation, de la première polarité,
  • en ce que le transistor amplificateur d'erreur a une surface d'émetteur double de celle de chacun des transistors composant le miroir de courant, a sa base connectée à la sortie du miroir de courant, son émetteur couplé à la première borne d'alimentation, son collecteur connecté au noeud reliant les bases des premier et deuxième transistors, noeud constituant également la sortie de l'amplificateur et fournit la tension stabilisée de sortie du circuit,
  • en ce que le transistor de polarisation a une surface d'émetteur équivalente à celle de l'ensemble des deux transistors de l'étage d'entrée, a son émetteur relié à la deuxième borne d'alimentation à travers une troisième source de courant délivrant un courant dont la valeur est égale à la somme des courants des première et deuxième sources de courant, a sa base connectée aux bases des deux transistors de l'étage d'entrée, et son collecteur connecté au noeud de sortie,
  • et en ce que le transistor de compensation a une surface d'émetteur double de celle du deuxième transistor, a sa base connectée au noeud de sortie, son émetteur relié à la première borne d'alimentation à travers une résistance de valeur égale à celle de la deuxième résistance d'émetteur de la cellule, et son collecteur, connecté à l'émetteur du transistor de polarisation.
    • To this end, a stabilized voltage generator circuit in accordance with the introductory paragraph is, according to the invention, characterized in that the collector of each of the first and second transistors is connected to the second supply terminal respectively by a first and a second current source delivering a current of the same value,
  • in that the amplifier comprises an input stage provided with two transistors, of opposite polarity to that of the first and second transistors, whose emitters of equivalent area, are respectively connected to the collectors of the first and second transistors, the bases of which are connected to each other and coupled to the first supply terminal through a circuit with a determined voltage drop, and the collectors of which are respectively connected to the input and to the output of a current mirror, of unit ratio, composed of transistors of said first polarity and whose emitters are coupled to the first supply terminal,
  • in that the amplifier comprises an output stage essentially consisting of a transistor known as an error amplifier, of the first polarity, of a so-called bias transistor, of the second polarity as well as of a so-called compensation transistor, of the first polarity,
  • in that the error amplifying transistor has an emitter surface twice that of each of the transistors making up the current mirror, at its base connected to the output of the current mirror, its emitter coupled to the first supply terminal , its collector connected to the node connecting the bases of the first and second transistors, node also constituting the output of the amplifier and provides the stabilized output voltage of the circuit,
  • in that the bias transistor has an emitter surface equivalent to that of all of the two transistors of the input stage, has its emitter connected to the second supply terminal through a third current source delivering a current whose value is equal to the sum of the currents of the first and second current sources, at its base connected to the bases of the two transistors of the input stage, and its collector connected to the output node,
  • and in that the compensation transistor has an emitter area twice that of the second transistor, its base connected to the output node, its emitter connected to the first supply terminal through a resistor of value equal to that of the second emitter resistance of the cell, and its collector, connected to the emitter of the bias transistor.

    • Par une analyse rapide de ce circuit, il est facile de constater qu'il est susceptible d'entrer en fonction pour une tension d'alimentation à peine supérieure à 2.VBE, tension qui est en rapport d'une part avec la chute de tension prévue dans les première, deuxième et troisième source de courant, et d'autre part, en rapport avec la tension fournie par le circuit à chute de tension déterminée.By a quick analysis of this circuit, it is easy to see that it is likely to come into operation for a supply voltage just above 2.V BE , a voltage which is partly related to the drop of voltage provided in the first, second and third current source, and on the other hand, in relation to the voltage supplied by the circuit with determined voltage drop.

    On notera à ce propos que le circuit connu de l'art antérieur cité plus haut comporte un dispositif de démarrage constitué de 4 jonctions et d'un transistor à effet de champ tenant lieu de résistance de valeur élevée, le tout disposé en série entre les bornes d'alimentation. Ainsi, ce circuit connu exige une tension d'alimentation qui doit être supérieure à 4.VBE.It will be noted in this connection that the known circuit of the prior art cited above comprises a starting device consisting of 4 junctions and a field effect transistor taking the place of a resistance of high value, the whole arranged in series between the power terminals. Thus, this known circuit requires a supply voltage which must be greater than 4.V BE .

    En pratique, le circuit selon l'invention peut être alimenté sous une tension de 2 Volts seulement, si on le désire.In practice, the circuit according to the invention can be supplied with a voltage of only 2 volts, if desired.

    Comme il sera précisé plus loin, en détail, le circuit selon l'invention présente un nombre important d'éléments fonctionnant symétriquement ce qui assure une compensation élevée des erreurs résiduelles, de sorte que ce circuit présente une tension de sortie d'une haute stabilité vis-à-vis des écarts de température aussi bien que des écarts de la tension d'alimentation.As will be specified below, in detail, the circuit according to the invention has a large number of operating elements symmetrically which ensures high error compensation residual, so this circuit has an output voltage high stability against temperature differences as well only deviations from the supply voltage.

    Le circuit selon l'invention présente également la particularité d'entrer en fonctionnement dès que la tension d'alimentation lui est appliquée.The circuit according to the invention also has the peculiarity to enter into operation as soon as the voltage power is applied to it.

    Il offre donc l'avantage qu'un dispositif de démarrage n'est pas nécessaire et que le circuit selon l'invention est, de ce point de vue, plus simple et plus compact.It therefore offers the advantage that a starting device is not necessary and that the circuit according to the invention is, from this point of view, simpler and more compact.

    Par ailleurs, sa vitesse propre de mise en ou hors service peut être mise à profit lorsque la tension stabilisée de sortie n'est requise que par intermittence dans l'application, de sorte qu'entre temps, la consommation du circuit peut être économisée. Ce type de fonctionnement intermittent est souhaitable, par exemple, pour la partie radio d'un appareil de téléphone portatif. Cet avantage est obtenu par une mise en oeuvre de l'invention qui est caractérisée en ce que ladite deuxième borne d'alimentation est reliée à une source d'alimentation via un dispositif interrupteur de mise en ou hors fonction du circuit générateur de tension.Furthermore, its own speed of switching on or off can be used when the stabilized output voltage is not required only intermittently in the app, so that between time, circuit consumption can be saved. This kind of intermittent operation is desirable, for example, for the radio part of a portable telephone device. This advantage is obtained by an implementation of the invention which is characterized in that said second supply terminal is connected to a source supply via an on or off switch device function of the voltage generator circuit.

    Le dispositif interrupteur peut se présenter sous diverses formes, la plus simple étant réduite essentiellement à un transistor à effet de champ dont l' électrode de commande reçoit un signal de commande approprié.The switch device can be presented in various forms, the simplest being essentially reduced to a transistor with field effect from which the control electrode receives a signal appropriate command.

    Selon un mode préféré de mise en oeuvre du circuit selon l'invention, celui-ci est caractérisé en ce que chacun des transistors du miroir de courant ayant son émetteur couplé à la première borne d'alimentation au moyen d'une résistance d'émetteur de valeur déterminée, une autre résistance dont la valeur est égale à la moitié de ladite valeur déterminée effectue le couplage de l'émetteur du transistor amplificateur d'erreur à la même première borne d'alimentation.According to a preferred embodiment of the circuit according to the invention, it is characterized in that each of the transistors of the current mirror having its transmitter coupled to the first terminal supply by means of a value transmitter resistor determined, another resistance whose value is equal to half of said determined value pairs the transmitter of the error amplifier transistor at the same first terminal feed.

    Même en adoptant une chute de tension assez faible dans les résistances en question, par exemple nominalement 0,3Volt, on accroít la précision de l'égalité entre les courants d'entrée et de sortie du miroir de courant et celle d'un courant, de valeur double, délivré par le transistor amplificateur d'erreur.Even by adopting a fairly small voltage drop in the resistors in question, for example nominally 0.3Volt, we increases the accuracy of the equality between the input currents and output of the current mirror and that of a current, of double value, delivered by the error amplifier transistor.

    Dans un mode de réalisation simplifié, avantageux lorsqu'une faible tension d'alimentation est requise, les première et deuxième sources de courant se réduisent à des résistances de collecteur de valeurs égales, tandis que la troisième source de courant est constituée par une autre résistance, de valeur moitié de la valeur de l'une de ces résistances de collecteur. In a simplified embodiment, advantageous when a low supply voltage is required, the first and second current sources are reduced to resistances of equal value collector, while the third source of current is constituted by another resistance, of value half of the value of one of these collector resistors.

    L'invention sera mieux comprise à l'aide de la description qui va suivre en regard des dessins annexés, relative à des exemples de réalisation donnés à titre non limitatifs.

  • La figure 1 présente le schéma électrique d'un exemple de réalisation du circuit selon l'invention,
  • les figures 2A à 2C présentent des schémas de différents exemples de montages possibles pour réaliser le circuit dit à chute de tension déterminée, faisant partie du circuit générateur de la figure 1,
  • la figure 3 montre un premier exemple de réalisation pratique d'un dispositif interrupteur tel qu'il a été représenté sous forme de bloc, à la figure 1,
  • la figure 4 donne un deuxième exemple de réalisation de ce dispositif interrupteur, au moyen duquel est également réalisée une pré-régulation du courant d'alimentation du régulateur de tension, et
  • la figure 5 donne le schéma d'un troisième exemple de dispositif interrupteur avec pré-régulation du courant d'alimentation.
    • The invention will be better understood with the aid of the description which follows with reference to the appended drawings, relating to exemplary embodiments given without limitation.
  • FIG. 1 shows the electrical diagram of an exemplary embodiment of the circuit according to the invention,
  • FIGS. 2A to 2C present diagrams of different examples of possible arrangements for producing the circuit known as a determined voltage drop, forming part of the generator circuit of FIG. 1,
  • FIG. 3 shows a first practical example of a switch device as shown in the form of a block, in FIG. 1,
  • FIG. 4 gives a second embodiment of this switch device, by means of which a pre-regulation of the supply current of the voltage regulator is also carried out, and
  • FIG. 5 gives the diagram of a third example of a switching device with pre-regulation of the supply current.

    • Conformément à la figure 1, un circuit générateur de tension selon l'invention comporte une cellule 1 du type "bandgap" ainsi qu'un amplificateur 2 délivrant une tension de référence Vref. Sur la figure ces deux parties sont séparées par une ligne verticale en traits mixtes. La cellule 1 comporte un premier transistor T1 et un deuxième transistor T2, le transistor T1 ayant une surface d'émetteur m fois plus grande que la surface d'émetteur du deuxième transistor T2. Ainsi qu'il est bien connu des spécialistes, le transistor T1 est de préférence constitué de m transistors individuels connectés en parallèle, ce qui donne une précision plus grande que la constitution d'un seul transistor T1. Dans ce qui suit, le transistor T1, quelle que soit sa constitution sera considéré comme un transistor unique. Son émetteur est connecté à une première extrémité d'une première résistance d'émetteur 12, l'autre extrémité de cette résistance étant connectée d'une part à l'émetteur du deuxième transistor T2 et d'autre part une première borne d'alimentation 9 (masse) à travers une deuxième résistance d'émetteur 13. Les bases des transistors T1 et T2 sont connectées entre elles. Les collecteurs des transistors T1 et T2 sont alimentés à partir d'une deuxième borne d'alimentation 8 à travers respectivement une première résistance de collecteur 14, 15 et une deuxième résistance de collecteur 16, 17, ces résistances tenant lieu de sources de courant appairées.In accordance with FIG. 1, a voltage generator circuit according to the invention comprises a cell 1 of the "bandgap" type as well as an amplifier 2 delivering a reference voltage Vref. In the figure these two parts are separated by a vertical line in dashed lines. The cell 1 comprises a first transistor T 1 and a second transistor T 2 , the transistor T 1 having an emitter surface m times larger than the emitter surface of the second transistor T 2 . As is well known to specialists, the transistor T 1 is preferably made up of m individual transistors connected in parallel, which gives greater precision than the constitution of a single transistor T 1 . In what follows, the transistor T 1 , whatever its constitution will be considered as a single transistor. Its emitter is connected to a first end of a first emitter resistor 12, the other end of this resistor being connected on the one hand to the emitter of the second transistor T 2 and on the other hand a first terminal of power supply 9 (ground) through a second emitter resistor 13. The bases of the transistors T 1 and T 2 are connected to each other. The collectors of the transistors T 1 and T 2 are supplied from a second supply terminal 8 through respectively a first collector resistor 14, 15 and a second collector resistor 16, 17, these resistors taking the place of sources of current paired.

    Sur la figure on a représenté lesdites résistances de collecteur formées chacune de deux parties de résistance égales, en série. Egalement pour une raison technologique, il faudra disposer d'une autre résistance dont la valeur soit égale à l'une de ces quatre parties de résistance.In the figure, said resistances of collector each formed of two equal resistance parts, in series. Also for a technological reason, it will be necessary to have of another resistance whose value is equal to one of these four resistance parts.

    L'amplificateur 2 comporte un étage d'entrée muni d'une paire de transistors T3, T4 de type PNP dont les émetteurs de surface équivalente, sont respectivement connectés au collecteur des premier et deuxième transistors T1, T2. Les bases des transistors T3 et T4 sont connectées entre elles et couplées à la première borne d'alimentation 9 à travers un circuit 7 assurant une chute de tension déterminée, voisine ou un peu plus élevée qu'une chute de tension d'une jonction polarisée en direct. Le collecteur du transistor T4 est connecté à l'entrée d'un miroir de courant M formé de transistors NPN T5 et T6, le transistor T5 étant connecté en diode tandis que le collecteur du transistor T3 est connecté au collecteur du transistor T6, ce noeud constituant la sortie du miroir de courant. Dans une mise en oeuvre préférée, les émetteurs des transistors T5 et T6 sont couplés à la première borne d'alimentation 9 à travers des résistances égales respectivement les résistances 25 et 26.Amplifier 2 includes an input stage provided with a pair of PNP type transistors T 3 , T 4 , the emitters of equivalent area, are respectively connected to the collector of the first and second transistors T 1 , T 2 . The bases of the transistors T 3 and T 4 are connected to each other and coupled to the first supply terminal 9 through a circuit 7 ensuring a determined voltage drop, close to or slightly higher than a voltage drop of one direct polarized junction. The collector of transistor T 4 is connected to the input of a current mirror M formed of NPN transistors T 5 and T 6 , the transistor T 5 being connected as a diode while the collector of transistor T 3 is connected to the collector of transistor T 6 , this node constituting the output of the current mirror. In a preferred implementation, the emitters of transistors T 5 and T 6 are coupled to the first supply terminal 9 through resistors equal to resistors 25 and 26 respectively.

    L'amplificateur 2 comporte enfin un étage de sortie essentiellement constitué d'un transistor appelé amplificateur d'erreur T56 de type NPN, d'un transistor dit de polarisation T34 de type PNP et d'un transistor dit de compensation T22, de type NPN. Chacun des transistors constituant l'étage de sortie à été représenté comme formé de deux transistors connectés en parallèle, ceci pour les mêmes raisons technologiques déjà évoquées plus haut, c'est-à-dire que le transistor T56 a une surface d'émetteur équivalente à l'ensemble des surfaces d'émetteur des transistor T5 et T6, que le transistor T34 a une surface d'émetteur équivalente à l'ensemble des surface d'émetteur des transistors T3 et T4 et que le transistor T22 a une surface d'émetteur équivalente au double de la surface d'émetteur du transistor T2. Par la suite, ces transistors seront considérés comme transistors uniques même s'ils sont formés de deux transistors de surface moitié, connectés en parallèle. The amplifier 2 finally comprises an output stage essentially constituted by a transistor called an error amplifier T 56 of the NPN type, a so-called bias transistor T 34 of the PNP type and a so-called compensation transistor T 22 , NPN type. Each of the transistors constituting the output stage has been represented as formed by two transistors connected in parallel, this for the same technological reasons already mentioned above, that is to say that the transistor T 56 has an emitter surface equivalent to all of the emitter surfaces of transistors T 5 and T 6 , that transistor T 34 has an emitter surface equivalent to all of the emitter surfaces of transistors T 3 and T 4 and that transistor T 22 has an emitter area equivalent to twice the emitter area of transistor T 2 . Subsequently, these transistors will be considered as single transistors even if they are formed by two half surface transistors, connected in parallel.

    Le noeud joignant les collecteurs des transistors T3 et T6, constituant la sortie de l'étage d'entrée, est connecté à la base du transistor amplificateur d'erreur T56. Le noeud reliant les bases de la paire de transistors T3 et T4 est connecté à la base du transistor de polarisation T34 et les collecteurs des transistors T34 et T56 sont connectés au noeud 117 reliant les bases des transistors T1 et T2, noeud qui d'une part est relié à la borne de sortie 18 de l'amplificateur et d'autre part est connecté à la base du transistor de compensation T22.The node joining the collectors of the transistors T 3 and T 6 , constituting the output of the input stage, is connected to the base of the error amplifier transistor T 56 . The node connecting the bases of the pair of transistors T 3 and T 4 is connected to the base of the bias transistor T 34 and the collectors of the transistors T 34 and T 56 are connected to the node 117 connecting the bases of the transistors T 1 and T 2 , node which on the one hand is connected to the output terminal 18 of the amplifier and on the other hand is connected to the base of the compensation transistor T 22 .

    Le noeud reliant l'émetteur du transistor de polarisation T34 au collecteur du transistor de compensation T22 est couplé à la deuxième borne d'alimentation 8 via une résistance 35 dont la valeur est égale à l'une des résistance 14-17 soit encore la moitié de la valeur de la première résistance de collecteur 14, 15 ou la moitié de son équivalent, la deuxième résistance de collecteur 16, 17. La résistance 35 réalise ainsi une source de courant simplifiée délivrant un courant de valeur double du courant traversant les résistances 14, 15 (ou 16,17). Le transistor amplificateur d'erreur T56 a son émetteur couplé à la première borne d'alimentation 9 via deux résistances d'émetteur en parallèles 45, 46 lesquelles sont égales entre elles et chacune égale à l'une des résistance d'émetteur 25 ou 26 des transistors T5 et T6.The node connecting the emitter of the bias transistor T 34 to the collector of the compensation transistor T 22 is coupled to the second power supply terminal 8 via a resistor 35 whose value is equal to one of the resistors 14-17, again half the value of the first collector resistor 14, 15 or half of its equivalent, the second collector resistor 16, 17. Resistor 35 thus achieves a simplified current source delivering a current of value twice the current flowing through resistors 14, 15 (or 16.17). The error amplifying transistor T 56 has its emitter coupled to the first supply terminal 9 via two emitter resistors in parallel 45, 46 which are equal to each other and each equal to one of the emitter resistors 25 or 26 of transistors T 5 and T 6 .

    Enfin, l'émetteur du transistor de compensation T22 est couplé à la première borne d'alimentation 9 via une résistance 43 dont la valeur est égale à la deuxième résistance d'émetteur 13 de la cellule 1.Finally, the emitter of the compensation transistor T 22 is coupled to the first supply terminal 9 via a resistor 43 whose value is equal to the second emitter resistor 13 of the cell 1.

    Une capacité 19 de valeur faible et non critique, peut être connectée en parallèle entre le noeud 117 et la base du transistor amplificateur d'erreur T56 de manière à assurer une meilleure stabilité du circuit générateur, à fréquence élevée.A capacitor 19 of low and non-critical value can be connected in parallel between the node 117 and the base of the error amplifier transistor T 56 so as to ensure better stability of the generator circuit, at high frequency.

    Dans une application où le circuit générateur de tension stabilisée fonctionne en permanence, ladite deuxième borne d'alimentation 8 peut être reliée à la source d'alimentation positive Vcc. Toutefois, selon le mode représenté à la figure 1, le circuit générateur de tension stabilisée peut être mis en ou hors fonctionnement au moyen d'un dispositif interrupteur 11 disposé en série entre la source d'alimentation proprement dite 10 portée au potentiel positif Vcc et le conducteur qui a été appelé deuxième borne d'alimentation 8.In an application where the voltage generator circuit stabilized works continuously, said second terminal 8 can be connected to the positive power source Vcc. However, according to the mode shown in Figure 1, the circuit stabilized voltage generator can be switched on or off operation by means of a switch device 11 arranged in series between the power source itself 10 brought to the positive potential Vcc and the conductor which was called second terminal supply 8.

    Le fonctionnement du circuit de la figure 1 est maintenant expliqué brièvement.The operation of the circuit of figure 1 is now explained briefly.

    Lors de la mise sous tension de la borne d'alimentation 8, un courant IS se partage tout d'abord en deux portions I1 et I2 en fonction des résistances de collecteur 14, 15 d'une part et 16, 17 d'autre part. Le courant I1 se partage à son tour d'une part en un courant IA entrant dans l'émetteur du transistor T3 et un courant Ipt entrant dans le collecteur du transistor T1. Le courant I2 se partage à son tour en un courant IB entrant dans l'émetteur du transistor T4 et un courant Ipt entrant dans le collecteur du transistor T2.When the supply terminal 8 is energized, a current I S is firstly divided into two portions I 1 and I 2 as a function of the collector resistors 14, 15 on the one hand and 16, 17 d 'somewhere else. The current I 1 is in turn divided on the one hand into a current I A entering the emitter of the transistor T 3 and a current I pt entering the collector of the transistor T 1 . The current I 2 is in turn divided into a current I B entering the emitter of transistor T 4 and a current I pt entering the collector of transistor T 2 .

    Comme on le verra ci-après, la cellule est alimentée de manière à ce que les courants de collecteur du transistor T1 et du transistor T2 soient égaux entre eux.As will be seen below, the cell is supplied in such a way that the collector currents of transistor T 1 and of transistor T 2 are equal to each other.

    En effet, la différence entre les courant entre IA et IB apparaít en sortie de l'étage d'entrée de l'amplificateur à savoir sur le noeud reliant les collecteurs des transistors T3 et T6 différence de courant qui est appliquée à la base du transistor T56. Le courant collecteur du transistor T56 qui est un courant d'erreur amplifié, est appliqué au noeud 117 joignant les bases des transistors T1, T2, T22 et fournit une contre-réaction fixant la tension de ce noeud de manière que les courants Ipt traversant les transistors T1 et T2 soient égaux. Puisque les bases des transistors T3 et T4 sont connectées entre elles, et que les résistances 14, 15 - 16, 17 sont égales entre elles, les courants IA et IB sont sensiblement égaux.Indeed, the difference between the current between I A and I B appears at the output of the input stage of the amplifier namely on the node connecting the collectors of the transistors T 3 and T 6 current difference which is applied to the base of transistor T 56 . The collector current of transistor T 56 which is an amplified error current, is applied to node 117 joining the bases of transistors T 1 , T 2 , T 22 and provides a feedback setting the voltage of this node so that the currents I pt passing through the transistors T 1 and T 2 are equal. Since the bases of the transistors T 3 and T 4 are connected together, and the resistors 14, 15 - 16, 17 are equal to each other, the currents I A and I B are substantially equal.

    Le transistor de compensation T22 a une surface d'émetteur double de celle du transistor T2. Son émetteur est connecté à une résistance d'émetteur 43 de valeur égale à la deuxième résistance d'émetteur 13 de la cellule 1, laquelle est traversée par un courant égal à 2.Ipt. Aussi, le transistor T22 débite-t-il lui aussi, un courant très sensiblement égal à 2.Ipt. Comme la résistance 35 est choisie d'une valeur égale à l'une des résistance 14-17 et que le transistor de polarisation T34 est choisi avec une surface d'émetteur double de celle de l'un des transistors T3 ou T4, il s'ensuit que le courant entrant dans l'émetteur du transistor T34 est très sensiblement égal à 2.IA. Ainsi un autre courant de valeur Is circule à partir de la borne d'alimentation 8 dans la résistance 35.The compensation transistor T 22 has an emitter surface twice that of the transistor T 2 . Its emitter is connected to an emitter resistance 43 of value equal to the second emitter resistance 13 of cell 1, which is crossed by a current equal to 2.I pt . Also, the transistor T 22 also outputs it, a current very substantially equal to 2.I pt . As the resistor 35 is chosen to have a value equal to one of the resistors 14-17 and the bias transistor T 34 is chosen with an emitter surface twice that of one of the transistors T 3 or T 4 , it follows that the current entering the emitter of transistor T 34 is very substantially equal to 2.I A. Thus, another current with a value I s flows from the supply terminal 8 into the resistor 35.

    Comme on le voit, le circuit décrit possède un haut degré de symétrie assurant une compensation élevée des causes d'erreurs résiduelles. La propriété d'une cellule, connue en soi, telle que représentée en 1 est brièvement rappelée :
    En notant Ie(T2) = courant d'émetteur du transistor T2, Ie(T2) = (VT/R12).Loge(m) expression dans laquelle R12 est la valeur de la résistance 12, et VT est égal kT/q, avec k = constante de Boltzmann, T = température absolue, q = charge de l'électron et m = rapport de la surface d'émetteur entre le transistor T1 et le transistor T2, et Loge(m) = logarithme népérien du rapport m. Le courant Ie(T2) est donc un courant proportionnel à la température absolue et le courant collecteur du même transistor, noté Ipt est aussi un courant de même propriété dont la valeur est très voisine de Ie(T2). Comme indiqué précédemment, le transistor de compensation T22, en parallèle sur le transistor T2, est agencé pour débiter un courant égal à 2.Ipt en remarquant que ce transistor T22 a sa base reliée à la base du transistor T2 et son collecteur soumis à une tension qui est identique à la tension collecteur du transistor T2, puisque le courant Is traversant la résistance 35 est très sensiblement égal au courant Is, somme des courants traversant les résistances de collecteur 14, 15 et 16, 17.    As can be seen, the circuit described has a high degree of symmetry ensuring high compensation for the causes of residual errors. The property of a cell, known per se, as shown in 1 is briefly recalled:
    By noting I e (T 2 ) = emitter current of transistor T 2 , I e (T 2 ) = (V T / R 12 ) .Log e (m) expression in which R 12 is the value of resistance 12, and V T is equal kT / q, with k = Boltzmann constant, T = absolute temperature, q = charge of the electron and m = ratio of the surface of emitter between transistor T 1 and transistor T 2 , and Log e (m) = natural logarithm of the ratio m. The current I e (T 2 ) is therefore a current proportional to the absolute temperature and the collector current of the same transistor, denoted I pt is also a current of the same property whose value is very close to I e (T 2 ). As indicated previously, the compensation transistor T 22 , in parallel on the transistor T 2 , is arranged to debit a current equal to 2.I pt by noting that this transistor T 22 has its base connected to the base of the transistor T 2 and its collector subjected to a voltage which is identical to the collector voltage of transistor T 2 , since the current I s passing through the resistor 35 is very substantially equal to the current I s , sum of the currents passing through the collector resistors 14, 15 and 16, 17.

    La tension minimale à appliquer à la borne d'alimentation positive 8 par rapport à la borne d'alimentation négative 9, se déduit aisément du schéma de la figure 1 et peut être évaluée à :
    V(7) + VBE(T34) + R35.Is , expression dans laquelle V(7) est la chute de tension dans le circuit 7, VBE(T34) est la tension émetteur-base du transistor T34, et R35 est la valeur de la résistance 35.
    La chute de tension dans la résistance 35 peut être choisie relativement faible, inférieure à 1 VBE par exemple, mais supérieure à plusieurs VT.    The minimum voltage to be applied to the positive supply terminal 8 with respect to the negative supply terminal 9, can easily be deduced from the diagram in FIG. 1 and can be evaluated at:
    V (7) + V BE (T 34 ) + R 35 .I s , expression in which V (7) is the voltage drop in circuit 7, V BE (T 34 ) is the emitter-base voltage of transistor T 34 , and R 35 is the value of the resistor 35.
    The voltage drop in the resistor 35 can be chosen to be relatively low, less than 1 V BE for example, but more than several V T.

    Ainsi, la tension minimale d'alimentation peut être un peu supérieure à 2.VBE et inférieure, à 3VBE si nécessaire. Lorsqu'un dispositif interrupteur tel que le dispositif 11 est inséré entre la borne d'alimentation 8 et une source 10, de tension Vcc, la tension de cette source peut être égale à la tension précédemment définie ou un peu plus élevée si l'on choisit un dispositif interrupteur 11 ayant une résistance interne propre.Thus, the minimum supply voltage can be a little more than 2.V BE and less, 3V BE if necessary. When a switching device such as the device 11 is inserted between the supply terminal 8 and a source 10, of voltage Vcc, the voltage of this source can be equal to the previously defined voltage or a little higher if one chooses a switch device 11 having its own internal resistance.

    Les propriétés de symétrie du circuit de la figure 1 sont résumées comme suit :
    les transistors PNP T3, T4, T34 fonctionnent avec une tension émetteur/base identique et une densité de courant identique.    The symmetry properties of the circuit in Figure 1 are summarized as follows:
    PNP transistors T 3 , T 4 , T 34 operate with an identical emitter / base voltage and an identical current density.

    Les transistors NPN T1, T2, T22 fonctionnent sous la même tension collecteur/base et, de plus, les transistors T2 et T22 fonctionnent avec la même densité de courant et le même VBE. Les transistors T5 et T6 fonctionnent à toutes conditions de courant identiques puisque le collecteur du transistor T6 est relié à la base du transistor T56 fonctionnant de manière symétrique à l'ensemble des transistors T5 et T6, alors que le transistor T5 a son collecteur connecté à sa base. Ceci reproduit une symétrie totale de fonctionnement pour les transistors T5, T6.The NPN transistors T 1 , T 2 , T 22 operate at the same collector / base voltage and, moreover, the transistors T 2 and T 22 operate with the same current density and the same V BE . The transistors T 5 and T 6 operate at all identical current conditions since the collector of transistor T 6 is connected to the base of transistor T 56 operating symmetrically with all the transistors T 5 and T 6 , while the transistor T 5 has its collector connected to its base. This reproduces a total operating symmetry for the transistors T 5 , T 6 .

    Il s'ensuit aussi que les transistors T3 et T4 fonctionnent à tension collecteur identique.It also follows that the transistors T 3 and T 4 operate at identical collector voltage.

    C'est seulement au noeud 117, portant la tension de sortie Vref, qu'il se produit une différence par rapport à la tension de base des transistors T5 et T6. En effet, la valeur de Vref est de l'ordre de 1,25 Volt, indépendante de la tension d'alimentation. Par contre, la tension base/collecteur des transistors T3 et T4 est en général différente de la tension base/collecteur du transistor T34 bien qu'il soit aisé de prévoir une égalité de tension pour une valeur nominale de la tension d'alimentation. Ainsi le courant collecteur du transistor T34 devrait être un peu inférieur ou supérieur à la somme des courants collecteur des transistors T3 et T4, selon que la chute de tension dans les résistances 25 et 26 a été choisie plus faible ou plus élevée que la chute de tension du circuit 7, et/ou que la tension d'alimentation s'écarte de sa valeur nominale.It is only at node 117, carrying the output voltage Vref, that there is a difference with respect to the base voltage of the transistors T 5 and T 6 . Indeed, the value of Vref is of the order of 1.25 Volts, independent of the supply voltage. On the other hand, the base / collector voltage of the transistors T 3 and T 4 is generally different from the base / collector voltage of the transistor T 34 although it is easy to provide a voltage equality for a nominal value of the voltage of food. Thus the collector current of transistor T 34 should be a little lower or higher than the sum of the collector currents of transistors T 3 and T 4 , depending on whether the voltage drop in resistors 25 and 26 has been chosen lower or higher than the voltage drop of circuit 7, and / or that the supply voltage deviates from its nominal value.

    Toutefois, la configuration de type cascode de l'ensemble des transistors PNP a pour effet de multiplier la résistance de sortie de ces transistors et ceci spécialement lorsqu'on adopte une chute de tension relativement élevée dans les résistances 35, 14-17 c'est-à-dire nettement supérieures à VT.However, the cascode type configuration of all the PNP transistors has the effect of multiplying the output resistance of these transistors and this especially when adopting a relatively high voltage drop in resistors 35, 14-17 is that is to say clearly greater than V T.

    Il peut exister également une différence de tension base/collecteur entre le transistor T56 et les transistors T5, T6, si la tension d'alimentation s'écarte de sa valeur nominale pour laquelle les éléments ont été calculés, mais cette cause d'erreur peut être largement réduite en utilisant des résistances d'émetteur 25, 26, 45, 46 de valeurs suffisamment élevées pour que la chute de tension dans ces résistances, soit > VT, dégénérant ainsi la caractéristique d'émetteur de ces transistors.There may also be a base / collector voltage difference between transistor T 56 and transistors T 5 , T 6 , if the supply voltage deviates from its nominal value for which the elements have been calculated, but this cause d 'error can be greatly reduced by using emitter resistors 25, 26, 45, 46 of sufficiently high values so that the voltage drop in these resistors, is> V T , thus degenerating the emitter characteristic of these transistors.

    Il y a lieu d'observer que tous les courants de base des transistors PNP T3, T4 et T34 étant évacués à travers la même chute de tension du circuit 7, toute variation de cette chute de tension induit le même effet sur les bases de ces transistors. Aussi, le gain en courant de ces transistors peut être relativement faible sans entraíner une erreur très significative sur la tension Vref obtenue.It should be observed that all the base currents of the PNP transistors T 3 , T 4 and T 34 being discharged through the same voltage drop of circuit 7, any variation of this voltage drop induces the same effect on the bases of these transistors. Also, the current gain of these transistors can be relatively low without causing a very significant error on the voltage Vref obtained.

    Les figures 2A, 2B et 2C montrent des exemples de réalisation du bloc 7 de la figure 1 assurant une chute de tension déterminée, voisine de celle d'une jonction polarisée en direct ou un peu supérieure. La valeur de cette chute de tension est choisie principalement en fonction de la tension nominale prévue sur la deuxième borne d'alimentation 8 et des chutes de tension dans les résistances 25, 26, 45, 46. Une valeur préférée est choisie pour assurer, à la tension d'alimentation nominale, une égalité approximative entre la tension Vref du noeud 117 et la tension des collecteurs des transistors T3 et T4. Pour cette tension d'alimentation nominale, le circuit générateur fonctionne alors de manière optimale avec un degré très élevé de symétrie éliminant la majorité des causes d'erreur de second ordre.FIGS. 2A, 2B and 2C show exemplary embodiments of the block 7 of FIG. 1 ensuring a determined voltage drop, close to that of a direct polarized junction or slightly higher. The value of this voltage drop is chosen mainly as a function of the nominal voltage provided on the second supply terminal 8 and of the voltage drops in the resistors 25, 26, 45, 46. A preferred value is chosen to ensure, at the nominal supply voltage, an approximate equality between the voltage V ref of the node 117 and the voltage of the collectors of the transistors T 3 and T 4 . For this nominal supply voltage, the generator circuit then operates optimally with a very high degree of symmetry eliminating most of the causes of second order errors.

    Selon la figure 2A, le circuit 7 se réduit à un transistor bipolaire T7 connecté en diode et polarisé en direct. Selon une variante non représentée, le transistor bipolaire T7 peut être remplacé par un transistor de type MOS à canal N, connecté de manière équivalente, de manière à présenter une chute de tension correspondant à sa tension de seuil. Une chute de tension un peu plus élevée qu'un VBE est alors obtenue, dont le comportement en température est avantageux pour le fonctionnement du circuit générateur.According to FIG. 2A, the circuit 7 is reduced to a bipolar transistor T 7 connected as a diode and directly biased. According to a variant not shown, the bipolar transistor T 7 can be replaced by an N-channel MOS type transistor, connected in an equivalent manner, so as to have a voltage drop corresponding to its threshold voltage. A voltage drop slightly higher than a V BE is then obtained, whose temperature behavior is advantageous for the operation of the generator circuit.

    A la figure 2B, le circuit 7 se présente sous la forme d'un montage, connu en soi, dans lequel un pont de résistances 71, 72 connecte en parallèle avec le trajet collecteur-émetteur d'un transistor NPN T70 dont la base est connectée au point intermédiaire de ce pont de résistances. Ce montage procure une chute de tension proportionnelle à un VBE, le facteur de proportionnalité, plus grand que 1, étant choisi à volonté en fonction des valeurs des résistances 71 et 72.In FIG. 2B, the circuit 7 is in the form of a circuit, known per se, in which a resistance bridge 71, 72 connects in parallel with the collector-emitter path of an NPN T 70 transistor whose base is connected to the intermediate point of this resistance bridge. This arrangement provides a voltage drop proportional to a V BE , the proportionality factor, greater than 1, being chosen at will according to the values of resistors 71 and 72.

    La figure 2C fournit encore un autre exemple de montage utilisable pour le circuit 7 de la figure 1, qui se réduit ici à un pont de résistances 73, 74 connecté entre la deuxième borne d'alimentation 8 (ou la source d'alimentation Vcc) et la masse (borne 9). La chute de tension utilisée pour écouler le courant de base des transistors T3, T4, et T34 est celle se produisant aux bornes de la résistance 74. Certes, cette chute de tension est affectée par des variations de tension d'alimentation, mais ceci de manière favorable puisque la variation de tension aux bornes de la résistance 74, se produit dans le même sens que la variation de la tension émetteur des transistors T3 et T4. La variation des courants IA et IB en fonction des variations de la tension d'alimentation Vcc, se trouve réduite.FIG. 2C provides yet another mounting example usable for the circuit 7 of FIG. 1, which is reduced here to a resistor bridge 73, 74 connected between the second power supply terminal 8 (or the power source Vcc) and the mass (terminal 9). The voltage drop used to flow the base current of the transistors T 3 , T 4 , and T 34 is that occurring at the terminals of the resistor 74. Admittedly, this voltage drop is affected by variations in supply voltage, but this is favorable since the variation in voltage across the resistor 74 occurs in the same direction as the variation in the emitter voltage of the transistors T 3 and T 4 . The variation of the currents I A and I B as a function of the variations of the supply voltage Vcc is reduced.

    De manière générale, on choisira un circuit 7 fournissant une chute de tension d'autant plus faible, et proche de 1 VBE, que la tension minimale d'alimentation est souhaitée plus faible.In general, a circuit 7 will be chosen which provides a lower voltage drop, the closer to 1 V BE , the lower the minimum supply voltage is desired.

    La figure 3 représente un exemple de réalisation de l'interrupteur 11 de la figure 1. Il est essentiellement constitué d'un transistor T20 à effet de champ à canal P, à enrichissement, dont la source est connectée à la source d'alimentation 10 portant la tension Vcc, à travers une résistance 31, dont le drain est connecté à la borne 8 dite deuxième borne d'alimentation. La grille de ce transistor T20 reçoit par une borne 30 un signal de commande plaçant le transistor soit en conduction soit hors conduction sous l'effet d'une tension de commande variant entre la tension de la masse et la tension Vcc. Dans les explications données à propos de la figure 1, il y a donc lieu de tenir compte de la résistance 31 en série avec la source du transistor T20, ainsi que de la résistance interne de ce transistor. Ces résistances étant ajoutées en série entre la source d'alimentation 10 et ladite deuxième borne d'alimentation 8, provoquent une chute de tension créée par le courant 2.Is.FIG. 3 represents an exemplary embodiment of the switch 11 of FIG. 1. It essentially consists of a P-channel field effect transistor T 20 , with enrichment, the source of which is connected to the power source 10 carrying the voltage Vcc, through a resistor 31, the drain of which is connected to terminal 8 called the second supply terminal. The gate of this transistor T 20 receives via a terminal 30 a control signal placing the transistor either in conduction or out of conduction under the effect of a control voltage varying between the voltage of the ground and the voltage Vcc. In the explanations given with reference to FIG. 1, it is therefore necessary to take account of the resistor 31 in series with the source of the transistor T 20 , as well as of the internal resistance of this transistor. These resistors being added in series between the power source 10 and said second power supply terminal 8, cause a voltage drop created by the current 2.I s .

    La figure 4 fournit un autre exemple de réalisation du dispositif interrupteur 11 de la figure 1, exemple dans lequel est également assurée une pré-régulation du courant (2.Is) alimentant l'amplificateur 2 de la figure 1.FIG. 4 provides another exemplary embodiment of the switch device 11 of FIG. 1, an example in which a pre-regulation of the current (2.I s ) supplying the amplifier 2 of FIG. 1 is also ensured.

    Selon la figure 4, un transistor à effet de champ T40 de type à effet de champ MOS, à canal N, a sa source connectée à la première borne d'alimentation 9, (masse). Sa grille reçoit un signal de commande convenable à partir d'une borne de commande 41. Son drain est couplé à la source d'alimentation 10, à tension Vcc, via une résistance 42 et un transistor T43 de type PNP connecté en diode. Un autre transistor PNP, T44, a sa base connectée à la base du transistor T43 et son émetteur, de surface n fois plus grande que celle de l'émetteur du transistor T43, couplé à la source 10 via une résistance d'émetteur 47. Le collecteur du transistor T44 fournit un courant à la borne 8 dite deuxième borne d'alimentation, dont la valeur déterminée pour une tension Vcc nominale, varie de manière logarithmique, et donc faiblement, lorsque Vcc varie.According to FIG. 4, a field effect transistor T 40 of the MOS field effect type, with N channel, has its source connected to the first supply terminal 9, (ground). Its gate receives a suitable control signal from a control terminal 41. Its drain is coupled to the power source 10, at Vcc voltage, via a resistor 42 and a PNP type transistor T 43 connected as a diode. Another PNP transistor, T 44 , has its base connected to the base of transistor T 43 and its emitter, with an area n times larger than that of the emitter of transistor T 43 , coupled to source 10 via a resistor. emitter 47. The collector of transistor T 44 supplies a current to terminal 8, called the second supply terminal, the value of which is determined for a nominal voltage Vcc, varies logarithmically, and therefore only slightly, when Vcc varies.

    D'une certaine manière, le circuit de la figure 4 est un équivalent de celui de la figure 3 dans lequel la résistance de source 31 aurait une valeur variant dans le même sens que la valeur de Vcc, atténuant ainsi les variations de la tension produite sur la borne 8.In a way, the circuit of figure 4 is a equivalent to that of Figure 3 in which the source resistance 31 would have a value varying in the same direction as the value of Vcc, thus attenuating variations in the voltage produced on terminal 8.

    La figure 5 présente une variante du circuit de la figure 4 selon laquelle c'est un transistor bipolaire T50, de type PNP, qui remplace le transistor T40 de la figure 4, dont le collecteur est connecté à la borne 9 (masse), et dont la base reçoit un signal de commande approprié de la borne de commande 51. L'émetteur du transistor T50 est couplé à la source d'alimentation 10 (Vcc) via une résistance 52 de valeur élevée et le trajet base-émetteur d'un transistor PNP, T53. Entre la résistance 52 et le collecteur de ce transistor T53 est insérée une résistance 54, dont la valeur est choisie pour créer une chute de tension voisine de VT dans les conditions nominales de fonctionnement.FIG. 5 presents a variant of the circuit of FIG. 4 according to which it is a bipolar transistor T 50 , of PNP type, which replaces the transistor T 40 of FIG. 4, the collector of which is connected to terminal 9 (ground) , and the base of which receives an appropriate control signal from the control terminal 51. The emitter of transistor T 50 is coupled to the power source 10 (Vcc) via a resistor 52 of high value and the base-emitter path of a PNP transistor, T 53 . Between the resistor 52 and the collector of this transistor T 53 is inserted a resistor 54, the value of which is chosen to create a voltage drop close to V T under the nominal operating conditions.

    Le collecteur du transistor T53 est connecté à la base d'un autre transistor PNP, T55, dont l'émetteur, de surface n fois plus grande que celle de l'émetteur du transistor T53, est connecté à la source d'alimentation 10.The collector of transistor T 53 is connected to the base of another PNP transistor, T 55 , whose emitter, with an area n times larger than that of the emitter of transistor T 53 , is connected to the source of food 10.

    Le collecteur du transistor T55 délivre un courant prérégulé à la borne 8, dont la valeur varie peu en fonction des variations de Vcc autour de sa valeur nominale, comme dans l'exemple précédent. The collector of transistor T 55 delivers a preset current at terminal 8, the value of which varies little as a function of variations in Vcc around its nominal value, as in the previous example.

    Il est clair que des modifications de détail sont à la portée du spécialiste notamment en ce qui concerne le choix du type des transistors utilisés dans les exemples décrits précédemment, sans sortir du cadre de l'invention.It is clear that details changes are at the scope of the specialist, in particular as regards the choice of type transistors used in the examples described above, without depart from the scope of the invention.

    Par exemple, le circuit de la figure 4 utilise un transistor T40 de type MOS pour la fonction d'interruption de l'alimentation tandis que le circuit de la figure 5 montre un transistor bipolaire T50 pour réaliser la même fonction. Bien entendu, le spécialiste reconnaítra aisément que l'usage de ces types de transistors aurait pu être échangé et qu'ils ne sont nullement spécifiques de chacun des exemples décrits, où un transistor de type NPN aurait pu également être utilisé aisément.For example, the circuit of FIG. 4 uses a transistor T 40 of the MOS type for the power interruption function while the circuit of FIG. 5 shows a bipolar transistor T 50 to perform the same function. Of course, the specialist will easily recognize that the use of these types of transistors could have been exchanged and that they are in no way specific to each of the examples described, where an NPN type transistor could also have been used easily.

    Il est à noter par ailleurs, qu'une fonction de prérégulation du courant d'alimentation a été décrite conjointement avec la fonction d'interruption de l'alimentation, conformément à un mode préféré de réalisation. Toutefois, il est bien clair que ces fonctions peuvent être mise en oeuvre de manière totalement indépendante. Enfin, dans l'exposé de l'invention et pour simplifier son expression, il a été mentionné que les différentes branches du circuit procurent une symétri de fonctionnement par l'égalité des courants qui y circulent, branches qui sont composées de transistors ayant des rapports de surface d'émetteur les plus simples aboutissant à cette égalité de courants. Certes, ce mode de réalisation est préféré pour sa simplicité. Toutefois, le spécialiste reconnaítra qu'un rapport de proportionnalité différent de l'unité peut être également envisagé, (par exemple IA = k.IB , miroir de courant M ayant un rapport sortie/entrée = k, T34 de surface d'émetteur égale à la somme des surfaces de T3 et T4 ...etc...). La valeur de Vref obtenue serait alors différente mais les caractéristiques intrinsèques du circuit de l'invention demeureraient les mêmes, avec les mêmes avantages.It should also be noted that a function for pre-regulating the supply current has been described in conjunction with the function for interrupting the supply, in accordance with a preferred embodiment. However, it is clear that these functions can be implemented completely independently. Finally, in the description of the invention and to simplify its expression, it has been mentioned that the different branches of the circuit provide symmetry of operation by the equality of the currents flowing therein, branches which are composed of transistors having ratios of the simplest emitter area resulting in this equality of currents. Certainly, this embodiment is preferred for its simplicity. However, the specialist will recognize that a proportionality ratio different from the unit can also be envisaged, (for example I A = kI B , current mirror M having an output / input ratio = k, T 34 of emitter surface equal to the sum of the areas of T 3 and T 4 ... etc ...). The value of Vref obtained would then be different but the intrinsic characteristics of the circuit of the invention would remain the same, with the same advantages.

    Claims (6)

    1. A stabilized voltage generator circuit comprising a cell (1) of the band-gap type, in which a plurality of parallel-connected transistors form a compound first transistor (T1) of a first conductivity type, whose emitter is connected to one end of a first emitter resistor (12), the other end of this resistor being connected to the emitter of a second transistor (T2) of the same conductivity type whose emitter area is equal to that of one of the transistors forming the compound first transistor (T1), which second transistor has its base coupled to that of the first transistor, the node between the emitter of the second transistor and the first emitter resistor (12) being coupled to a first supply terminal (9) via a second emitter resistor (13), which circuit further comprises an amplifier (2) acting upon the base of the first and of the second transistor to assure equality of the currents flowing through the first and the second transistor, respectively, the power supply to the collectors of these transistors (T1, T2) being received from a second supply terminal (8), characterized in that the collectors of the first and second transistors are each coupled to the second supply terminal (8) by a first and a second current source (14-15, 16-17), respectively, supplying a current of the same value, in that the amplifier (2) has an input stage comprising two transistors (T3, T4) of a conductivity type opposite to that of the first and second transistors (T1, T2) and having their emitters, of equivalent area, connected to the collectors of the first and second transistors, respectively, having their bases interconnected and coupled to the first supply terminal (9) via a circuit (7) with a given voltage drop, and having their collectors connected to, respectively, the input and the output of a current mirror (M) of unity ratio, comprising transistors (T5, T6) of said first conductivity type and having their emitters coupled to the first supply terminal (9),
      in that the amplifier (2) comprises an output stage which is basically formed by a so-called error-amplifier transistor (T56) of the first conductivity type, by a so-called bias transistor (T34) of the second conductivity type, and by a so-called compensation transistor (T22) of the first conductivity type,
      in that the error-amplifier transistor (T56) has an emitter area equal to twice that of each of the transistors (T5, T6) forming the current mirror (M), has its base connected to the output of the current mirror, has its emitter coupled to the first supply terminal (9), and has its collector connected to the node (117) between the bases of the first (T1) and second (T2) transistors, which node also forms the output (18) of the amplifier and supplies the stabilized output voltage (Vref) of the circuit,
      in that the bias transistor (T34) has an emitter area equivalent to that of the two transistors (T3, T4) of the input stage together, has its emitter coupled to the second supply terminal (8) via a third current source (35) supplying a current equal in value to the sum of the currents of the first and the second current source (14-15), (16-17), has its base connected to the bases of the two transistors (T3, T4) of the input stage, and has its collector connected to the output node (117),
      and in that the compensation transistor (T22) has an emitter area equal to twice that of the second transistor (T2), has its base connected to the output node (117), has its emitter coupled to the first supply terminal (9) via a resistor (43) of a value equal to that of the second emitter resistor (13) of the cell, and has its collector connected to the emitter of the bias transistor (T34).
    2. A circuit as claimed in Claim 1, characterized in that the first and the second current source of the cell (1) are formed by collector resistors (14-15), (16-17) of equal values, while in the amplifier (2) the third current source is formed by another resistor whose value is equal to half that of one of said collector resistors.
    3. A circuit as claimed in Claim 1 or 2, characterized in that each of the transistors (T5, T6) of the current mirror has its emitter coupled to the first supply terminal (9) by means of an emitter resistor (25, 26) of given value, another resistor (45-46) whose value is equal to half said given value coupling the emitter of the error-amplifier transistor (T56) to the same first supply terminal.
    4. A circuit as claimed in any one of the Claims 1 to 3, characterized in that said second supply terminal (8) is coupled to a supply source (10) via a switching device (11) for turning on and turning off the voltage generator circuit.
    5. A circuit as claimed in Claim 4, characterized in that the transistors of the second conductivity type are PNP transistors, the switching device (11) basically comprises a p-channel field-effect transistor (T20) whose gate receives a control signal, whose drain supplies the second supply terminal (8), and whose source is coupled to a positive supply source (10) via a current-limiting resistor (31).
    6. A circuit as claimed in any one of the Claims 1 to 4, characterized in that said second supply terminal (8) is coupled to a supply source (10) via a pre-regulation circuit for the current (2.Is) with which the voltage regulator is supplied, which circuit has an impedance which varies in the same sense as the voltage (Vcc) of the supply source (10).
    EP94202878A 1993-10-13 1994-10-05 Regulated voltage generating circuit of bandgap type Expired - Lifetime EP0649079B1 (en)

    Applications Claiming Priority (2)

    Application Number Priority Date Filing Date Title
    FR9312187A FR2711258A1 (en) 1993-10-13 1993-10-13 Stabilized voltage generator circuit of the bandgap type.
    FR9312187 1993-10-13

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    EP0649079B1 true EP0649079B1 (en) 1998-09-23

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    JP2836547B2 (en) * 1995-10-31 1998-12-14 日本電気株式会社 Reference current circuit
    DE19621110C1 (en) * 1996-05-24 1997-06-12 Siemens Ag Switch-on, switch-off band-gap reference potential supply circuit
    DE19624676C1 (en) * 1996-06-20 1997-10-02 Siemens Ag Circuit arrangement for generation of reference voltage
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    EP0649079A1 (en) 1995-04-19
    JPH07152445A (en) 1995-06-16
    FR2711258A1 (en) 1995-04-21
    DE69413489T2 (en) 1999-05-20
    DE69413489D1 (en) 1998-10-29
    US5488329A (en) 1996-01-30

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